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Baschenis, Félix. "Minimizing resources for regular word transductions." Thesis, Bordeaux, 2017. http://www.theses.fr/2017BORD0810/document.
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Cette thèse a eu pour objectif d'étudier des questions naturelles de définissabilité autour des transducteurs bidirectionnels.Il est bien connu que les transducteurs bidirectionnels définissent une plus grande classe de transductions que celles des transducteurs unidirectionnels. La première question que nous avons étudiée est donc de décider si un transducteur bidirectionnel est définissable par un transducteur unidirectionnel. Il a été montré en 2013 que cette question est décidable pour des transducteurs fonctionnels (nous montrons aussi en paralèlle que cette question devient indécidable si les transducteurs ne sont plus fonctionnels) mais la complexité de la procédure de décision était non-élémentaire.Nous proposons une caractérisation de la "définissabilité par transducteur unidirectionnel" décidable en espace doublement exponentiel. Cette caractérisation est effective en ce sens qu'elle produit en temps triplement exponentiel le transducteur équivalent. De plus, nous avons étudié ce problème aussi pour les transducteurs "sweeping", pour lesquels la procédure de décision et la construction du transducteur équivalent requièrent une exponentielle de moins. Comme nous avons par ailleurs montré qu'il existe des familles de fonctions réalisables de façon unidirectionnelle avec au minimum deux sauts exponentiels, notre procédure est optimale dans le cas "sweeping".Le fait d'avoir particulièrement étudié les transducteurs"sweeping" nous a poussé à étudier d'autres questions dedéfinissabilité~: est-ce qu'un transducteur donné estréalisable par un transducteur sweeping ? Et par un transducteursweeping réalisant au maximum k passages ? Nous montrons que cesquestions sont décidables avec les mêmes complexitésobtenues précédemment. Comme nous avons montré qu'ilexiste une borne sur le nombre de passages nécéssaires pourréaliser avec un transducteur sweeping une transductiondonnée, cela nous permet aussi de minimiser le nombre de passages d'untransducteur sweeping.Enfin nous avons cherché à caractériser la classe destransductions sweeping dans d'autres modèles de transductions,les Streaming String Transducers (SST) et lestransductions MSO. Cela a en autres permis, en établissant unecorrespondance entre le nombre de passages des transducteurssweeping et le nombre de registres d'une sous-classe de SST, deminimiser le nombre de registres pour une classe intéressantede SST. Dans l'ensemble, notre travail a permis de couvrir l'ensembledes relations entre ces modèles, et les questions dedéfinissabilité qui se posent naturellement<br>The goal of this thesis was to study definability questionsabout finite-state transducers and in particular two-waytransducers. It is known that two-way transducers cover a larger classof transductions than one-way transducers. Then the first question wetackled is the one-way definability problem: is it possible torealize a given two-way transduction by a one-way transducer? Thisproblem was shown to be decidable for functionaltransducers (we also show as a side result that one-way definability becomes undecidable for non-functional transducers) but the decision procedure had non-elementary complexity.We proposed a characterization of one-way definability thatallows us to decide it in double-exponential space, and provide anequivalent one-way transducer of triple-exponential size. We firststudied this question for a restricted class, namely sweepingtransducers, for which the decision procedure and the construction ofthe one-way transducer take one less exponential. For suchtransducers, our procedure is optimal in the sense that we have shownthat there exists a family of functions that are one-way definable andfor which an equivalent one-way transducer requires doubly exponentialsize.The study of sweeping transducers raised other definability questions: Is a given transducer equivalent to some sweeping transducer? And to some sweeping transducer that performs at most k passes? We showed that those questions are decidable and the decision procedure, as well as the equivalent transducer, have the same complexity as in the one-way case. Moreover, as we have shown that there exists a bound on the number of passes required to realize a transduction by a sweeping transducer, we managed to obtain a procedure to minimize the number of passes of a sweeping transducer.Finally we tried to characterize sweeping transducers in other models for regular transductions such as Streaming String transducers (SST) and MSO transductions. As we obtained an equivalence between the number of passes of a sweeping transducer and the number of registers of the equivalent SST we provided a minimization procedure for the number of registers of a large class of SST's. To conclude, our work allowed us to provide a good overall understanding of the definability questions between the models for regular transductions and in particular regarding the resources, whether it is the number of passes (and of course one-way definability is crucial in that aspect) or the number of registers
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Götze, Doreen. "Weighted Unranked Tree Automata over Tree Valuation Monoids." Doctoral thesis, Universitätsbibliothek Leipzig, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:15-qucosa-221154.
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Quantitative aspects of systems, like the maximal consumption of resources, can be modeled by weighted automata. The usual approach is to weight transitions with elements of a semiring and to define the behavior of the weighted automaton by mul- tiplying the transition weights along a run. In this thesis, we define and investigate a new class of weighted automata over unranked trees which are defined over valuation monoids. By turning to valuation monoids we use a more general cost model: the weight of a run is now determined by a global valuation function. Besides the binary cost functions implementable via semirings, valuation functions enable us to cope with average and discounting. We first investigate the supports of weighted unranked tree automata over valuation monoids, i.e., the languages of all words which are evalu- ated to a non-zero value. We will furthermore consider the support of several other weighted automata models over different structures, like words and ranked trees. Next we prove a Nivat-like theorem for the new weighted unranked tree automata. More- over, we give a logical characterization for them. We show that weighted unranked tree automata are expressively equivalent to a weighted MSO logic for unranked trees. This solves an open problem posed by Droste and Vogler. Finally, we present a Kleene- type result for weighted ranked tree automata over valuation monoids.
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Suresh, Amrita. "Formal Verification of Communicating Automata." Electronic Thesis or Diss., université Paris-Saclay, 2022. http://www.theses.fr/2022UPASG092.
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Les systèmes distribués concernent des processus qui s’exécutent indépendamment et communiquent de manière asynchrone. Bien qu’ils couvrent un large éventail de cas d’utilisation et soient donc omniprésents dans notre monde, il est particulièrement difficile de garantir leur exactitude. Dans cette thèse, nous modélisons de tels systèmes en utilisant une formulation mathématique et logique, et nousles vérifions algorithmiquement. En particulier, nous nous concentrons sur les automates FIFO (First In First Out), et plus précisément sur des systèmes à un ou plusieurs automates finis qui communiquent via des canaux FIFO fiables pouvant contenir des mots de longueur arbitrairement grande. Comme la plupart des problèmes de vérification sont connus pour être indécidables pour les automates FIFO, nous nous concentrons sur diverses sous-classes et approximations du modèle. Le premier modèle que nous considérons est celui des systèmes de transition bien structurés sur les branches d’états accessibles (branch-WSTS), une classe qui inclut strictement la classe des WSTS. Nous étudions les problèmes de finitude des canaux et de terminaison pour de tels systèmes, et nous en montrons quelques exemples. Nous définissons également une autre classe de systèmes où la condition de monotonie est relâchée et nous montrons qu’une variante du problème de couerture est décidable sous des conditions naturelles d’effectivité. Nous étudions ensuite la restriction de la limitation de l’entrée (input-boundedness) sur les canaux FIFO et nous montrons que l’accessibilité rationnelle et diverses autres propriétés sont décidables pour les automates FIFO. Ce faisant, nous répondons à une question ouverte concernant l’accessibilité des automates FIFO limités en entrée. Nous dérivons également certaines bornes de complexité en considérant le cas le plus simple, un automate FIFO avec un seul canal. Une autre restriction que nous étudions est la synchronisabilité dans les systèmes communicants. En particulier, nous étudions cette notion pour les MSCs (Message Sequence Charts), qui est un modèle pour représenter les exécutions d’un système communicant. Nous montrons que si un ensemble quelconque de MSC satisfait les deux propriétés suivantes, à savoir la définissabilité MSO (Monadic Second-order Logic) et la (spécial) largeur d’arbre (tree-width) bornée, alors la synchronisabilité est décidable. De plus, l’accessibilité et le model checking sont également décidables dans ce cadre. Nous unifions alors certaines classes de la littérature à l’aide de ce cadre, et pour certaines autres classes, nous montrons leur indécidabilité<br>Distributed systems involve processes that run independently and communicate asynchronously. While they capture a wide range of use cases and are hence, ubiquitous in our world, it is also particularly difficult to ensure their correctness. In this thesis, we model such systems using mathematical and logical formulation, and try to algorithmically verify them. In particular, we focus on FIFO (First In First Out) machines, with one or more finite-state machines communicating via unbounded reliable FIFO buffers.As most verification problems are known to be undecidable for FIFO machines, we focus on various subclasses and approximations of the model. The first model we consider are branch-well structured transition systems (branch-WSTS), a class which strictly includes the well-known class of WSTS. We study the problems of boundedness and termination for such systems, and demonstrate some examples of them. We also define another class of systems where the monotony condition is relaxed and show that a variant of the coverability problem is decidable under effectivity conditions.We then study the restriction of input-boundedness on FIFO machines, and show that rational reachability and various other properties are decidable for FIFO machines under the input-bounded restriction. In doing so, we answer a long standing open question regarding the reachability for input-bounded FIFO machines. We also derive some complexity bounds by considering the simplest case, a FIFO machine with a single channel.Another restriction that we study is synchronizability in communicating systems. In particular, we study this notion for MSCs (Message Sequence Charts), which is a model to represent executions of a communicating system. We show that if any set of MSCs can satisfy two properties, namely MSO (Monadic Second-order Logic) definability and bounded (special-)tree width, then synchronizability is decidable. Moreover, reachability and model-checking are also decidable within this framework. We also unify some classes from the literature using this framework, and for some other classes, show their undecidability
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Mohan, Ashwin. "A fuzzy controller developed in RSLogix 5000 using ladder logic and function blocks implemented on a Control Logix PLC /." free to MU campus, to others for purchase, 2004. http://wwwlib.umi.com/cr/mo/fullcit?p1420941.
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Srinivasan, Venkataramanujam. "Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9643.
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The tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the need for high-speed multipliers.
The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power dissipation. The second one is to design high-speed arithmetic circuits, in particular, gigahertz-range multipliers that exploit the many attractive features of the MCML logic style. A small library of MCML gates that form the core components of the multiplier were designed and optimized for high-speed operation. The three 8-bit MCML multiplier architectures designed and simulated in TSMC 0.18 mm CMOS technology are: 3-2-tree architecture with ripple carry adder (Architecture I), 4-2-tree design with ripple carry adder (Architecture II) and 4-2-tree architecture with carry look-ahead adders (Architecture III). Architecture I operates with a maximum throughput of 4.76 GHz (4.76 Billion multiplications per second) and a latency of 3.78 ns. Architecture II has a maximum throughput of 3.3 GHz and a latency of 3 ns and Architecture III has a maximum throughput of 2 GHz and a latency of 3 ns. Architecture I achieves the highest throughput among the three multipliers, but it incurs the largest area and latency, in terms of clock cycle count as well as absolute delay. Although it is difficult to compare the speed of our multipliers with existing ones, due to the use of different technologies and different optimization goals, we believe our multipliers are among the fastest found in contemporary literature.<br>Master of Science
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Maestro, Izquierdo Marcos. "Analysis of the Resistive Switching phenomenon in MOS devices for memory and logic applications." Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/405453.
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En general, la continua evolución de la tecnología ha llevado a afrontar nuevos retos emergentes. En cuanto al campo de la electrónica, uno de los más relevantes ha sido la ley de Moore que postula que "el número de transistores en un circuito integrado se duplica aproximadamente cada dos años". Para cumplir esta ley, la solución ha sido reducir las dimensiones de los dispositivos. Sin embargo, en las últimas décadas se han alcanzado limitaciones físicas debido a que la disminución de las dimensiones está alcanzando el rango atómico. Se han observado además problemas debidos al escalamiento del dispositivo tales como efectos de canal corto en MOSFET. Por ello, la comunidad científica se ha centrado en la exploración de nuevos materiales, alternativas estructuras de dispositivo o diferentes fenómenos que superen los diferentes problemas debidos l escalado.
En cuanto a los fenómenos alternativos, uno de los más relevantes ha sido el fenómeno de Resistive Switching (RS) que ha mostrado características prometedoras para ser implementado en muchas aplicaciones. Este fenómeno se basa en la capacidad de una capa dieléctrica para cambiar su resistencia (o conductividad) entre dos o más valores, que muestran un comportamiento no volátil, bajo la acción de un campo eléctrico. Estas características hacen que este fenómeno sea muy prometedor para su aplicación en: lógica digital, donde surge un nuevo paradigma de computación basado en este fenómeno; en el desarrollo de redes neuronales artificiales, que emulan el comportamiento de la parte neuronal conocida como sinapsis o memoria como la próxima generación de memorias no volátiles.
Sin embargo, a pesar de los grandes esfuerzos de la comunidad científica en la última mitad de siglo, hay varios temas candentes, tales como la comprensión profunda de RS, el análisis de los problemas de fiabilidad que afectan el comportamiento de RS o la investigación sobre nuevas aplicaciones de dispositivos basados en RS, en los que queda mucho trabajo por hacer. Por lo tanto, en esta tesis, se ha estudiado el fenómeno RS tanto a nivel de dispositivo, para analizar el fenómeno en sí mismo, como a nivel de circuito, para analizar su aplicación como memorias y en operaciones digitales.
Inicialmente, el fenómeno se ha estudiado experimentalmente en transistores MOSFET analizando el efecto de la polaridad de tensión aplicada para provocar RS sobre el cambio de resistencia dieléctrica. Además, debido al carácter localizado del fenómeno, se han analizado las diferentes contribuciones involucradas en la conducción a través del dieléctrico y la posibilidad de controlar la localización de dichas contribuciones.
A continuación, se ha estudiado RS en memristores con una capa dieléctrica basada en HfO2. Concretamente, se ha estudiado el fenómeno aplicando rampas de tensión rápidas para provocar los cambios de resistencia con el fin de analizar la influencia de la velocidad de rampa de tensión en los parámetros RS. Además, se han propuesto sistemas experimentales y métodos de caracterización mejorados para analizar el random telegraph noise (RTN) asociado a RS.
Después, se han investigado los memristores con una capa dieléctrica basada en SiO como dispositivos de memoria y selección realizando diferentes análisis DC y AC para corroborar la viabilidad de tales dispositivos para esas aplicaciones.
Finalmente, se han estudiado los memristores como el elemento principal para diseñar puertas lógicas, específicamente, para implementar las puertas lógicas IMPLY y NAND. Se ha llevado a cabo la demostración experimental del funcionamiento de ambas puertas lógicas así como el estudio experimental del comportamiento transitorio de los memristores implicados en la puerta IMPLY con el fin de analizar que sucede durante la operación lógica.<br>In general, the continuous evolution, and improvement, of the technology has led to face new emerging challenges. Regarding the electronic field, one of the most relevant has been the Moore’s law which postulates “the number of transistors in a dense integrated circuit doubles approximately every two years”. To accomplish this postulate, the solution has been reducing the device dimensions. However, in last decades, physical limitations have been reached since device dimensions are in the atomic range. Moreover, problems originated from the device scaling such as short channel effects in MOSFETs have been observed. Consequently, the focus of the scientific community has turned into the exploration of alternative device materials and structures or different phenomena that would overcome the different issues owing to the scaling.
Concerning alternative phenomena, one of the most relevant has been the Resistive Switching (RS) phenomenon which has shown promising features to be implemented in many applications. This phenomenon is based on the capability of a dielectric layer to change its resistance (or conductivity) between two or more values, which show a non-volatile behavior, under the action of an electric field. Overall, these characteristics makes this phenomenon very suitable and promising for its application in digital logic where a new paradigm of computation based on this phenomenon is emerging, in the development of artificial neural networks emulating the behavior of the neuron part known as synapse, and in memory like the next generation of non-volatile memories.
However, despite the great efforts of the scientific community in last half a century, there are several hot topics such as the deeper RS understanding, the analysis of reliability issues affecting RS behavior or the investigation on new applications of RS based devices in which much more work must be done. In this way, the goal of this thesis has been focused on increasing the RS phenomenon knowledge and studying its feasibility for different applications. Hence, RS phenomenon has been study both at device level, to analyze the phenomenon itself, and at circuit level, to analyze its application in memory and digital fields.
Initially, the phenomenon has been experimentally studied on MOSFET transistors analyzing the effect on the dielectric resistance change of the voltage polarity applied to provoke RS. Furthermore, due to the localized character of the phenomenon, the different current contributions involved in the conduction through the dielectric and the control of those current contributions have been analyzed.
Then, RS has been studied on memristors with a dielectric layer based on HfO2. Here, the phenomenon has been studied applying fast voltage ramps to provoke the resistance changes to analyze the influence of the voltage ramp speed on the RS parameters. In addition, enhanced experimental setups and characterization methods have been proposed to analyze the RTN associated to RS.
In addition, memristors with a SiO-based dielectric layer have been investigated as memory and selector devices by performing different DC and pulsed analysis to corroborate the feasibility of such devices for these applications.
Finally, the application of memristors in digital field have been performed. Memristors have been used as the main element to design logic gates, specifically, to implement material implication-based (IMPLY) and NAND gates. Then, the experimental demonstration of both memristor-based logic gates (IMPLY and NAND) performance has been carried out. In addition, the transient behavior of memristors involved in the IMPLY gate have been experimentally studied in order to analyze what happens to memristors during the operation.
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Khordoc, Karim. "A MOS switch-level simulator with delay calculation /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65461.
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Kirawanich, Phumin. "Fuzzy logic control for an active power line conditioner /." free to MU campus, to others for purchase, 2002. http://wwwlib.umi.com/cr/mo/fullcit?p3060114.
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Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183139647.
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Ramirez, Carlos. "Meso-machining of miniature space system components." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2007. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Lindberg, Jordan J. "Language, logic, knowledge, and reality : the logical atomisms of Russell and Wittgenstein /." free to MU campus, to others for purchase, 1997. http://wwwlib.umi.com/cr/mo/fullcit?p9842548.
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Hosseini, Ebrahim. "A multiple-input-single-output, MISO, fuzzy logic model for generation of watershed Soil Conservation Service, SCS, curve numbers." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape15/PQDD_0025/NQ31526.pdf.
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Zeng, Yinghui. "Internet-based fuzzy logic and statistics models for integrated solid waste management planning /." free to MU campus, to others for purchase, 2004. http://wwwlib.umi.com/cr/mo/fullcit?p3164557.
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Choi, Youngsik. "Incorporating robustness into fuzzy logic and mixture decomposition for image enhancement and segementation /." free to MU campus, to others for purchase, 1996. http://wwwlib.umi.com/cr/mo/fullcit?p9737866.
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Ahmed, Mahbub. "Investigation on the flame dynamics of meso-combustors." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Heim, Marcus Edwin Allan. "ANALYSIS OF MOS CURRENT MODE LOGIC (MCML) AND IMPLEMENTATION OF MCML STANDARD CELL LIBRARY FOR LOW-NOISE DIGITAL CIRCUIT DESIGN." DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1422.
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MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented here allows for fast development of mixed signal circuits by providing quiet digital building block gates that reduce the simultaneous switching noise (SSN) by an order of magnitude over conventional CMOS based designs [3]. This thesis project developed the following digital gates in MCML as a standard cell library for general-purpose low noise and very low noise applications: inverter, buffer, NAND, AND, NOR, OR, XOR, NXOR, 2:1 MUX, CMOS to MCML, MCML to CMOS, and double edge triggered flip-flop (DETFF).
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Bice, Jonathon Ray. "Experimental investigation of a meso-scale axial flow pump." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Furtado, Gabriela Firpo. "Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/165167.
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Aborda-se, nesse trabalho, o fenômeno de envelhecimento de transistores MOS por bias temperature instability (BTI), relevante fator de degradação da confiabilidade e de redução do tempo de vida de circuitos integrados CMOS. Uma nova modelagem matemática determinística para BTI é introduzida, proporcionando, rapidamente, informação acerca do desvio na tensão de limiar de um transistor em decorrência da ação de BTI. O modelo é, então, implementado em uma ferramenta comercial SPICE, com o intuito de se verificarem, através de simulações transientes, os efeitos de BTI em circuitos CMOS; nesse sentido, a abordagem determinística representa um enorme avanço em relação à modelagem estocástica tradicional, que, muitas vezes, não pode ser aplicada em simulações transientes de circuitos complexos, devido ao seu vultoso custo computacional. O fenômeno de alargamento de pulso induzido pela propagação (PIPB) de single event transients (SETs), verificado experimentalmente na literatura, é estudado e tido como resultado da ação de BTI nas bordas de subida e descida do pulso transiente. À vista disso, simula-se a propagação de um pulso SET injetado na entrada de uma cadeia de 10000 inversores lógicos de tecnologia PTM bulk 90nm, verificando a dependência do alargamento de pulso com a tensão de alimentação, com o tempo de estresse DC anterior à aplicação do pulso e com a frequência do sinal de entrada. O aumento do atraso de portas lógicas em decorrência da ação de bias temperature instability é abordado, também, através da simulação da aplicação de um pulso nas entradas de uma porta NAND, medindo-se a variação do tempo de atraso de propagação devido à inserção da modelagem matemática para BTI. Utiliza-se novamente o modelo de transistores PTM bulk 90nm, e apuram-se os efeitos da variação da tensão de alimentação e do tempo de estresse DC no tempo de atraso de propagação. Por fim, as disparidades na variação do atraso para as bordas de subida e descida de pulsos lógicos de nível alto-baixo-alto (“101”) e baixo-alto-baixo (“010”) são verificadas, sendo explicadas em termos do diferente impacto de BTI para os períodos de estresse e de relaxação e, também, para transistores PMOS e NMOS.<br>This work addresses the aging of MOS transistors by bias temperature instability (BTI), which is a key factor to the degradation of the reliability and of the lifetime of CMOS integrated circuits. A novel deterministic mathematical model is presented, providing fast information about the impact of BTI in the transistors threshold voltage shifts. The model is implemented in a commercial SPICE tool, in order to verify the effects of BTI in CMOS circuits through transient simulations; in this sense, the deterministic approach represents a great advance compared to the traditional stochastic modelling, that may result in prohibitively long transient simulations for complex circuits, due to its huge computation cost. The phenomenon of propagation induced pulse broadening (PIPB) of single event transients (SETs), verified experimentally in the literature, is studied and understood as the result of the BTI effect on the rising and falling edges of the transient pulse. Therefore, the propagation of a SET injected in the input of a 10,000-inverters chain is simulated, using the PTM bulk 90nm technology model, verifying the dependence of the pulse broadening on the supply voltage, on the DC stress time previous to the application of the pulse and on the input signal frequency. The increase of the propagation delay of logic gates due the action of bias temperature instability is also studied through the simulation of the injection of a pulse in the inputs of a NAND gate, and the variation of the propagation delay time due to the BTI effect is evaluated. The PTM bulk 90nm model is used once again, and the outcome of variations on the supply voltage and on the DC stress time on the propagation delay is measured. Finally, the disparities on the delay variation for the rising and falling edges of high-low-high (“101”) and low-high-low (“010”) input logic pulses are verified, and they are explained as the result of the different impact of BTI for the stress and recovery periods and also for PMOS and NMOS transistors.
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Wasman, Deanna G. "An investigation of algebraic reasoning of seventh- and eighth-grade students who have studied from the Connected mathematics project curriculum /." free to MU campus, to others for purchase, 2000. http://wwwlib.umi.com/cr/mo/fullcit?p9988711.
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Lyaudet, Laurent. "Graphes et hypergraphes : complexités algorithmique et algébrique." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2007. http://tel.archives-ouvertes.fr/tel-00905137.
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Attention, ce résumé comporte un peu d'ironie et d'humour. Dans ce mémoire, nous défendons l'idée selon laquelle, pour tout modèle de calcul raisonnable, ce n'est plus tant le modèle qui compte pour caractériser les classes de complexité importantes que la complexité de la structure combinatoire sous-jacente et en définitive d'un graphe sous-jacent. Pour prendre l'exemple des circuits booléens ou algébriques comme modèles, tout ce qui importe est la complexité du graphe orienté sous-jacent au circuit. Par modèle de calcul raisonnable, nous entendons, comme il se doit, un modèle qui étudié sur une classe de graphes standard nous donne la classe de complexité standard attendue afin de satisfaire aux règles élémentaires des tautologies. On pourrait aussi choisir comme modèles raisonnables les modèles Turing-complet (ou une autre notion de complétude plus adaptée selon les objets calculés), formalisables dans une logique simple (afin d'éviter les "tricheries" et les modèles conçus spécialement pour faire échouer la belle idée défendue). Néanmoins, cette seconde option n'étant pas sans risque, nous nous contentons de la proposer. La thèse défendue est une version un peu plus formalisée et précise mathématiquement de cette idée aux contours un peu flous et qui est donc nécessairement un peu fausse telle quelle.
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Hermosillo, Jesus Manuel. "Acoustic-based localization in wireless sensor networks using MISO Least Squares Estimators." To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2008. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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Jabeur, Kotb. "Ambipolar independent double gate FET (Am -IDGFET) logic design : methods and techniques." Phd thesis, Ecole Centrale de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00777679.
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The continuous growth of global demand for semiconductor products (in a broad range of sectors, such as security, healthcare, entertainment, connectivity, energy, etc.) has been both enabled and fuelled by Moore's law and regular doubling of circuit density and performance increases. However, as CMOS technology scaling begins to reach its theoretical limits, the ITRS predicts a new era known as "Beyond CMOS". Novel materials and devices show an ability to complement or even replace the CMOS transistor or its channel in systems on chip with silicon-based technology. This has led to the identification of promising phenomena such as ambipolar conduction in quasi one- and zero-dimensional structures, for example in carbon nanotubes, graphene and silicon nanowires. Ambipolarity, in a dual-gate context (DG-FETs), means that n- and p-type behavior can be observed in the same device depending on the backgate voltage polarity. In addition to their attractive performances and the low power consumption, ambipolar double gate devices enable the development of completely new circuit structures and design paradigms. Conventional logic synthesis techniques cannot represent the capability of DG-FETs to operate as either n-type or p-type switches and new techniques must be found to build optimal logic. The work in this thesis explores design techniques to enable the use of such devices by defining generic approaches and design techniques based on ambipolar DG-FETs. Two different contexts are tackled: (i) improving standard cell logic design with more compact structures and better performance, as well as low-power design techniques exploiting the fourth terminal of the device, and (ii) adapting conventional logic synthesis and verification techniques such as Binary Decision Diagrams or Function Classification to ambipolar DGFETs in order to build reconfigurable logic cells. The proposed methods and techniques are validated and evaluated in a case study focused on DG-CNTFET through accurate simulations, using the most mature and recent DG-CNTFET model available in the literature.
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Marks, Leonie A. "Evaluating alternative farming systems : a fuzzy MADM approach /." free to MU campus, to others for purchase, 1998. http://wwwlib.umi.com/cr/mo/fullcit?p9924905.
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Li, Hongzheng. "Design of fast algorithms through matrix manipulation for image processing applications /." free to MU campus, to others for purchase, 1999. http://wwwlib.umi.com/cr/mo/fullcit?p9962538.
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Parker, Don James. "A study of the macro to micro process of persuasion for advertising in context towards a meso dominant logic model of consumer behaviour." Thesis, University of South Wales, 2014. https://pure.southwales.ac.uk/en/studentthesis/a-study-of-the-macro-to-micro-process-of-persuasion-for-advertising-in-context-towards-a-meso-dominant-logic-model-of-consumer-behaviour(8a76c8ce-2301-4134-9d8b-489af0136500).html.
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This thesis gains an insight into advertising and integrated marketing communications with an exploration of the relationships between advertisers and consumers at the meso level of interface between the two groups. As an initial investigation into advertising and integrated marketing communications and its relationships to consumers’ behaviour, the inquiry develops by exploring an alternative lineage of interpretive consumer research. The two areas of focus emerging from the literature review are the concepts of manufacturing consent (Herman and Chomsky, 2002) as the macro advertiser/sender level of behaviour and the concept of motivational behaviour research (Tadajewski, 2006) as the micro consumer/receiver level of behaviour. The study utilises a mixed methods research design to explore the interface between advertisers and consumers. From the analysis of the commonalites and variances within the data, a mapping of behaviour between the two groups presented a new and unexpected set of interactions. Interactions that reflect the Foundation Premises within the work of Vargo and Lush (2008) by developing an emergent conceptual model.
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Zhao, Weisheng. "Conception, evaluation and development of the non-volatile programmable logic circuits using the Magnetic Tunnel Junction (MTJ)." Paris 11, 2008. http://www.theses.fr/2008PA112051.
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Ces 20 dernières années, les circuits logiques programmables se sont développés rapidement, notamment grâce à l’avantage présenté par leur reconfigurabilité, leur facilité d’utilisation et le prix réduit de leur procédé de développement. Cependant, la volatilité intrinsèque de leur technologie de réalisation (CMOS) est à l’origine des inconvénients pour ces circuits, tels que : la perte de données en cas de pannes d’alimentation, la latence longue pour initialiser le système à chaque démarrage et la consommation d’énergie en état veille à cause des courants de fuite. Ce dernier point est devenu un défi majeur avec la minimisation des transistors sous 90nm. Ces dernières années, de nombreuses technologies émergentes ont été proposées et explorées pour résoudre ces inconvénients. Parmi celles-ci, les technologies magnétiques, basées sur la spintronique, sont parmi les plus performantes et pratiquement réalisables. Ce travail de thèse porte sur l’étude, la conception, la simulation et la réalisation des circuits reconfigurables combinant une technologie CMOS avancée et les technologies non-volatiles émergentes basées sur la nano-spintronique. Les Jonctions Tunnel Magnétiques (JTM) ont été plus particulièrement étudiées selon plusieurs modes d’écriture (écriture par champ et par transfert de spin). Des circuits hybrides ont été tout d’abord conçus et simulés électriquement. Ils montrent de grands potentiels en terme de vitesse, de non-volatilité et de consommation par rapport aux circuits classiques. Ils permettraient également des nouvelles architectures de calcul et des modes de reconfigurations avancés. Enfin, un prototype a été développé pour démontrer les comportements et performances de ces circuits de la manière physique<br>Over the past 20 years, programmable logic circuits have grown rapidly, particularly through the advantages presented by their reconfigurability, ease of use and low cost of their development process. However, the inherent volatility of CMOS technology based on charge storage is the source of inconvenient for these circuits, such as: data loss in case of power failure, the long latency to initialize the system at each (re) start-up and increasing high standby power due to the leakage currents. This last point has become a major challenge as the shrinking of transistors down to 90nm or below. In recent years, numerous emerging technologies have been proposed and explored to overcome these problems. Among them, Spintronics technology, is among the most efficient and practical solutions. This thesis focuses on the study, design, simulation and implementation of reconfigurable circuits combining CMOS technology and advanced non-volatile emerging technologies based on Nano Spintronics. The Magnetic Tunnel Junction (MTJ) was particularly studied based on three modes of writing such as Spin Transfer Torque (STT). The hybrid circuits were first designed and simulated electrically. They show great potential in terms of speed, non-volatility and power compared to conventional circuits. They would promise also new computing architectures and some advanced reconfiguration methods. Finally, a prototype was developed to demonstrate the behaviour and performance of these circuits
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Braud, Laurent. "The structure of orders in the pushdown hierarchy." Phd thesis, Université Paris-Est, 2010. http://tel.archives-ouvertes.fr/tel-00587409.
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Cette thèse étudie les structures dont la théorie au second ordremonadique est décidable, et en particulier la hiérarchie à pile. Onpeut définir celle-ci comme la hiérarchie pour $n$ des graphesd'automates à piles imbriquées $n$ fois ; une définition externe, partransformations de graphes, est également disponible. Nous nousintéressons à l'exemple des ordinaux. Nous montrons que les ordinauxplus petits que $epsilon_0$ sont dans la hiérarchie, ainsi que des graphesporteurs de plus d'information, que l'on appelle "graphecouvrants''. Nous montrons ensuite l'inverse : tous les ordinaux de lahiérarchie sont plus petits que $epsilon_0$. Ce résultat utilise le fait queles ordres d'un niveau sont en fait isomorphes aux structures desfeuilles des arbres déterministes dans l'ordre lexicographique, aumême niveau. Plus généralement, nous obtenons une caractérisation desordres linéaires dispersés dans la hiérarchie. Dans un troisièmetemps, nous resserons l'intérêt aux ordres de type $omega$ --- les mots infinis --- pour montrer que les mots du niveau 2 sont les motsmorphiques, ce qui nous amène à une nouvelle extension au niveau 3
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Naveh-Benjamin, Yizchak. "Simulating organizational decision-making using a cognitively realistic agent model /." free to MU campus, to others for purchase, 2004. http://wwwlib.umi.com/cr/mo/fullcit?p1420946.
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卓維信 та Wei-Hsin Cho. "MSK 通訊系統效能分析". 碩士, 中華大學, 1997. http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22097CHPI5442035%22.&searchmode=basic.
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Marusiak, David. "MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS." DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.
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Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells.
The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.
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Wood, Diane L. "The influence of abiotic factors on lotic insect communities of submerged rootmats and temporary pools /." free to MU campus, to others for purchase, 1999. http://wwwlib.umi.com/cr/mo/fullcit?p9964013.
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BOGGERO, LUCA. "Design techniques to support aircraft systems development in a collaborative MDO environment." Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710702.
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The aircraft design is a complex multidisciplinary and collaborative process. Thousands of disciplinary experts with different design competences are involved within the whole development process. The design disciplines are often in contrast with each other, as their objectives might be not coincident, entailing compromises for the determination of the global optimal solution. Therefore, Multidisciplinary Design and Optimization (MDO) algorithms are being developed to mathematically overcome the divergences among the design disciplines. However, a MDO formulation might identify an optimal solution, but it could be not sufficient to ensure the success of a project. The success of a new project depends on two factors. The first one is relative to the aeronautical product, which has to be compliant with all the capabilities actually demanded by the stakeholders. Furthermore, a “better” airplane may be developed in accordance with customer expectations concerning better performance, lower operating costs and fewer emissions. The second important factor refers to the competitiveness among the new designed product and all the other competitors. The Time-To-Market should be reduced to introduce in the market an innovative product earlier than the other aeronautical industries. Furthermore, development costs should be decreased to maximize profits or to sell the product at a lower price. Finally, the development process must reduce all the risks due to wrong design choices.
These two main motivations entail two main objectives of the current dissertation. The first main objective regards the assessment and development of design techniques for the integration of the aircraft subsystems conceptual design discipline within a collaborative and multidisciplinary development methodology. This methodology shall meet all the necessities required to design an optimal and competitive product. The second goal is relative to the employment of the proposed design methodology for the initial development of innovative solutions. As the design process is multidisciplinary, this thesis is focused on the on-board systems discipline, without neglecting the interactions among this discipline with all the other design disciplines. Thus, two kinds of subsystems are treated in the current dissertation. The former deals with hybrid-electric propulsion systems installed aboard Remotely Piloted Aerial Systems (RPASs) and general aviation airplanes. The second case study is centered on More and All Electric on-board system architectures, which are characterized by the removal of the hydraulic and/or pneumatic power generation systems in favor of an enhancement of the electrical system.
The proposed design methodology is based on a Systems Engineering approach, according to which all the customer needs and required system functionalities are defined since the earliest phase of the design. The methodology is a five-step process in which several techniques are implemented for the development of a successful product. In Step 1, the design case and the requirements are defined. A Model Based Systems Engineering (MBSE) approach is adopted for the derivation and development of all the functionalities effectively required by all the involved stakeholders. All the design disciplines required in the MDO problem are then collected in Step 2. In particular, all the relations among these disciplines – in terms of inputs/outputs – are outlined, in order to facilitate their connection and the setup of the design workflow. As the present thesis is mainly focused on the on-board system design discipline, several algorithms for the preliminary sizing of conventional and innovative subsystems (included the hybrid propulsion system) are presented. In the third step, an MDO problem is outlined, determining objectives, constraints and design variables. Some design problems are analyzed in the present thesis: un-converged and converged Multidisciplinary Design Analysis (MDA), Design Of Experiments (DOE), optimization. In this regard, a new multi-objective optimization method based on the Fuzzy Logic has been developed during the doctoral research. This proposed process would define the “best” aircraft solution negotiating and relaxing some constraints and requirements characterized by a little worth from the user perspective. In Step 4, the formulation of the MDO problem is then transposed into a MDO framework. Two kinds of design frameworks are here considered. The first one is centered on the subsystems design, with the aim of preliminarily highlighting the impacts of this discipline on the entire Overall Aircraft Design (OAD) process and vice-versa. The second framework is distributed, as many disciplinary experts are involved within the design process. In this case, the level of fidelity of the several disciplinary modules is higher than the first framework, but the effort needed to setup the entire workflow is much higher. The proposed methodology ends with the investigation of the design space through the implemented framework, eventually selecting the solution of the design problem (Step 5).
The capability of the proposed methodology and design techniques is demonstrated by means of four application cases. The first case study refers to the initial definition of the physical architecture of a hybrid propulsion system based on a set of needs and capabilities demanded by the customer. The second application study is focused on the preliminary sizing of a hybrid-electric propulsion system to be installed on a retrofit version of a well-known general aviation aircraft. In the third case study, the two kinds of MDO framework previously introduced are employed to design conventional, More Electric and All Electric subsystem architectures for a 90-passenger regional jet. The last case study aims at minimizing the aircraft development costs. A Design-To-Cost approach is adopted for the design of a hybrid propulsion system.
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Poucin, Cyprien. "Borane adsorption on MgO nanoparticles for increased catalytic activity in the cycloaddition of CO2 on epoxides." Electronic Thesis or Diss., Sorbonne université, 2023. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2023SORUS142.pdf.
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La capture et la valorisation du dioxyde de carbone sont devenus des défis majeurs pour les décennies à venir. Les technologies de capture sont déjà suffisamment matures pour être mises en œuvre à l'échelle industrielle, mais les technologies de valorisation font encore défaut. Ce travail de thèse se concentre sur le développement de nouveaux catalyseurs pour la valorisation chimique du CO2. L'introduction bibliographique souligne le potentiel des oxydes alcalino-terreux pour la capture et la valorisation du CO2 en raison de leur capacité à former facilement des carbonates, ainsi que le développement récent de la chimie des Paires de Lewis Frustrées (FLP) pour l'activation de petites molécules comme le CO2. Nous y proposons une stratégie de synthèse de nanoparticules d'oxyde de magnésium fonctionnalisées avec des ligands boranes pour créer une interaction de type FLP à la surface et augmenter l'activité catalytique des nanoparticules dans la cycloaddition du CO2 sur des époxydes. Dans la première partie de ce travail, la synthèse de nanoparticules d'oxyde de magnésium par précipitation-calcination est étudiée. Les paramètres de réaction tels que la température de calcination et les lavages post-synthèse ont un impact sur la morphologie et l'état de surface des nanoparticules. La deuxième partie de ce travail se concentre sur l'adsorption de boranes sur les nanoparticules de MgO avec et sans présence de CO2. La preuve d'une interaction MgO-CO2-BPh3 est apportée par des analyses de spectroscopie infrarouge. Une interaction unique entre MgO et le chloroborane BCl2Ph est mise en évidence par un changement de couleur visuel des nanoparticules ainsi que par spectroscopie infrarouge. La dernière partie de ce travail se concentre sur l'étude catalytique de la réaction de cycloaddition. La comparaison entre les différents catalyseurs MgO confirme l'importance des paramètres de synthèse des nanoparticules sur leur activité. L'adsorption de boranes modifie l'activité et/ou la sélectivité de MgO en fonction du solvant de réaction. L'ajout de BCl2Ph augmente l'activité du catalyseur MgO d'un facteur 10 mais réduit également sa sélectivité vers la formation du carbonate cyclique. L'impact de la température, de la concentration et de la durée de la réaction sur les performances catalytiques de ce couple nanoparticule-ligand est étudié afin de dévoiler l'origine de cette synergie inédite entre MgO et BCl2Ph<br>Carbon dioxide capture and valorisation have become major challenges for the future decades. Capture technologies are already mature enough to start being implemented at industrial scale but valorisation technologies are still lacking. This thesis work focuses on the development of new catalysts for CO2 chemical valorisation. The bibliographic introduction emphasizes the potential alkaline earth oxides for CO2 capture and valorisation due to their ability to easily form carbonates, as well as the recent development of Frustrated Lewis Pair (FLP) chemistry for the activation of small molecules like CO2. We propose a strategy to synthesize magnesium oxide nanoparticles functionalised with borane ligands to create FLP-like interaction at the surface and increase the catalytic activity of the nanoparticles in the cycloaddition of CO2 on epoxides. In the first part of this work, the synthesis of magnesium oxide nanoparticles by precipitation-calcination is studied. Reaction parameters like calcination temperature and post synthesis washings are shown to impact the nanoparticles morphology and surface state. The second part of this work focuses on borane adsorption on MgO nanoparticles with and without presence of CO2. Proof of a MgO-CO2-BPh3 interaction is found using infrared spectroscopy analyses. A unique interaction between MgO and the chloroborane BCl2Ph is evidenced by a visual colour change of the nanoparticles and by infrared spectroscopy. The last part of this work focuses on the catalytic study of the cycloaddition reaction. Comparison between the different MgO catalysts confirmes the importance of the nanoparticles synthesis parameters on their activity. Adsorption of borane modifies the MgO activity and/or selectivity depending on the reaction solvent. The addition of BCl2Ph increases the activity of the MgO catalyst by a factor 10 but also reduces the selectivity toward cyclic carbonate. Impact of temperature, concentration and reaction duration on the catalytic performances of this nanoparticle¬ ligand pair is studied to unveil the origin of this unreported synergy between MgO and BCl2Ph
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Canal, Bruno. "MCML gate design methodology ante the tradeoffs between MCML and CMOS applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/142585.
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Este trabalho propõe uma metodologia de projeto para células digitais MOS Current-Mode Logic (MCML) e faz um estudo da utilização destes circuitos, frente à utilização de células CMOS tradicionais. MCML é um estilo lógico desenvolvido para ser utilizado em circuitos de alta frequência e tem como princípio de funcionamento o direcionamento de uma corrente de polarização através de uma rede diferencial. Na metodologia proposta o dimensionamento inicial da célula lógica é obtido a partir do modelo quadrático de transistores e através de simulações SPICE analisa-se o comportamento da célula e se redimensiona a mesma para obter as especificações desejadas. Esta metodologia considera que todos os pares diferencias da rede de pull-down possuem o mesmo dimensionamento. O objetivo através desta metodologia é encontrar a melhor frequência de operação para uma dada robustez da célula digital. Dimensionamos células lógicas MCML de até três entradas para três tecnologias (XFAB XC06, IBM130 e PTM45). Comparamos os resultados da metodologia proposta com o software comercial de otimização de circuitos, Wicked™, o qual obteve uma resposta de atraso 20% melhor no caso da tecnologia XFAB XC06 e 3% no caso do processo IBM130. Através de simulações de osciladores em anel, demonstramos que a topologia MCML apresenta vantagens sobre as células digitais CMOS estáticas, em relação à dissipação de potência quando utilizada em circuitos de alta frequência e caminhos de baixa profundidade lógica. Também demonstramos, através de divisores de frequência, que estes circuitos quando feitos na topologia MCML podem atingir frequências de operação que em geral são o dobro das apresentadas em circuitos CMOS, além do mais atingem este desempenho com uma dissipação de potência menor que circuitos CMOS. A natureza analógica das células MCML as torna susceptíveis às variações de processo. Variações globais são compensadas pelo aumento dos transistores da PDN, já casos de descasamentos, por não terem um método de compensação, acabam por degradar a confiabilidade do circuito. Na avaliação da área ocupada por célula, a topologia MCML mostrou consumir mais área do que a topologia CMOS.<br>This work proposes a simulation-based methodology to design MOS Current-Mode Logic (MCML) gates and addresses the tradeoffs of the MCML versus static CMOS circuits. MCML is a design style developed focusing in a high-speed logic circuit. This logic style works with the principle of steering a constant bias current through a fully differential network of input transistors. The proposed methodology uses the quadratic transistor model to find the first design solution, through SPICE simulations, make decisions and resizes the gate to obtain the required solution. The method considers a uniform sizing of the pull-down network transistors. The target solution is the best propagation delay for a predefined gate noise margin. We design MCML gates for three different process technologies (XFAB XC06, IBM130 and PTM45), considering gates up to three inputs. We compare the solutions of the proposed methodology against commercial optimization software, Wicked™, that considers different sizing for PDN differential pairs. The solutions of the software results in a 20% of improvement, when compared to the proposed methodology, in the worst case input delay for the XFAB XC06 technology, and 3% in IBM130. We demonstrate through ring oscillators simulations that MCML gates are better for high speed and small logic path circuits when compared to the CMOS static gates. Moreover, by using MCML frequency dividers we obtained a maximum working frequency that almost doubles the frequency achieved by CMOS frequency dividers, dissipating less power than static CMOS circuits. We demonstrate through a reliability analysis that the analog behavior of MCML gates makes them susceptible to PVT variations. The global variations are compensated by the bias control circuits and with the increase of the PDN transistor width. This procedure compensates the gain loss of these transistors in a worst case variation. In other hand, this increasing degrades the propagation delay of the gates. The MCML gates reliability is heavily affected by the mismatching effects. The difference of the mirrored bias current and the mismatching of the differential pairs and the PUN degrade the design yield. The results of the layout extracted simulations demonstrate that MCML gates performs a better propagation delay performance over gates that depend on complexes pull-up networks in standard CMOS implementation, as well as multi-stages static CMOS gates. Considering the gate layout implementation we demonstrate that the standard structures of pull-up and bias current mirror present in the gate are prejudicial for the MCML gate area.
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Nichols, Rebecca Jo. "Biodiversity of aquatic insects in relation to temperate and tropical land use, and the life histories and microhabitat associations of Lotic mayflies /." free to MU campus, to others for purchase, 1996. http://wwwlib.umi.com/cr/mo/fullcit?p9737899.
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Tran, Duc Anh. "Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20132/document.
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L'évolution de la technologie CMOS consiste à la miniaturisation continue de la taille des transistors. Cela permet la réalisation de circuits et systèmes intégrés de plus en plus complexes et plus performants, tout en réduisant leur consommation énergétique, ainsi que leurs coûts de fabrication. Cependant, chaque nouveau noeud technologique CMOS doit faire face aux problèmes de fiabilité, dues aux densités de fautes et d'erreurs croissantes. Par conséquence, les techniques de tolérance aux fautes, qui utilisent des ressources redondantes pour garantir un fonctionnement correct malgré la présence des fautes, sont devenus indispensables dans la conception numérique. Ce thèse étudie une nouvelle architecture hybride tolérante aux fautes pour améliorer la robustesse des circuits et systèmes numériques. Elle s'adresse à tous les types d'erreur dans la partie combinatoire des circuits, c'est-à-dire des erreurs permanentes (« hard errors »), des erreurs transitoires (« SETs ») et des comportements temporels fautifs (« timing errors »). L'architecture proposée combine la redondance de l'information (pour la détection d'erreur), la redondance de temps (pour la correction des erreurs transitoires) et la redondance matérielle (pour la correction des erreurs permanentes). Elle permet de réduire considérablement la consommation d'énergie, tout en ayant une surface de silicium similaire comparée aux solutions existantes. En outre, elle peut également être utilisée dans d'autres applications, telles que pour traiter des problèmes de vieillissement, pour tolérer des fautes dans les architectures pipelines, et pour être combiné avec des systèmes avancés de protection des erreurs transitoires dans la partie séquentielle des circuits logiques (« SEUs »)<br>Evolution of CMOS technology consists in continuous downscaling of transistor features sizes, which allows the production of smaller and cheaper integrated circuits with higher performance and lower power consumption. However, each new CMOS technology node is facing reliability problems due to increasing rate of faults and errors. Consequently, fault-tolerance techniques, which employ redundant resources to guarantee correct operations of digital circuits and systems despite the presence of faults, have become essential in digital design. This thesis studies a novel hybrid fault-tolerant architecture for robustness improvement of digital circuits and systems. It targets all kinds of error in combinational part of logic circuits, i.e. hard, SETs and timing errors. Combining information redundancy for error detection, timing redundancy for transient error correction and hardware redundancy for permanent error corrections, the proposed architecture allows significant power consumption saving, while having similar silicon area compared to existing solutions. Furthermore, it can also be used in other applications, such as dealing with aging phenomenon, tolerating faults in pipeline architecture, and being combined with advanced SEUs protection scheme for sequential parts of logic circuits
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Abouzeid, Fady. "Étude d'architecture et circuiterie digitale dans le régime sous le seuil en technologie submicronique." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0144.
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L'alimentation des circuits à très faible tension, permettant une efficacité énergétique multipliée par 10, répond aux contraintes des applications mobiles, au prix d'une variabilité accrue limitant la prédiction des résultats et nécessitant des efforts et méthodologies de conception spécifiques. Cette thèse associe la conception à très faible tension aux exigences industrielles, et présente le développement de cellules digitales optimisées pour la très faible tension, par une méthodologie indépendante de la technologie. Ces cellules, validées par des mesures sur silicium en technologie CMOS 40 nm, ont conduit à la fabrication d'un circuit numérique, dont le test met en évidence les adaptations permettant d'améliorer le rendement. Enfin, une cellule mémoire a été conçue et optimisée à très faible tension, ainsi que des solutions d'assistance en lecture et en écriture pour renforcer la tolérance à la variabilité. Un démonstrateur 128 kb est fabriqué en 65 nm pour valider ces développements<br>Ultra-low voltage enables to answer the limitations of the wearable mobile applications with an energy efficiency improved by a factor x10, at the price of an increased transistor variability limiting the predictability of the results. In respect with the industrial requirements, this thesis presents the development of logical cells optimized at ultra-low voltage, using a technology independent methodology. These cells, certified then validated by silicon measurements in 40 nm, led to the design of a digital circuit, fabricated on silicon, which analysis highlighted the adaptations needed to enhance the yield and the predictability of the results. At last, a memory cell was developed and optimized at ultra-low voltage. Read and write assist solutions were conceived in order to reinforce the tolerance to variability. A 128 kb memory demonstrator was then fabricated in 65 nm to validate these developments
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Haque, Francia. "Réactivité de nanoparticules d'oxydes d'orientations définies." Electronic Thesis or Diss., Paris 6, 2015. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2015PA066420.pdf.
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La connaissance d’un système gaz/solide requiert l’analyse de l’adsorption, du premier stade jusqu’à saturation. C’est la motivation de l’analyse des surfaces sous vide. L’approche des surfaces divisées est souvent tronquée. Pratiquée à des pressions suffisamment élevées pour être compatible avec un temps de réaction raisonnable, elle ne permet pas l'analyse de la surface nue à la monocouche. L’objectif du présent travail a été d’établir une continuité d’observation par FTIR, de l’UHV à la pression ambiante, de poudres de MgO, ZnO et ZnxMg1-xO exposées à l’eau ou à l’hydrogène. Il a été montré que les fumées de ZnO se comparent à des cristaux présentant les faces (0001), (0001̅), (101̅0), (112̅0), avec un rapport non-polaire/polaire de 75/25. Par FTIR combinée à la photoémission et à la désorption thermique, trois étapes de l’hydroxylation des fumées de MgO ont été identifiées : défauts ponctuels (10-8 mbar), marches (10-6 mbar) puis terrasses (> 10-5 mbar), avec une restructuration qui prouve que l’eau change la structure de surface de MgO. La représentation commune de la surface de MgO par une suite de facettes (100) est mise en cause. Aux faibles teneurs en zinc, l’oxyde mixte ZnxMg1-xO est formé de cristallites cubiques de même structure que MgO. Le zinc en substitution tend à ségréger vers les sites de basse coordinence où il affecte les propriétés d’adsorption d’eau et d’hydrogène. Par ailleurs, le mélange ZnO-MgO obtenu par combustion d’alliage ZnMg offre une possibilité d’application grâce aux propriétés bactéricides de ZnO et de faible toxicité de MgO. L’ensemble des résultats montre la pertinence de l’étude des poudres pratiquée dans les conditions de l’UHV<br>The analysis of adsorption from the first stage to saturation is necessary to understand gas/solid interactions. This is the motivation for surface analysis under vacuum. The common approach of dispersed materials surfaces is incomplete since working pressures, that are high enough to achieve reasonable reaction times, do not allow studies of powder surfaces from bare to fully covered. The aim of the present work is to examine the successive changes of ZnO, MgO and ZnxMg1-xO nanopowders upon exposure to water or hydrogen from UHV to the ambient by FTIR. It is shown that ZnO smokes behave in a same way as a collection of single crystals which exhibit (0001), (0001̅), (101̅0) and (112̅0) faces with a non-polar/polar ratio of 75/25. Combining FTIR with XPS and TPD techniques, three stages of hydroxylation were identified on MgO smokes: point defects (10-8 mbar), steps (10-6 mbar) then terraces (> 10-5 mbar). Results indicate a reorganisation of surface structure showing that water adsorption on MgO(100) is an irreversible process. The common model of MgO as a series of (100) facets is questioned. At low concentrations of zinc, the mixed oxide ZnxMg1-xO consists of crystals with similar structure as MgO. A segregation of Zn2+ toward low coordinated surface sites is suggested to explain the changes in reactivity of the ZnxMg1-xO with respect to water and hydrogen at low coverages. Furthermore, the mixture ZnO-MgO produced by combustion of ZnMg alloy combines the antibacterial properties of ZnO and the biocompatibility of MgO, interesting for potential applications. The overall results demonstrate the relevance of the study of powders in ultra-high vacuum conditions
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Usai, Giulia. "Conception et Fabrication hybride 3D monolithique de relais NEMS co-integrés CMOS." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT069.
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Ce travail de thèse porte sur les relais nano électromécaniques (NEMS en anglais). Afin de surmonter la limite d’efficacité énergétique inhérente à la technologie CMOS, l’utilisation de relais NEMS pour des circuits logiques a été récemment proposée. En effet, les bénéfices cumulés d’un courant nul à l’état bloqué et d’une commutation abrupte permettent d’améliorer le compromis puissance-performance lorsque la tension d’alimentation VDD est réduite.Cependant, les relais NEMS sont limités intrinsèquement par leur endurance, leur fréquence de fonctionnement ainsi que par leur faible densité d’intégration. De ce fait, une approche complémentaire basée sur la co-intégration entre CMOS et relais (mémoire tampon, éléments non volatiles…) plutôt qu’un remplacement semble plus pertinente à court terme. Une intégration 3D monolithique permet l’ajout de tels éléments sur la même surface tout en bénéficiant d’une précision d’alignement lithographique. De plus, pour certains dispositifs (ex. sans couche diélectrique), une plus grande immunité aux radiations ionisantes est attendue, ouvrant des perspectives dans les domaines des applications militaires ou spatiales.En particulier, ce travail de thèse explore les forces et les faiblesses de ces structures et identifie des applications à fort potentiel. Il comprend en outre la conception de prototypes correspondants, depuis leur modélisation et simulation permettant un dimensionnement fonctionnel, le perfectionnement de l’intégration 3D « NEMS sur CMOS », et enfin leurs tests électriques. A la lumière de ces analyses, des recommandations sont fournies pour le développement de circuits hybrides 3D CMOS/NEMS pour la logique et les mémoires avancés<br>This manuscript focuses on Nano-Electro-Mechanical (NEM) relays with electrostatic actuation for advanced logic and memory applications. The use of Nano-Electro-Mechanical relays was recently proposed for digital logic circuits in order to overcome the fundamental energy-efficiency limitations that mainstream CMOS technology is currently facing. The cumulated benefits of essentially Zero Off-State current and ultimately abrupt DC switching characteristics enable alleviating the power-performance trade-off as the supply voltage VDD is reduced. Additionally, for some particular switch designs (e.g. free of dielectric layers), an increased resistance to ionizing radiations is also anticipated, making such components valuable for defense or aerospace applications.However, NEM relays have intrinsic limitations in terms of integration density, endurance and operation frequency. Therefore, rather than considering them as technology that could replace MOSFETs, we adopt an intermediate approach that consists in using NEM relays as a complement to CMOS circuits (e.g.: buffers, non-volatile elements for SRAM and CAM), which can be fabricated in a 3D co-integration scheme. This approach mitigates the area penalty issue.The thesis explores the strength and the weakness of NEMS relays and identifies applications for which hybrid NEMS/CMOS circuits are potentially interesting.This work includes the manufacturing of prototype devices designed to be proof of concept for the identified applications. At first, NV NEM relays design and dimensioning through modelling and simulations was performed. Then NV NEM/CMOS circuits were validated trough simulations. This was followed by the tapeout and the process integration of monolithically co-integrated NEMS above CMOS. After wafer processing the devices were electrically characterized.This all-inclusive works allows identifying some crucial challenges that NEMS relays still have to face
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Dekhissi, Habri. "Etude des performances des technologies HCMOS 3 et HCMOS 4." Grenoble 2 : ANRT, 1987. http://catalogue.bnf.fr/ark:/12148/cb37604368s.
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Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
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Delevoye-Orsier, Elisabeth. "Contribution à la démonstration de faisabilité d'une filière durcie, mixte, sur silicium-sur-isolant." Grenoble INPG, 1993. http://www.theses.fr/1993INPG0043.
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La realisation de circuits complexes, durcis aux effets des rayonnements ionisants, impose le developpement d'une nouvelle technologie, mixte, sur silicium sur isolant reepitaxie, dmill, alliant composants mos et a jonctions et permettant l'integration monolithique de fonctions logiques et analogiques resistantes aux irradiations. Ce memoire presente une analyse approfondie des conditions d'obtention des composants a jonctions, njfet, pjfet et transistors bipolaires verticaux npn et pnp, prenant en compte l'ensemble des contraintes technologiques induites par les methodes de durcissement et par la compatibilite avec les procedes de fabrication des dispositifs cmos. L'etude du procede de fabrication met en evidence une marge de manuvre restreinte mais suffisante pour envisager l'optimisation des differents composants. Les conditions de realisation du polysilicium commun aux grilles mos et aux emetteurs des transistors bipolaires sont etablies. On souligne l'importance du dopage de grille polysilicium dans le durcissement des transistors mos. Les differents niveaux d'implantation disponibles sont communs a plusieurs dispositifs pour reduire la complexite de la technologie, en terme de nombre de niveaux de masquage, a celle d'une filiere bicmos classique. Une fois calibrees, les simulations de procede, a une ou deux dimensions, permettent d'affiner les conditions de realisation. Les caracterisations electriques des composants obtenus, ainsi que la poursuite de l'etude des conditions de realisation mettent en evidence la possibilite d'elaborer une filiere fortement durcie, rapide et bas-bruit, pour laquelle l'optimisation simultanee de six composants est possible. Les caracterisations en bruit des pjfet et des npn permettent de souligner la bonne qualite du procede de fabrication. La complexite globale de la filiere, penalisante lors de la realisation de circuits, est reduite lors du choix, par les concepteurs, des composants les mieux adaptes a l'application parmi les six disponibles. La realisation de six composants optimises, l'etude de leur fiabilite et du rendement de fabrication des circuits constituent les etapes futures du developpement de dmill.
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Deng, Erya. "Conception et développement de circuits logiques de faible consommation et fiables basés sur des jonctions tunnel magnétiques à écriture par transfert de spin." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT012/document.
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Avec la diminution du nœud de la technologie CMOS, la puissance statique et dynamique augmente spectaculairement. It est devenu l'un des principaux problèmes en raison de l'augmentation du courant de fuite et de la longue distance entre les mémoires et les circuits logiques. Au cours des dernières décennies, les dispositifs de spintronique, tels que la jonction tunnel magnétique (JTM) écrit par transfert de spin, sont largement étudiés pour résoudre le problème de la puissance statique grâce à leur non-volatilité. L'architecture logic-in-memory (LIM) hybride permet de fabriquer les dispositifs de spintronique au-dessus des circuits CMOS, réduisant le temps de transfert et la puissance dynamique. Cette thèse vise à la conception de circuits logiques et mémoires pour le système de faible puissance, en combinant les technologies JTM et CMOS. En utilisant un modèle compact JTM et le design-kit CMOS de STMicroelectronics, nous étudions les circuits hybrides MTJ/CMOS de 1-bit et multi-bit, y compris les opérations de lecture et d'écriture. Les méthodes d'optimisation sont également introduites pour améliorer la fiabilité, ce qui est extrêmement important pour les circuits logiques où les blocs de correction d'erreur ne peuvent pas être facilement intégrés sans sacrifier leurs performances ou augmenter la surface de circuit. Nous étendons la structure MTJ/CMOS hybride de multi-bit à la conception d’une mémoire MRAM avec les circuits périphériques simples. Basés sur le concept de LIM, les circuits logiques/arithmétiques non-volatiles sont conçus. Les JTMs sont intégrés non seulement comme des éléments de stockage, mais aussi comme des opérandes logiques. Tout d'abord, nous concevons et analysons théoriquement les portes logiques non-volatiles (PLNVs) comprenant NOT, AND, OR et XOR. Ensuite, les additionneurs complets non-volatiles (ACNVs) de 1-bit et 8-bit sont proposés et comparés avec l'additionneur classique basé sur la technologie CMOS. Nous étudions l'effet de la taille de transistor CMOS et des paramètres de JMT sur les performances d’ACNV. De plus, nous optimisons l’ACNV sous deux faces. Premièrement, un circuit de détection (mode de tension) de très haute fiabilité est proposé. Après, nous proposons de remplacer le JTM à deux électrodes par un JTM à trois électrodes (écrit par transfert de spin assisté par l’effet Hall de spin) en raison du temps d'écriture et de la puissance plus petit. Basé sur les PLNVs et ACNVs, d'autres circuits logiques peuvent être construits, par exemple, soustracteur non-volatile. Enfin, une mémoire adressable par contenu non-volatile (MACNV) est proposée. Deux décodeurs magnétiques visent à sélectionner des lignes et à enregistrer la position de recherche dans un état non-volatile<br>With the shrinking of CMOS (complementary metal oxide semi-conductor) technology, static and dynamic power increase dramatically and indeed has become one of the main challenges due to the increasing leakage current and long transfer distance between memory and logic chips. In the past decades, spintronics devices, such as spin transfer torque based magnetic tunnel junction (STT-MTJ), are widely investigated to overcome the static power issue thanks to their non-volatility. Hybrid logic-in-memory (LIM) architecture allows spintronics devices to be fabricated over the CMOS circuit plane, thereby reducing the transfer latency and the dynamic power dissipation. This thesis focuses on the design of hybrid MTJ/CMOS logic circuits and memories for low-power computing system.By using a compact MTJ model and the STMicroelectronics design kit for regular CMOS design, we investigate the hybrid MTJ/CMOS circuits for single-bit and multi-bit reading and writing. Optimization methods are also introduced to improve the reliability, which is extremely important for logic circuits where error correction blocks cannot be easily embedded without sacrificing their performances or adding extra area to the circuit. We extend the application of multi-context hybrid MTJ/CMOS structure to the memory design. Magnetic random access memory (MRAM) with simple peripheral circuits is designed.Based on the LIM concept, non-volatile logic/arithmetic circuits are designed to integrate MTJs not only as storage elements but also as logic operands. First, we design and theoretically analyze the non-volatile logic gates (NVLGs) including NOT, AND, OR and XOR. Then, 1-bit and 8-bit non-volatile full-adders (NVFAs), the basic elements for arithmetic operations, are proposed and compared with the traditional CMOS-based full-adder. The effect of CMOS transistor sizing and the MTJ parameters on the performances of NVFA is studied. Furthermore, we optimize the NVFA from two levels. From the structure-level, an ultra-high reliability voltage-mode sensing circuit is used to store the operand of NVFA. From the device-level, we propose 3-terminal MTJ switched by spin-Hall-assisted STT to replace the 2-terminal MTJ because of its smaller writing time and power consumption. Based on the NVLGs and NVFAs, other logic circuits can be built, for instance, non-volatile subtractor.Finally, non-volatile content addressable memory (NVCAM) is proposed. Two magnetic decoders aim at selecting a word line to be read or written and saving the corresponding search location in non-volatile state
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Le, Pelleter Tugdual. "Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT043/document.
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Les systèmes embarqués mobiles font partis intégrante de notre quotidien. Afin de les rendre plus adaptésaux usages, ils ont été miniaturisés et leur autonomie a été augmentée, parfois de façon très considérable.Toutefois, les propositions d’amélioration butent désormais sur les possibilités de la technologie des circuitsintégrés. Pour aller plus loin, il faut donc envisager de repenser la chaîne de traitement du signal afin deréduire la consommation de ces dispositifs. Cette thèse développe une approche originale pour exploiterefficacement l’échantillonnage par traversée de niveaux d’une part et, d’autre part, associe cet échantillonnageà une logique évènementielle afin de réduire drastiquement la consommation d’énergie des systèmesintégrés autonomes. Une méthode de discrétisation adaptée à une application de reconnaissance de signauxphysiologiques, utilisée comme exemple dans cette thèse, y est présentée. Un premier prototype en logiqueévènementielle (asynchrone) sur circuit FPGA a permis de valider cette stratégie et de démontrer les bénéficesde cet échantillonnage dédié en termes de réduction de l’activité par rapport à un échantillonnage uniforme.Un second prototype en logique asynchrone et conçu en technologie CMOS AMS 0.35 μm a permis de validerpar simulation électrique un gain extrêmement important sur la consommation électrique du dispositif<br>Our everyday life is highly dependent on mobile embedded systems. In order to make them suitable to differentapplications, they have underwent size reduction and lifetime extension. However, these improvementsare currently limited by the possibilities of the integrated circuits technologies. In order to push back theboundaries, it is necessary to reconsider the whole digital signal processing chain from scratch to sustain thepower consumption reduction in this kind of system. This work develops on the first hand a strategy thatsmartly uses the level-crossing sampling scheme and on the other combines this sampling method with eventlogicto highly reduce the power consumption in mobile embedded systems. A discretisation method adaptedto the recognition of physiological patterns application is described. A first event-logic (asynchronous) prototypeimplemented on FPGA proved the potential benefits that an adapted sampling scheme could offersto reduce activity compared to a uniform sampling scheme. Electrical simulations performed on a secondprototype, also designed in asynchronous logic, with CMOS AMS 0.35 μm technology, validated a high gainin power consumption
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Bertrand, François. "Conception descendante appliquée aux microprocesseurs VLSI." Phd thesis, Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316026.
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Dans la méthode de conception sûre et descendante CAPRI applicable aux circuits intégrés VLSI, on analyse les spécifications initiales à la définition de l'architecture du circuit. La méthode proposée est une méthode par affinements successifs de spécifications dans laquelle on distingue: 1) le choix des algorithmes; 2) le choix du chemin de données associé aux blocs fonctionnels; 3) le choix de la structure de la partie contrôle. Application de la démarche descendante au microordinateur 80 C48 d'INTEL en technologie CMOS
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O'Dorchai, Sile Padraigin. "Family, work and welfare states in Europe: women's juggling with multiple roles :a series of empirical essays." Doctoral thesis, Universite Libre de Bruxelles, 2007. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210592.
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The general focus of this thesis is on how the family, work and the welfare system are intertwined. A major determinant is the way responsibilities are shared by the state, the market and civil society in different welfare state regimes. An introductory chapter will therefore be dedicated to the development of the social dimension in the process of European integration. A first chapter will then go deeper into the comparative analysis of welfare state regimes, to comment on the provision of welfare in societies with a different mix of state, market and societal welfare roles and to assess the adequacy of existing typologies as reflections of today’s changed socio-economic, political and gender reality. Although they stand strong on their own, these first two chapters also contribute to contextualising the research subject of the remainder of the thesis: the study and comparison of the differential situation of women and men and of mothers and non-mothers on the labour markets of the EU-15 countries as well as of the role of public policies with respect to the employment penalties faced by women, particularly in the presence of young children. In our analysis, employment penalties are understood in three ways: (i) the difference in full-time equivalent employment rates between mothers and non-mothers, (ii) the wage penalty associated with motherhood, and (iii) the wage gap between part-time and full-time workers, considering men and women separately. Besides from a gender point of view, employment outcomes and public policies are thus assessed comparatively for mothers and non-mothers. Because women choose to take part in paid employment, fertility rates will depend on their possibilities to combine employment and motherhood. As a result, motherhood-induced employment penalties and the role of public policies to tackle them should be given priority attention, not just by scholars, but also by politicians and policy-makers.<br>Doctorat en Sciences économiques et de gestion<br>info:eu-repo/semantics/nonPublished
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Märcker, Steffen. "Charakterisierung erkennbarer Baumreihen über starken Bimonoiden durch gewichtete MSO-Logik." 2010. https://ul.qucosa.de/id/qucosa%3A16489.
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Endliche Wortautomaten ermöglichen es, reguläre Wortsprachen sowohl zu erkennen als auch zu erzeugen. Julius Richard Büchi gelang es, diese erkennbaren Wortsprachen mithilfe der monadischen Logik zweiter Stufe, kurz MSO, zu charakterisieren [7, 19]. Dieses Ergebnis wurde dann auf erkennbare Baumsprachen, das heißt Mengen von geordneten Bäumen, die durch einenAufwärtsbaumautomaten erkannt werden, erweitert [11, 28]. Anstelle der <-Relation auf den Positionen eines Wortes tritt dabei die Kindrelation edgei(x; y) für die Positionen eines Baumes. Die erkennbaren Wort- und Baumsprachen haben breite Anwendung in der Informatik gefunden. Zu den bekanntesten gehören beispielsweise reguläre Ausdrücke und Syntaxbäume vieler Programmiersprachen. Im Zusammenspiel mit XML ist die Schemasprache RelaxNG zur Dokumentvalidierung [9, 29], im Gegensatz zu XML-Schema, durch die reiche Theorie erkennbarer Baumsprachen
fundiert.
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Götze, Doreen. "Weighted Unranked Tree Automata over Tree Valuation Monoids." Doctoral thesis, 2016. https://ul.qucosa.de/id/qucosa%3A15442.
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Quantitative aspects of systems, like the maximal consumption of resources, can be modeled by weighted automata. The usual approach is to weight transitions with elements of a semiring and to define the behavior of the weighted automaton by mul- tiplying the transition weights along a run. In this thesis, we define and investigate a new class of weighted automata over unranked trees which are defined over valuation monoids. By turning to valuation monoids we use a more general cost model: the weight of a run is now determined by a global valuation function. Besides the binary cost functions implementable via semirings, valuation functions enable us to cope with average and discounting. We first investigate the supports of weighted unranked tree automata over valuation monoids, i.e., the languages of all words which are evalu- ated to a non-zero value. We will furthermore consider the support of several other weighted automata models over different structures, like words and ranked trees. Next we prove a Nivat-like theorem for the new weighted unranked tree automata. More- over, we give a logical characterization for them. We show that weighted unranked tree automata are expressively equivalent to a weighted MSO logic for unranked trees. This solves an open problem posed by Droste and Vogler. Finally, we present a Kleene- type result for weighted ranked tree automata over valuation monoids.
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Wang, Chi-Shong, and 王啟雄. "A MSG-BASED DESIGN FLOW AUGMENTING LOGIC-PHYSICAL CO-SYNTHESIS." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/51998420682943968190.
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博士<br>國立中正大學<br>電機工程所<br>94<br>Traditionally, in order to simplify the highly complex design flow of VLSI chip, EDA tools often separated the flow of chip design into distinctive stages, such as high level synthesis, logic synthesis, and physical design, etc. However, those mutually un-related phases of design are increasingly incapable to handle the much complicated problems encountered in the deep submicron SOC era, in which the dominant factor affecting performance of the chip is mainly on the wire delays instead of the gate delays. As a result, a new design paradigm that simultaneously considers the properties of different design stages is popular in recent years. This dissertation investigates the integration of logic synthesis and physical design for performance improvement of combinational circuits. The pivot concept used in our approach for the logic-physical co-synthesis is a technique of circuit partitioning called maximal super-gates (MSGs).
In the logic aspect of co-synthesis, first, with the help of MSG partitioning, the circuit can be transformed to a globally trees locally non-trees structure, which contrasts with the locally trees globally non-trees structure in traditional tree-based technology mapping. This structure enables us to globally perform dynamic programming technology mapping on the circuit. Besides, by way of delay analysis, the nodes in circuit can be divided into two groups, the ones belonging to the timing critical MSGs and the others belonging to the timing non-critical MSGs. This separation of nodes allows the individual MSG to be manipulated in different way. In our approach, the nodes belonging to timing critical MSGs are matched in a way allowing gate duplication to reduce the circuit delay, while those belonging to the timing non-critical MSGs are matched without duplication to minimize the area penalty. In addition, to enrich the design space for the technology mapping, graph matching instead of tree matching can be applied in each MSG, while the partitions per se can largely alleviate the computational complexity problem imposed by the graph-matching algorithm. Experimental results on the ISCAS’85 benchmarks show that our approach delivers an average of 20.6% reduction on delay with only 9.5% increase on area.
In the physical design aspect of co-synthesis, two salient characteristics of MSG partitioning are especially valuable. First, the MSG forms a natural cluster of circuit, i.e., the strongly connected wires are confined in the MSGs. Second, the inputs to MSG are mutually logic independent. The former property relieves the burden of placement tools whose goal is set to place the close connected cells together and the latter property provides more degrees of freedom to place the input blocks of MSGs. In this dissertation, we propose a dynamic programming mechanism for placement algorithm, which solves the standard cell placement for the combinational circuit of random logic. During the post-order traversal of MSG trees, the MSG blocks are treated as soft macro-cells and a design space exploration algorithm is invoked to generate a variety of design alternatives for the MSGs. The final placement of the circuit is determined in the pre-order traversal process, which picks the best implementation of placements and runs a row-merging algorithm to merge the row placement with that of its parent MSG block. Although we have not yet finished the experiments, we believe that the proposed dynamic programming approach is very promising for the performance driven standard cell placement.
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Lou, Shao-Wei, and 樓紹緯. "Effect of alumina content on the liquid properties and foaming life of FeO-2.5CaO/SiO2-xAl2O3-MgO-MnO slag system." Thesis, 2019. http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22107NCHU5159035%22.&searchmode=basic.
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碩士<br>國立中興大學<br>材料科學與工程學系所<br>107<br>In this study, the carbon was replaced by scrap aluminum except for the foaming process, and then the manipulation was improved to reduce CO2 emission. The effects of different contents of Al2O3 (5.1-18.3wt. %) and FeO (30.2-11.4wt. %) in the slag system of 2.5(CaO/SiO2)-5MgO-5MnO-xAl2O3-FeO on the high temperature characteristics were investigated. After confirming the composition of each slag by XRF and FeO chemical wet titration, each high temperature property of oxygen slag was tested. The fluidity and melting process of the molten slag were analyzed by the viscosity and high temperature dynamic image. Finally, they are combined with foaming operation and dephosphorization test. The research found out the best proportion of Al2O3 in slag, and the benefits of Al2O3 in liquid slag were explained by XRD, ESCA and CFD simulation.
The reduction stage of FeO only took 3 minutes and had a strong exothermic reaction with aluminum. It showed that the crystalline phases of the slags were Ca2SiO4 and FeO phases from the XRD results. With the increase of Al2O3 content, Ca2Al2Si2O7 phases began to appear and FeO remained a single phase. It showed that if A1 group was used as the control group, the increase of Al2O3 content in slag would not inhibit the dephosphorization efficiency. The results of high temperature dynamic image and viscosity analysis showed that increasing the content of alumina in slag was helpful to reduce the melting point of slag. The higher Al2O3 content of the slag at 1550"℃" , the lower surface tension was. In addition, the liquid bonding gradually changed from simple structure to complex network structure.