Tesis sobre el tema "MOSFETs"
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Amberetu, Mathew Atekwana. "Lateral superjunction power MOSFETs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63012.pdf.
Texto completoDharmawardana, Kahanawita Gamaethiralalage Padmapani. "High performance power MOSFETs". Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621963.
Texto completoSyme, Richard Travers. "Thermal transport in MOSFETs". Thesis, University of Cambridge, 1989. https://www.repository.cam.ac.uk/handle/1810/283665.
Texto completoFard, A. M. "Hot electron currents in MOSFETs". Thesis, University of Surrey, 1994. http://epubs.surrey.ac.uk/843618/.
Texto completoWang, Ping. "Wide band noise in MOSFETs". Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/12345.
Texto completoChen, Xiangdong. "Bandgap engineering in vertical MOSFETs". Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3025006.
Texto completoIqbal, M. M. H. "On the static performance of lateral high voltage MOSFETs and novel nanoscale accumulation mode MOSFETs". Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604944.
Texto completoLu, Huaxin. "Compact modeling of Double-Gate MOSFETs". Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3237382.
Texto completoTitle from first page of PDF file (viewed December 8, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 138-143).
Herrmann, Tom. "Simulation und Optimierung neuartiger SOI-MOSFETs". Doctoral thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-63173.
Texto completoChen, Chih-Hung. "High-frequency noise modeling of MOSFETs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/mq24106.pdf.
Texto completoZhang, Wei Dong. "Defect generation and characterization in MOSFETs". Thesis, Liverpool John Moores University, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.275794.
Texto completoZhao, Yinpeng. "Simulation and optimisation of SiGe MOSFETs". Thesis, University of Glasgow, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.368584.
Texto completoKhakifirooz, Ali. "Transport enhancement techniques for nanoscale MOSFETs". Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/42907.
Texto completoThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (p. 155-183).
Over the past two decades, intrinsic MOSFET delay has been scaled commensurate with the scaling of the dimensions. To extend this historical trend in the future, careful analysis of what determines the transistor performance is required. In this work, a new delay metric is first introduced that better captures the interplay of the main technology parameters, and employed to study the historical trends of the performance scaling and to quantify the requirements for the continuous increase of the performance in the future. It is shown that the carrier velocity in the channel has been the main driver for the improved transistor performance with scaling. A roadmapping exercise is presented and it is shown that new channel materials are needed to lever carrier velocity beyond what is achieved with uniaxially strained silicon, along with dramatic reduction in the device parasitics. Such innovations are needed as early as the 32-nm node to avoid the otherwise counter-scaling of the performance. The prospects and limitations of various approaches that are being pursued to increase the carrier velocity and thereby the transistor performance are then explored. After introducing the basics of the transport in nanoscale MOSFETs, the impact of channel material and strain configuration on electron and hole transport are examined. Uniaixal tensile strain in silicon is shown to be very promising to enhance electron transport as long as higher strain levels can be exerted on the device. Calculations and analysis in this work demonstrate that in uniaxially strained silicon, virtual source velocity depends more strongly on the mobility than previously believed and the modulation of the effective mass under uniaxial strain is responsible for this string dependence.
(cont) While III-V semiconductors are seriously limited by their small quantization effective mass, which limits the available inversion charge at a given voltage overdrive, germanium is attractive as it has enhanced transport properties for both electrons and holes. However, to avoid mobility degradation due to carrier confinement as well as L - interband scattering, and to achieve higher ballistic velocity, (111) wafer orientation should be used for Ge NFETs. Further analysis in this work demonstrate that with uniaixally strained Si, hole 3 ballistic velocity enhancement is limited to about 2x, despite the fact that mobility enhancement of about 4x has been demonstrated. Hence, further increase of the strain level does not seem to provide major increase in the device performance. It is also shown that relaxed germanium only marginally improves hole velocity despite the fact that mobility is significantly higher than silicon. Biaxial compressive strain in Ge, although relatively simple to apply, offers only 2x velocity enhancement over relaxed silicon. Only with uniaxial compressive strain, is germanium able to provide significantly higher velocities compared to state-of-the-art silicon MOSFETs. Most recently, germanium has manifested itself as an alternative channel material because of its superior electron and hole mobility compared to silicon. Functional MOS transistors with relatively good electrical characteristics have been demonstrated by several groups on bulk and strained Ge. However, carrier mobility in these devices is still far behind what is theoretically expected from germanium. Very high density of the interface states, especially close to the conduction band is believed to be responsible for poor electrical characteristics of Ge MOSFETs. Nevertheless, a through investigation of the transport in Ge-channel MOSFETs and the correlation between the mobility and trap density has not been undertaken in the past.
(cont) Pulsed I -V and Q-V measurement are performed to characterize near intrinsic transport properties in Ge-channel MOSFETs. Pulsed measurements show that the actual carrier mobility is at least twice what is inferred from DC measurements for Ge NFETs. With phosphorus implantation at the Ge-dielectric interface the difference between DC and pulsed measurements is reduced to about 20%, despite the fact that effects of charge trapping are still visible in these devices. To better understand the dependence of carrier transport on charge trapping, a method to directly measure the inversion charge density by integrating the S/D current is proposed. The density of trapped charges is measured as the difference between the inversion charge density at the beginning and end of pulses applied to the gate. Analysis of temporal variation of trapped charge density reveals that two regimes of fast and slow charge trapping are present. Both mechanisms show a logarithmic dependence on the pulse width, as observed in earlier literature charge-pumping studies of Si MOSFETs with high- dielectrics. The correlation between mobility and density of trapped charges is studied and it is shown that the mobility depends only on the density of fast traps. To our knowledge, this is the first investigation in which the impact of the fast and slow traps on the mobility has been separated. Extrapolation of the mobility-trap relationship to lower densities of trapped charges gives an upper limit on the available mobility with the present gate stack if the density of the fast traps is reduced further. However, this analysis demonstrates that the expected mobility is still far below what is obtained in Si MOSFETs. Further investigations are needed to analyze other mechanisms that might be responsible for poor electron mobility in Ge MOSFETs and thereby optimize the gate stack by suppressing these mechanisms.
by Ali Khakifirooz.
Ph.D.
Chern, Winston. "Compressively strained Ge trigate p-MOSFETs". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78464.
Texto completoCataloged from PDF version of thesis.
Includes bibliographical references (p. 71-74).
State of the art MOSFET performance is limited by the electronic properties of the material that is being used, silicon (Si). In order to continue performance enhancements, different materials are being studied for the extension of Si CMOS. One of the materials of interest, particularly for p-MOSFETs, is Ge because it has very high intrinsic hole mobility. Further improvements in hole mobility can be achieved by straining the material. At the same time it is important to study strained Ge transport in device architectures such as trigate MOSFETs. These devices offer the potential for better scalability than planar MOSFETs via improved electrostatics. The investigation of hole mobility in strained Ge trigate ("nanowire") p- MOSFETs is the focus of this work. To study the effects of strain on Ge as a p-channel material, Strained Germanium Directly on Insulator (SGDOI) substrates were fabricated. The substrates were strained to ~2.4% using lattice mismatch which originates from the growth of Ge on a relaxed Si₀.₆Ge₀.₄ epitaxial layer. A biaxially strained SGDOI substrate was patterned to form Ge nanowires which were measured by Raman spectroscopy to investigate the strain relaxation from the free surface. Another SGDOI substrate was used for nanowire trigate p-MOSFET fabrication. The semiconductor layer structure for the devices consisted of 10 nm-thick strained-Ge with a 5 nm-thick strained-Si cap. On-chip biaxially strained MOSFETs were compared to asymmetrically strained Ge nanowire devices. Significantly improved mobilities (~2x) were observed for nanowire devices with a width of 49 nm compared to the on-chip biaxially strained Ge controls. These mobilities are ~15x over Si universal hole mobility. The impact of strain on the transport of holes in long channel devices is also studied as a function of nanowire width. Mobility decreased for narrower nanowire MOSFETs, likely associated with increased sidewall line edge roughness scattering in narrow lines.
by Winston Chern.
S.M.
Leedham, Robert John. "High frequency switching with power MOSFETs". Thesis, University of Cambridge, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.627468.
Texto completoCao, Xuezhou. "Subthreshold behaviour of small geometry MOSFETs". Thesis, University of Edinburgh, 1993. http://hdl.handle.net/1842/13306.
Texto completoZhang, Zhikuan. "Source/drain engineering for extremely scaled MOSFETs /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20ZHANG.
Texto completoFlorentín, Matthieu. "Irradiation impact on optimized 4H-SiC MOSFETs". Doctoral thesis, Universitat Politècnica de Catalunya, 2016. http://hdl.handle.net/10803/395187.
Texto completoLas tecnologías de dispositivos de potencia en silicio (Si) han alcanzado una gran madurez. Sin embargo, las limitaciones del Si debidas a sus restricciones mecánicas, térmicas y eléctricas hacen necesario otros materiales semiconductores que puedan competir con el Si y superar sus limitaciones. Este es el caso del Carburo de Silicio (SiC) y del Nitruro de Galio (GaN) que ya comienzan a ser serios competidores del Si debido a sus mejores propiedades físicas. En lo que respecta al SiC, el politipo 4H es el candidato más adecuado para la integración de MOSFETs de potencia debido, entre otros, a los valores del bandgap, campo eléctrico crítico, movilidad volumíca de los electrones y tensión umbral alcanzable. A pesar de estas ventajas teóricas del material, es necesario optimizar cada uno de los procesos tecnológicos involucrados en la fabricación de un MOSFET en SiC para que realmente pueda competir con su contrapartida en Si. Este es el caso del proceso de oxidación para la formación del dieléctrico de puerta. Concretamente, una buena estabilidad de la tensión umbral del componente requiere disminuir la densidad de cargas en la interfase óxido/semiconductor, y mejoras adicionales en la calidad de esta interfase son también necesarias para obtener altos valores de la movilidad de los portadores en el canal de inversión. La solución de los problemas tecnológicos anteriormente enunciados abrirá nuevas perspectivas a las aplicaciones de alta potencia. Este trabajo es una continuación directa del de Aurore Constant. Se centra en dispositivos basados en 4H-SiC, y más específicamente en los procesos de oxidación de puerta, y de sus comportamientos eléctricos en diferente ambientes de trabajo hostiles. Hasta la fecha, la mayor parte de la investigación se ha centrado en la mejora de la calidad de la interfase dióxido de silicio/carburo de silicio (SiO2/SiC). La solución de estos problemas debería permitir el diseño de MOSFETs muy rápidos y con pérdidas de conmutación muy bajas. El objetivo del trabajo previo de Aurore Constant fue encontrar un nuevo procedimiento de limpieza de la superficie antes de realizar la oxidación, y en definir un nuevo proceso de oxidación para la formación del dieléctrico de puerta. Los resultados obtenidos mostraron claras mejoras del comportamiento eléctrico de los componentes. Sin embargo, estamos convencidos que la mejora podría ser aún mayor optimizando la etapa del recocido post-oxidación, utilizando un proceso adicional de dopaje superficial, o realizando un adecuado proceso de irradiación. Todos los esfuerzos de este trabajo se han dirigido al desarrollo de MOSFETs en SiC fiables, con mejores características eléctricas, y capaces de trabajar en ambientes de alta temperatura y de irradiación protónica o electrónica. En resumen, las principales líneas de esta Tesis son las siguientes: 1. Estado del arte de los diferentes dominios de trabajo del SiC. 2. Procesos y técnicas de caracterización eléctrica. 3. Impacto de la irradiación de protones en MOSFETs fabricados en 4H-SiC, y descripción teórica de los mecanismos de creación de carga en la interfase SiO2/SiC. 4. Impacto de la irradiación electrónica en MOSFETs fabricados en 4H-SiC. 5. Optimización de los procesos de oxidación y de implantación. 6. Límite de robustez de los procesos tecnológicos optimizados en ámbitos irradiados.
Hosenfeld, Fabian. "NEGF Based Analytical Modeling of Advanced MOSFETs". Doctoral thesis, Universitat Rovira i Virgili, 2017. http://hdl.handle.net/10803/462901.
Texto completoLa corriente túnel de fuente a drenador (SD) disminuye el rendimiento de los dispositivos MOSFETs cuando la longitud del canal cae por debajo de 10 nm. La modelización de los efectos cuánticos incluyendo la corriente túnel SD ha ganado más importancia especialmente para los desarrolladores de modelos compactos. La función de Green de no equilibrio (NEGF) se ha convertido en un método del estado-de-arte para la simulación a nano-escala de los dispositivos en los últimos años. En el sentido de un enfoque de simulación a escala múltiple es necesario cerrar la brecha entre los modelos compactos con su cálculo rápido y eficiente de la corriente, y los modelos numéricos que consideran los efectos cuánticos de los dispositivos de nano escala . En este trabajo, se introduce un modelo analítico basado en NEGF para los MOSFETs de doble compuerta (DG) de nano-escala y FETs de efecto túnel. El modelo consiste en una solución del potencial de forma cerrada a partir de un modelo compacto clásico y un formalismo NEGF 1D para el cálculo de la corriente, teniendo en cuenta los efectos cuánticos. El cálculo del potencial omite el acoplamiento iterativo, lo que permite el cálculo directo de la corriente. El modelo se basa en un enfoque balístico del método NEGF donde los efectos de la retro-dispersión se consideran como de segundo orden de manera simplificada. La precisión y escalabilidad del modelo no iterativo para DG MOSFET se inspecciona en comparación con datos numéricos de simulaciones TCAD nanoMOS para longitudes de canal desde 6 nm hasta 30 nm. Con la ayuda de este modelo se realizan investigaciones sobre los efectos de canal corto y de la temperatura. Los resultados del modelo analítico de FET-túnel se verifican con datos numéricos provenientes de simulaciones TCAD Sentaurus.
Source-to-drain (SD) tunneling decreases the device performance in MOSFETs falling below the 10 nm channel length. Modeling quantum mechanical effects including SD tunneling has gained more importance specially for compact model developers. The non-equilibrium Green's function (NEGF) has become a state-of-the-art method for nano-scaled device simulation in the past years. In the sense of a multi-scale simulation approach it is necessary to bridge the gap between compact models with their fast and efficient calculation of the device current, and numerical device models which consider quantum effects of nano-scaled devices. In this work, a NEGF based analytical model for nano-scaled double-gate (DG) MOSFETs and Tunneling-FETs is introduced. The model consists of a closed-form potential solution of a classical compact model and a 1D NEGF formalism for calculating the device current, taking into account quantum mechanical effects. The potential calculation omits the iterative coupling and allows the straightforward current calculation. The model is based on a ballistic NEGF approach whereby backscattering effects are considered as second order effect in a closed-form. The accuracy and scalability of the non-iterative DG MOSFET model is inspected in comparison with numerical nanoMOS TCAD data for channel lengths from 6 nm to 30 nm. With the help of this model investigations on short-channel and temperature effects are performed. The results of the analytical Tunneling-FET model are verified with numerical TCAD Sentaurus simulation data.
Campbell, John William M. "Reentrant metal-insulator transitions in silicon-MOSFETs". Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/9768.
Texto completoDagenais, Michel R. "Timing analysis for MOSFETS, an integrated approach". Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75459.
Texto completoThe classical simulation approach cannot be used to insure the timing and electrical correctness of the large circuits that are now being designed. The huge number of possible states in large circuits renders this method impractical. Worst-case analysis tools alleviate the problem by restricting the analysis to a limited set of states which correspond to the worst-case operating conditions. However, existing worst-case analysis tools for MOS circuits present several problems. Their accuracy is inherently limited since they use a switch-level model. Also, these procedures have a high computational complexity because they resort to path enumeration to find the latest path in each transistor group. Finally, they lack the ability to analyze circuits with arbitrarily complex clocking schemes.
In this text, a new procedure for circuit-level timing analysis is presented. Because it works at electronic circuit level, the procedure can detect electrical errors, and attains an accuracy that is impossible to attain by other means. Efficient algorithms, based on graph theory, have been developed to partition the circuits in a novel way, and to recognize series and parallel combinations. This enables the efficient computation of worst-case, earliest and latest, waveforms in the circuit, using specially designed algorithms. The new procedure extracts automatically the timing requirements from these waveforms and can compute the clocking parameters, including the maximum clock frequency, for arbitrarily complex clocking schemes.
A computer program was written to demonstrate the effectiveness of the new procedure and algorithms developed. It has been used to determine the clocking parameters of circuits using different clocking schemes. The accuracy obtained on these parameters is around 5 to 10% when compared with circuit-level simulations. The analysis time grows linearly with the circuit size and is approximately 0.5s per transistor, on a microVAX II computer. This makes the program suitable for VLSI circuits.
Paquin, Normand. "Electron transport in uniaxially stressed silicon MOSFETs". Thesis, University of Cambridge, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.257213.
Texto completoBeer, Chris. "Fabrication and characterisation of novel Ge MOSFETs". Thesis, University of Warwick, 2007. http://wrap.warwick.ac.uk/2411/.
Texto completoRazavieh, Ali. "Rf linearity in low dimensional nanowire mosfets". Thesis, Purdue University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3636500.
Texto completoABSTRACT Razavieh, Ali. Ph.D., Purdue University, May 2014. RF Linearity in Low Dimensional Nanowire MOSFETs. Major Professors: Joerg Appenzeller and David Janes. Ever decreasing cost of electronics due to unique scaling potential of today's VLSI processes such as CMOS technology along with innovations in RF devices, circuits and architectures make wireless communication an un-detachable part of everyday's life. This rapid transition of communication systems toward wireless technologies over last couple of decades resulted in operation of numerous standards within a small frequency window. More traffic in adjacent frequency ranges imposes more constraints on the linearity of RF front-end stages, and increases the need for more effective linearization techniques. Long-established ways to improve linearity in DSM CMOS technology are focused on system level methods which require complex circuit design techniques due to challenges such as nonlinear output conductance, and mobility degradation especially when low supply voltage is a key factor. These constrains have turned more focus toward improvement of linearity at the device level in order to simplify the existing linearization techniques. This dissertation discusses the possibility of employing nanostructures particularly nanowires in order to achieve and improve RF linearity at the device level by making a connection between the electronic transport properties of nanowires and their circuit level RF characteristics (RF linearity). Focus of this work is mainly on transconductance (gm) linearity because of the following reasons: 1) due to good electrostatics, nanowire transistors show fine current saturation at very small supply voltages. Good current saturation minimizes the output conductance nonlinearities. 2) non-linearity due to the gate to source capacitances (Cgs) can also be ignored in today's operating frequencies due to small gate capacitance values. If three criteria: i) operation in the quantum capacitance limit (QCL), ii) one-dimensional (1-D) transport, and iii) operation in the ballistic transport regime are met at the same time, a MOSFET will exhibit an ideal linear Id-Vgs characteristics with a constant gm of which is independent of the choice of channel material when operated under high enough drain voltages. Unique scaling potential of nanowires in terms of body thickness, channel length, and oxide thickness makes nanowire transistors an excellent device structure of choice to operate in 1-D ballistic transport regime in the QCL. A set of guidelines is provided for material parameters and device dimensions for nanowire FETs, which meet the three criteria of i) 1-D transport ii) operation in the QCL iii) ballistic transport, and challenges and limitations of fulfilling any of the above transport conditions from materials point of view are discussed. This work also elaborates how a non-ideal device, one that approaches but does not perfectly fulfill criteria i) through iii), can be analyzed in terms of its linearity performance. In particular the potential of silicon based devices will be discussed in this context, through mixture of experiment and simulation. 1-D transport is successfully achieved in the lab. QCL is simulated through back calculation of the band movement of the transistors in on-state. Quasi-ballistic transport conditions can be achieved by cooling down the samples to 77K. Since, ballistic transport is challenging to achieve for practical channel lengths in today's leading semiconductor device technologies the effect of carrier back-scattering on RF linearity is explored through third order intercept point (IIP3) analysis. These findings show that for the devices which operate in the QCL, while 1-D sub-bands are involved in carrier transport, current linearity is directly related to the nature of the dominant scattering mechanism in the channel, and can be improved by proper choice of channel material in order to enforce a specific scattering mechanism to prevail in the channel. Usually, in semiconductors, the dominant scattering mechanism in the channel is the superposition of different mechanisms. Suitable choice of channel material and bias conditions can magnify the effect of a particular scattering mechanism to achieve higher linearity levels. The closing section of this thesis focuses on InAS due to its potential for high linearity since it has small effective mass and large mean-free-path.
Lin, Jianqiang Ph D. Massachusetts Institute of Technology. "InGaAs Quantum-Well MOSFETs for logic applications". Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99777.
Texto completoThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 151-161).
InGaAs is a promising candidate as an n-type channel material for future CMOS due to its superior electron transport properties. Great progress has taken place recently in demonstrating InGaAs MOSFETs for this goal. Among possible InGaAs MOSFET architectures, the recessed-gate design is an attractive option due to its scalability and simplicity. In this thesis, a novel self-aligned recessed-gate fabrication process for scaled InGaAs Quantum-Well MOSFETs (QW-MOSFETs) is developed. The device architectural design emphasizes scalability, performance and manufacturability by making extensive use of dry etching and Si-compatible materials. The fabrication sequence yields precise control of all critical transistor dimensions. This work achieved InGaAs MOSFETs with the shortest gate length (Lg=20 nm), and MOSFET arrays with the smallest contact size (Lc=40 nm) and smallest pitch size (Lp=150 nm), at the time when they were made. Using a wafer bonding technique, InGaAs MOSFETs were also integrated onto a silicon substrate. The fabricated transistors show the potential of InGaAs to yield devices with well-balanced electron transport, electrostatic integrity and parasitic resistance. A device design optimized for transport exhibits a transconductance of 3.1 mS/[mu]m, a value that matches the best III-V high-electron-mobility transistors (HEMTs). The precise fabrication technology developed in this work enables a detailed study of the impact of channel thickness scaling on device performance. The scaled III-V device architecture achieved in this work has also enabled new device physics studies relevant for the application of InGaAs transistors for future logic. A particularly important one is OFF-state leakage. For the first time, this work has unambiguously identified band-to-band tunneling (BTBT) amplified by a parasitic bipolar effect as the cause of excess OFF-state leakage current in these transistors. This finding has important implications for future device design
by Jianqiang Lin.
Ph. D.
Su, Lisa T. (Lisa Tzu-Feng). "Extreme-submicrometer silicon-on-insulator (SOI) MOSFETs". Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/11618.
Texto completoGuo, Alex. "Bias temperature instability (BTI) in GaN MOSFETs". Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/107335.
Texto completoCataloged from PDF version of thesis.
Includes bibliographical references (pages 109-116).
GaN is a promising alternative to Si for transistors for power electronics. For high-voltage applications, the GaN high electron mobility transistor with insulated gate (MIS-HEMT) is an attractive transistor structure because of its high breakdown voltage combined with low gate leakage current. Impressive device performance has recently been reported. However, before GaN MIS-HEMTs cab be deployed in the field, reliability and stability issues need to be solved. In particular, the threshold voltage (VT) instability under high voltage and temperature stress, sometimes referred to as bias-temperature instability (BTI), is a serious concern. The physical mechanisms responsible for BTI in GaN MIS-HEMT are not well understood. This is mainly because of the complex gate stack with multiple layers and interfaces, which presents many trapping sites with complex dynamics. In this work, a simpler GaN MOSFET structure is used to isolate the role of the gate oxide and the oxide/GaN interface in BTI. Using a carefully designed benign characterization approach, we have studied in detail the response to positive and negative gate bias stress of GaN MOSFETs with various gate dielectrics. This has allowed us to postulate relevant physical mechanisms. For positive gate stress (PBTI), positive VT shifts are caused by a combination of electron trapping in pre-existing oxide traps and trap generation either at the oxide/GaN interface (SiO₂/GaN) or in the oxide close to the interface (A1₂O₃/GaN). For negative gate stress (NBTI), three degradation mechanisms are proposed. In low-stress regime, recoverable electron detrapping from pre-existing oxide traps takes place resulting a temporary negative VT shift. In mid-stress regime, a transient positive VT shift is probably caused by electron trapping in the GaN channel under the edges of the gate. In high-stress regime, there is a permanent negative VT shift, which is consistent with interface state generation. In addition, we have confirmed that for benign positive and negative gate bias stress, there is a unified reversible mechanism that accounts for the device dynamics and that is electron trapping/detrapping in pre-existing oxide traps. This work provides fundamental understanding to elucidate the reliability and instability of high-voltage GaN MIS-HEMTs.
by Alex Guo.
Ph. D.
Dragosavac, Marko. "Electron transport in ultrathin oxide silicon MOSFETs". Thesis, University of Cambridge, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.614808.
Texto completoJigang, M. "Defects and lifetime prediction of germanium MOSFETs". Thesis, Liverpool John Moores University, 2015. http://researchonline.ljmu.ac.uk/4587/.
Texto completoChen, Yuhui. "Resonant Gate Drive Techniques for Power MOSFETs". Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/10099.
Texto completoMaster of Science
Xiangxiang, Fang. "Characterization and Modeling of SiC Power MOSFETs". The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1354687371.
Texto completoConstant, Aurore. "SiC oxidation processing technology for MOSFETs fabrication". Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20061.
Texto completoPower electronic devices are mainly based on the mature and very well established silicon technology. However, silicon exhibits some important limitations regarding power losses, operation temperature and speed of switching. Furthermore, unfortunately the successful silicon technology has almost reached its physical limits. Hence, a new generation of power devices based on new materials must be developed to face the future global energetic challenges. Nowadays, the most promising semiconductor material is silicon carbide (SiC). SiC is increasingly considered as the best candidate to overcome the intrinsic limitations of silicon in developing high-power and high-temperature electronic devices. It shows the best trade-off between theoretical characteristics and real commercial availability of the starting material and maturity of its technological processes.This thesis is focused on SiC-based power devices, particularly, on one of the major issues in SiC technology: the gate oxidation process. Indeed, SiC can be easily oxidized to form a thin silicon dioxide (SiO2) layer. This provides a unique opportunity to develop power Metal Oxide Semiconductor (MOS) devices, as in the Si-based technology. SiC-based power MOSFETs are expected to have great potential for high-speed and low-loss switching devices. Unfortunately, the oxide/SiC interface quality and oxide reliability are major barriers to the fabrication of advanced SiC power MOSFET devices. Alternative solutions have been developed to overcome these problems. However, SiC MOSFETs have only been recently commercially available, mainly due to reliability concerns. The MOSFET process suitable for mass production is still a challenge. The main efforts carried out in the framework of this thesis are addressed towards the development of SiC MOSFETs by improving the current gate oxide process state-of-the-art. A newly gate oxidation process based on rapid thermal processing is demonstrated, and the physical mechanisms associated with oxide formation and the SiO2/SiC interface properties are proposed. This oxidation process has been tested on hexagonal SiC (4H-SiC) and cubic SiC (3C-SiC). Furthermore, the investigated oxidation processing technology is integrated into the fabrication of reliable 4H-SiC MOSFETs, and the bias-stress instability has been evaluated up to operating temperatures of 300 ºC
Yu, Bo. "Design and modeling of non-classical MOSFETs". Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3372587.
Texto completoTitle from first page of PDF file (viewed October 22, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 155-163).
Liu, Jingjing Michelle. "Strain induced effects on lateral power MOSFETs". [Gainesville, Fla.] : University of Florida, 2009. http://purl.fcla.edu/fcla/etd/UFE0041290.
Texto completoPande, Peyush. "Characterization of Active Defects in SiC MOSFETs". Thesis, Griffith University, 2020. http://hdl.handle.net/10072/394315.
Texto completoThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Eng & Built Env
Full Text
Zupac, Dragan 1961. "ESD-induced noncatastrophic damage in power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/291470.
Texto completoNEDELJKOVIC, SONJA R. "PARAMETER EXTRACTION AND DEVICE PHYSICS PROJECTIONS ON LATERAL LOW VOLTAGE POWER MOSFET CONFIGURATIONS". University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1005163403.
Texto completoShen, Jian. "Double gate MOSFETs : process variations and design considerations /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20SHEN.
Texto completoHoltij, Thomas. "ANALYTICAL COMPACT MODELING OF NANOSCALE MULTIPLE-GATE MOSFETS". Doctoral thesis, Universitat Rovira i Virgili, 2014. http://hdl.handle.net/10803/284038.
Texto completoEl objetivo principal de este trabajo es el desarrollo de un modelo compacto para MOSFETs de múltiple puerta de escala nanométrica, que sea analítico, basado en la física del dispositivo, y predictivo para simulaciones AC y DC. Los dispositivos investigados son el MOSFET estándar en modo inversión, además de un nuevo dispositivo llamado “junctionless MOSFET” (MOSFET sin uniones). El modelo se desarrolló en una formulación compacta con la ayuda de la ecuación de Poisson y la técnica de transformación conforme de Schwarz-Cristoffel. Se obtuvieron las ecuaciones del voltaje umbral y la pendiente subumbral. Usando la función W de Lambert, además de una función de suavización para la transición entre las regiones de depleción y acumulación, se obtiene un modelo unificado de la densidad de carga, válido para todos los modos de operación del transistor. Se estudian también las dependencias entre los parámetros físicos del dispositivo y su impacto en su rendimiento. Se tienen en cuenta efectos importantes de canal corto y de cuantización. Se discuten también la simetría alrededor de Vds= 0 V, y la continuidad de la corriente de drenador en las derivadas de orden superior. El modelo fue validado mediante simulaciones TCAD numéricas y medidas experimentales.
The main focus is on the development of an analytical, physics-based and predictive DC and AC compact model for nanoscale multiple-gate MOSFETs. The investigated devices are the standard inversion mode MOSFET and a new device concept called junctionless MOSFET. The model is derived in closed-from with the help of Poisson's equation and the conformal mapping technique by Schwarz-Christoffel. Equations for the calculation of the threshold voltage and subthreshold slope are derived. Using Lambert's W-function and a smoothing function for the transition between the depletion and accumulation region, an unified charge density model valid for all operating regimes is developed. Dependencies between the physical device parameters and their impact on the device performance are worked out. Important short-channel and quantization effects are taken into account. Symmetry around Vds = 0 V and continuity of the drain current at derivatives of higher order are discussed. The model is validated versus numerical TCAD simulations and measurement data.
Esteve, Romain. "Fabrication and Characterization of 3C- and4H-SiC MOSFETs". Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-32367.
Texto completoQC 20110415
Upstone, Richard Peter. "Low temperature studies of transport in silicon MOSFETs". Thesis, University of Cambridge, 1986. https://www.repository.cam.ac.uk/handle/1810/265340.
Texto completoChen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS". Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.
Texto completoThomas, Stephen Michael. "Electrical characterisation of novel silicon MOSFETs and finFETs". Thesis, University of Warwick, 2011. http://wrap.warwick.ac.uk/36864/.
Texto completoWaite, Andrew Michael. "Elevated source/drain MOSFETs for deep submicron VLSI". Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299702.
Texto completoChang, Richard T. (Richard Tzewei) 1975. "Physics of high-frequency operation in silicon MOSFETs". Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/47571.
Texto completoIncludes bibliographical references (leaves 66-68).
by Richard T. Chang.
M.Eng.
Lu, Wenjie. "Nano-scale ohmic contacts for III-V MOSFETs". Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/90137.
Texto completo35
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 65-68).
As modem silicon CMOS has been scaled down to extremely small dimensions, there is an urgent need for technological innovations of new devices architectures that would allow the continuation of Moore's Law into the future. In particular, for CMOS with nanometer scale pitch size, the intrinsic electronic properties of silicon as channel material represent a significant hindrance to further scaling. As a result, new channel materials are being investigated all over the world that would enable the push into the sub-10 nm regime. Among them, certain III-V compound semiconductors have emerged as the most promising candidates to replace silicon in future generations of CMOS. In particular and as a result of their extraordinary electron or hole transport properties, InGaAs, InAs, and InGaSb enable transistors with faster operation at a lower power consumption. This is the key to enable future scaling. One of the major challenges of extremely-scaled III-V logic MOSFETs is the series resistance. To achieve the performance goals, it is necessary to fabricate source and drain ohmic contacts with ultra-low contact resistance, perhaps as low as 50 [Omega] · [mu]m. This is particularly difficult to achieve as the device size shrinks down to the 10-20 nm length range since the contact resistance increases drastically for small contact lengths. Moreover, it is not clearly known how to characterize nano-scale metal-semiconductor ohmic contacts. All available test structures and models, such as the transmission line model (TLM), are designed for relatively large ohmic contacts, on the order of micrometers, and are unable to make accurate measurements of extremely small contact resistance. To deal with nano-scale contacts for III-V CMOS, we need a more accurate test structure capable of extracting extremely small values of contact resistance on very small contacts. In this thesis, a novel test structure, nano-TLM, is developed to address this issue. We demonstrate how the nano-TLM is capable of providing accurate measurements of the contact resistance, metal resistance, and semiconductor resistance of an ohmic contact system at the same time. We demonstrate this new technique in Mo/n⁺-InGaAs ohmic contacts where we have achieved an extremely low contact resistance of 32.5 [Omega] · [mu]m with contact length as small as 19 nm. This contact resistance at this contact length is, to the best of our knowledge, the lowest reported value to date. Our proposed new test structure will help understand and characterize ohmic contacts suitable for future III-V CMOS device fabrication.
by Wenjie Lu.
S.M. in Electrical Engineering
Chu, Po-Ju y 朱柏儒. "Investigation of Lateral High Voltage u/p-GaN MOSFETs and InGaN MOSFETs". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/74355390930334410428.
Texto completo國立清華大學
電子工程研究所
99
Lateral high-voltage single RESURF GaN MOSFETs on sapphire substrates were investigated and fabricated, with mesa isolation and Zn implantation isolation to avoid surface leakage. We demonstrated depletion-mode uGaN MOSFETs with a maximum drain current density up to 100mA/mm, a threshold voltage of -3V and a specific on-state resistance of 35mΩ-cm2 when VG=35V. The channel mobility is 26 cm2/Vs extracted from linear region at VDS=0.1V. Furthermore, we have demonstrated enhancement-mode pGaN MOSFETs with a threshold voltage of 2.37V and a maximum drain current density higher than 70mA/mm, a specific on-state resistance as low as 48mΩ-cm2 at VG=35V. The channel mobility of 21 cm2/Vs is extracted from linear region at VDS=0.1V. A pGaN MOSFET with a channel length of 3μm and a RESURF length of 25 μm shows a maximum breakdown voltage up to 120V. A lateral high-voltage InGaN MOSFET has also been investigated attempting to improve the channel mobility of GaN MOSFETs. In the fabrication of InGaN MOSFET, no ion implantation and no sintering for source and drain region was done and all fabrication has been realized at low temperatures. The depletion-mode InGaN HV-MOSFET was fabricated with the maximum breakdown voltage of 380V. The channel mobility measured from a long channel (100μm) device is 93 cm2/Vs.
Jayanarayanan, Sankaran Banerjee Sanjay. "Silicon-based vertical MOSFETs". 2004. http://repositories.lib.utexas.edu/bitstream/handle/2152/2021/jayanarayanans042.pdf.
Texto completoJayanarayanan, Sankaran. "Silicon-based vertical MOSFETs". Thesis, 2004. http://hdl.handle.net/2152/2021.
Texto completoOntalus, Viorel. "Quantum effects in MOSFETs /". Diss., 2000. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:9995563.
Texto completo