Tesis sobre el tema "MOSFET"
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Ngabonziza, Nyampame Christian. "Drivning av Likströmsmotor med MOSFET : DC Motor control by MOSFET". Thesis, Linnéuniversitetet, Institutionen för datavetenskap, fysik och matematik, DFM, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-11294.
Texto completoLui, Jerome C. (Jerome Chun Lung). "Automated MOSFET parameter extraction". Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36583.
Texto completoMajor, Jan. "Počítačové modelování MOSFET tranzistoru". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219148.
Texto completoMunteanu, Daniela. "Modélisation et caractérisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultramince". Grenoble INPG, 1999. http://www.theses.fr/1999INPG0104.
Texto completoShah, Nirav. "Stress modeling of nanoscale MOSFET". [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0012221.
Texto completoProkhorov, Andrey y Olesya Gerzheva. "Model of MOSFET in Delphi". Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-14209.
Texto completoChen, Max Chuan. "Modeling of KTH UTBSOI MOSFET". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177444.
Texto completoHalvledarkomponenter såsom transistorer och integrerade kretsar finns överallt i vår vardag, det är en av de viktigaste grunderna för dagens informationssamhälle. Nanoteknik möjliggör produktion av lättare, snabbare och effektivare komponenter och system. Tillverkningstekniken har förbättrats avsevärt under de senaste 40 åren, men på de senaste åren har de bulktillverkade transistorerna nått gränserna för Moores lag, när storleken krymper till några tiotal nanometer. De största svårigheterna är att minska energiförbrukningen, förbättra hastigheten samt bevara den låga tillverkningskostnaden. Detta har gett möjlighet för att utvecklar ny halvledarteknik. En av de mest lovande metoderna är implementering av nya transitor arkitekturer, till exempel FinFET och UTBSOI. Detta examensarbete omfattar grunderna i modellering av SOIMOSFET, med hjälp av BSIMSOI och SPICE programvara Cadence kan man modellera KTH transistor. Resultatet av denna studie visar noggrannheten hos BSIMSOI och kan användas för framtida arbete inom ämnet.
李華剛 y Eddie Herbert Li. "Narrow-channel effect in MOSFET". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.
Texto completoWang, Yao. "MOSFET strain sensor for microcantilevers". Thesis, Queen's University Belfast, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.675436.
Texto completoAraújo, Guido Costa Souza de 1962. "Simulação bidimensional de dispositivos MOSFET". [s.n.], 1990. http://repositorio.unicamp.br/jspui/handle/REPOSIP/261310.
Texto completoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica
Made available in DSpace on 2018-07-13T21:47:06Z (GMT). No. of bitstreams: 1 Araujo_GuidoCostaSouzade_M.pdf: 7097802 bytes, checksum: 3989d5131b3e9436f6f55fc6d620a10e (MD5) Previous issue date: 1990
Resumo: Com a drástica diminuição das dimensões nas novas gerações de transistores MOS VLSI, um aumento considerável de efeitos dimensionais no comportamento destes dispositivos tem surgido. Isto traz como conseqüência imediata, a impossibilidade de utilização dos modelos clássicos analíticos no projeto e no estudo destes transistores. A proposta deste trabalho é a de desenvolver um simulador bidimensional para transistores MOSFET de canal curto, que permita uma caracterização precisa destes dispositivos em equilíbrio termodinâmico. Nesta situação, a influência de efeitos dimensionais sobre VT pode ser melhor estudada, possibilitando assim a obtenção de uma primeira aproximação para o projeto destes dispositivos
Mestrado
Mestre em Engenharia Elétrica
Peters, Chris (Christopher Joseph) Carleton University Dissertation Engineering Electrical. "MOSFET based gamma radiation detector". Ottawa, 1992.
Buscar texto completoMaréchal, Aurélien. "Metal-oxide-semiconductor capacitor for diamond transistor : simulation, fabrication and electrical analysis". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT094/document.
Texto completoOver two decades of technological progresses in growth quality, doping control and device processing have led to the emergence of new potentialities for power electronic applications. As diamond represents the ultimate semiconductor owing to its superior physical properties, efforts have been conducted to develop various electronic devices, such as Schottky diodes, field effect transistors, bipolar transistor, p-i-n junctions...As a prerequisite to the development of new generation diamond power devices, on one side, is the development of simulation tools able to anticipate the device electrical properties as well as its architecture in order to take full advantage of the material physical properties. On the other hand, experimental study of the gate contact, the second building block of the transistor, is fundamental in order to develop high performance devices. In this regard, one can consider several open questions: (i) Are the simulation tools able to take into account the specificities of diamond to model electrical devices? (ii) Is the aluminum oxide suitable to develop a MOSFET gate contact? (iii) If so, is the oxide/diamond interface of good enough quality? (iv) Is the fabrication of a diamond MOSFET a technological issue?This PhD project, attend to answer these questions and pave the way towards the inversion mode MOSFET.Emphasize on the diamond physical properties will help to understand why this material is the ultimate WBG semiconductor. State of the art diamond devices will be presented focusing on field effect transistors. A complementary topic for the development of new generation diamond power device is the anticipation of device electrical properties and architecture through finite element base simulation software. Thus the need for reliable simulation tools will be presented.On one hand, the main models implemented in the simulation tools will be presented and emphasize on the diamond electrical properties will be given. For the simulation of diamond metal-oxide-semiconductor field effect transistor (MOSFET), the study of two building blocks is required: the p-n junction and the gate contact. The later ideal properties will be presented while the former will serve as a basis for the calibration of the physical parameters implemented in the finite element based software. Generation-recombination models influence on the simulated p-n junction electrical properties will be discussed. Finally, the simulation of the electrical properties of a diamond metal-oxide-semiconductor field effect transistor (MOSFET) will be shown.On the other hand, focus will be made on diamond metal-oxide-semiconductor capacitor (MOSCAP) fabrication and electrical characterization. Specifically, the interfacial band configuration of the Al2O3/oxygen-terminated diamond (O-diamond) has been investigated using X-ray photoelectron spectroscopy. The results allowed establishing the band diagram of the Al2O3/O-diamond heterostructure. Then, the electrical properties of the diamond MOSCAP will be shown. Specifically, investigation of the interface states density revealed the pinning of the Fermi level at the interface between the Al2O3 and the O-diamond. Moreover, the leakage currents through the Al2O3 layer will be discussed in terms of temperature dependent trap assisted tunneling of holes from the diamond layer to the top gate contact. Finally, the electrical characterization of the first diamond MOSFET, performed at the National Institute for Advanced Industrial Science and Technology (AIST) in Japan, will be presented. Even if this first attempt was unsuccessful, it is promising for the development of diamond MOSFET since the demonstration of the actual realization of the device is clearly established
NEDELJKOVIC, SONJA R. "PARAMETER EXTRACTION AND DEVICE PHYSICS PROJECTIONS ON LATERAL LOW VOLTAGE POWER MOSFET CONFIGURATIONS". University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1005163403.
Texto completoMohta, Nidhi. "MOSFET piezoresistance coefficients on (100) silicon". [Gainesville, Fla.] : University of Florida, 2006. http://purl.fcla.edu/fcla/etd/UFE0017761.
Texto completoWang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling". Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.
Texto completoPhilip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.
Lin, Xinnan. "Double gate MOSFET technology and applications /". View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.
Texto completoGajula, Durga Rao. "Optimization of germanium MOSFET fabrication processes". Thesis, Queen's University Belfast, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.602509.
Texto completoRudnicki, Kamil. "MOSFET transistor fabrication on AFM tip". Thesis, University of Glasgow, 2014. http://theses.gla.ac.uk/5398/.
Texto completoIyengar, Pravin. "Pulsed MOSFET based linear transformer driver". Thesis, University of Strathclyde, 2014. http://oleg.lib.strath.ac.uk:80/R/?func=dbin-jump-full&object_id=24217.
Texto completoDybek, Marcin. "Ocena przydatności detektorów MOSFET w radioterapii". Doctoral thesis, Katowice : Uniwersytet Śląski, 2012. http://hdl.handle.net/20.500.12128/5372.
Texto completoChvátal, Miloš. "Transportní a šumové charakteristiky tranzistorů MOSFET". Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-233635.
Texto completoClavijo, William. "Nanowire Zinc Oxide MOSFET Pressure Sensor". VCU Scholars Compass, 2014. http://scholarscompass.vcu.edu/etd/625.
Texto completoBudihardjo, Irwan Kukuh. "A charge based power MOSFET model /". Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/5975.
Texto completoFiala, Zbyněk. "Budiče spínacích výkonových tranzistorů GaN MOSFET". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242073.
Texto completoConstant, Aurore. "SiC oxidation processing technology for MOSFETs fabrication". Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20061.
Texto completoPower electronic devices are mainly based on the mature and very well established silicon technology. However, silicon exhibits some important limitations regarding power losses, operation temperature and speed of switching. Furthermore, unfortunately the successful silicon technology has almost reached its physical limits. Hence, a new generation of power devices based on new materials must be developed to face the future global energetic challenges. Nowadays, the most promising semiconductor material is silicon carbide (SiC). SiC is increasingly considered as the best candidate to overcome the intrinsic limitations of silicon in developing high-power and high-temperature electronic devices. It shows the best trade-off between theoretical characteristics and real commercial availability of the starting material and maturity of its technological processes.This thesis is focused on SiC-based power devices, particularly, on one of the major issues in SiC technology: the gate oxidation process. Indeed, SiC can be easily oxidized to form a thin silicon dioxide (SiO2) layer. This provides a unique opportunity to develop power Metal Oxide Semiconductor (MOS) devices, as in the Si-based technology. SiC-based power MOSFETs are expected to have great potential for high-speed and low-loss switching devices. Unfortunately, the oxide/SiC interface quality and oxide reliability are major barriers to the fabrication of advanced SiC power MOSFET devices. Alternative solutions have been developed to overcome these problems. However, SiC MOSFETs have only been recently commercially available, mainly due to reliability concerns. The MOSFET process suitable for mass production is still a challenge. The main efforts carried out in the framework of this thesis are addressed towards the development of SiC MOSFETs by improving the current gate oxide process state-of-the-art. A newly gate oxidation process based on rapid thermal processing is demonstrated, and the physical mechanisms associated with oxide formation and the SiO2/SiC interface properties are proposed. This oxidation process has been tested on hexagonal SiC (4H-SiC) and cubic SiC (3C-SiC). Furthermore, the investigated oxidation processing technology is integrated into the fabrication of reliable 4H-SiC MOSFETs, and the bias-stress instability has been evaluated up to operating temperatures of 300 ºC
Guérin, Chloé. "Etude de la dégradation par porteurs chauds des technologies CMOS avancées en fonctionnement statique et dynamique". Aix-Marseille 1, 2008. http://www.theses.fr/2008AIX11041.
Texto completoIn the last technologies, dimension reduction is performed at constant bias which means an increase of the MOSFET lateral electrical field. Reliability risks in term of hot carriers are coming back. It is very important to understand the hot carrier degradation physical root causes to insure the best compromise between performance and reliability. After studying numerous stress biases, temperatures, oxide thicknesses and lengths, we established a new physical formalism based on both carrier energy and number. This double effect translates in a three degradation mode competition dominated by each of the modes depending on the energy range. At high energy, the degradation is due to a single carrier interaction with Si-H bonds (mode 1). But when the energy decreases, carrier number begins to dominate first trough Electron-Electron interactions (mode 2) and particularly at very low energy where we put forward that degradation increases due to bond multiple vibrational excitation with cold carriers (mode 3). This new modelling allows a better lifetime extrapolation at nominal biases. Applied to degradation under digital signals, it also enables a rigorous estimation of the degradation ratio between alternative and continuous current (AC-DC). Then new design guidelines concerning frequency, fanOut and rise time have been evidenced. Finally, this new modelling is now included in Design-in Reliability simulators to know precisely circuit bloc hot carrier degradation
Bouguet, Christophe. "Développement d’un Driver Communicant pour MOSFET SiC". Thesis, Nantes, 2017. http://www.theses.fr/2017NANT4034/document.
Texto completoThe semiconductors used in power converters such as IGBT and MOSFET transistors are driven by an electronic circuit called “gate driver”. This circuit is an interface between the control command circuit and the power semiconductors. In the work done during this PhD, a driver dedicated to SiC MOSFET transistors has been developed. It is designed for components with a continuous drain current value of 300A and working under a drain- source voltage of 1200V. Beyond the development of a driver dedicated to SiC M OSFET transistors technology, a second aspect of the work presented in this PhD is about the implementation of communication functions within the power converters. Drivers are then essential elements of the communication network then constituted. A communi cation channel that suits the standards requirements relating to drivers and suits the requirements concerning the power electronics working environment has been designed. It is located between the primary side of the driver and each of its channels. Thus, the communication network in the power converter reaches the area where the DC bus voltage of 1200V is situated. The galvanic isolation necessary to the user’s safety is kept and the parasitic capacitance induced by the addition of this communication func tion remains lower than 2pF. The possible uses offered by this communication channel are discussed. Some trials done under high electric constraints (2kV / 125kV/μs) validate the functioning of the prototype of the communication channel that has been devel oped. Data transmissions reaching a speed of 500kbits/s and based on CAN protocol have been carried out
Linewih, Handoko y h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET". Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.
Texto completoJackson, Keith M. (Keith Matthew). "Optimal MOSFET design for low temperature operation". Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8565.
Texto completoIncludes bibliographical references.
The phenomenal scaling of MOSFET feature size, two orders of magnitude in the past 30 years, has provided the gains in performance and packing density that underlie the GHz microprocessors and 256 MB DRAMs that exist today. Looking forward, the connection between increased performance and smaller devices faces significant challenges. Lowering the operating temperature can help achieve the desired increases in performance as device size scales. Lowering the temperature reduces the off-state leakage of a MOSFET removing constraints on reducing the threshold voltage. In addition, lower temperatures increase the current drive via increased carrier mobility and saturation velocity. Equally as important, the parasitic resistances of the device and of the interconnect decrease as temperature decreases. The approach of this thesis is to use comparisons of optimal designs across channel lengths and across temperatures to accurately assess the performance increases and increased design flexibility that come with lowering the device operating temperature. Using analytical equations, the tradeoff between fully scaled performance and maintaining reasonable off-current levels is clearly shown. As an alternative to allowing off-currents to rise, two possible temperature scaling scenarios, that either meet or exceed fully scaled performance, are explored. Focusing on a nominal channel length of 90 nm (worst-case of 75 nm) operating at 200 K, a detailed analysis of channel doping profile design to achieve the highest on current at the nominal channel length, while meeting the off-current limit for the worst case channel length is performed. Using an inverse modeling approach, a 2-D numerical simulator is first calibrated at various temperatures to measured device data down to 80 nm channel lengths. Coupling the simulator with an optimizer, a range of different halo, retrograde, and uniform doping profiles are examined. Halo doping is found to give the best device performance due to its lower threshold voltage, lower threshold voltage decrease with channel length, and lower body effect. The halo profiles become more abrupt for lower temperature designs. Comparing optimal designs for a 90 nm nominal device across temperature, on-current gains, and thus switching speed gains, of 3.5% for every 10 °C decrease in temperature can be achieved.
by Keith M. Jackson.
Ph.D.
Al, Kzair Christian. "SiC MOSFET function in DC-DC converter". Thesis, Uppsala universitet, Elektricitetslära, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-415147.
Texto completoSUNDARAM, KARTHIK. "A DYNAMIC MOSFET MODEL IN VHDL-AMS". University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1154637877.
Texto completoTuladhar, Looja R. "Resonant Power MOSFET Driver for LED Lighting". Youngstown State University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1264709029.
Texto completoTuladhar, Looja R. "Resonant power MOSFET drivers for LED lighting /". Connect to resource online, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1264709029.
Texto completoLinewih, Handoko. "Design and Application of SiC Power MOSFET". Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.
Texto completoThesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Full Text
Matiaško, Maroš. "Experimentální spínaný zdroj s tranzistory GaN MOSFET". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242061.
Texto completoGuerfi, Youssouf. "Réalisation et caractérisation de transistors MOS à base de nanofils verticaux en silicium". Thesis, Toulouse 3, 2015. http://www.theses.fr/2015TOU30253/document.
Texto completoIn order to further downscaling of the MOS transistors, the semiconductor industry has anticipated the limitations of miniaturization by the introduction of new materials and new architectures. The advent of triple gate structures (FinFET) allowed mastering the short channel effects and further miniaturization efforts (14 nm technology node in 2014). The ultimate case to the electrostatic control of the gate on the channel is given by a gate completely surrounding the device channel. For this purpose, Gate All Around (GAA) nanowire transistor is considered as the most suitable structure for technology nodes below 7 nm. In this thesis, a large scale process for the realization of miniaturized MOSFETs based on vertical silicon nanowires has been developed. Firstly, the vertical nanowires were made by a top down approach by the transfer by etching of hard mask made of Hydrogen silsesquioxane (HSQ) resist created at low voltage electron beam lithography. An original design strategy called "star" was developed to define perfectly circular nanowires. Si nanowires are obtained by plasma etching then thinned by sacrificial wet oxidation. This method allows obtaining vertical Si nanowires with perfectly anisotropic walls, a perfect reproducibility and a maximum yield. The implementation of the MOSFETs on the nanowire network was done by successive engineering of nanoscale thin films (conductive and dielectric). In this context, an innovative process for producing insulation layers in HSQ by controlled chemical etching showed excellent flatness associated with surface roughness of less than 2 nm. Finally, a method using conventional UV photolithography has been developed to achieve the nanometer gate length transistor. These devices have demonstrated excellent electrical performances with conduction currents superior than 600 µA/µm and excellent control of short channel effects (subthreshold slope of 95 mV/dec and DIBL of 25 mV/V) despite extreme miniaturization of the gate length (15 nm). Finally, we present a first proof of concept of a CMOS inverter based on vertical nanowires technology
Ljunggren, Tobias. "Investigation of PWM-controlled MOSFET with inductive load". Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1271.
Texto completoThis report is the basis for a Bachelor of Science thesis in engineering done at Volvo Powertrain in Gothenburg. The problem consisted of investigating a circuit with a PWM-controlled MOSFET driving a DC-motor.
The problem was to investigate what caused the circuit to break the transistor. Finally an improvement of the circuit is designed making the MOSFET withstand the stressful conditions exposed to.
An overall description of the problems with switching an inductive load using a MOSFET as switch is done. Some methods to protect the MOSFET from failure are also discussed. Finally a discussion is held to suggest what broke the MOSFET, and an improved design is proposed.
Escobedo-Cousin, Enrique. "Material characterisation of strained Si/SiGe MOSFET devices". Thesis, University of Newcastle upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.485864.
Texto completoZhang, Yucai. "Multiharmonic tuning behavior of MOSFET RF power amplifiers". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63040.pdf.
Texto completoMurray, D. C. "MOSFET flicker noise : its characterisation and its origins". Thesis, University of Southampton, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315505.
Texto completoHuang, Yan-Hua y 黃彥皓. "Radio frequency MOSFET". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/47630350584396371167.
Texto completo國立交通大學
電子工程系
87
Small signal S parameters of a quarter micron Si MOSFET in common source configuration are measured from 100MHz to 18 GHz in different biasing conditions. From the S parameters we found the evidence of the non-quasi-static (NQS) effects, namely the low-pass nature of the transconductance, and the nonzero real part of the impedance looking into the gate. Also the output impedance is lowered by the finite conductance of the substrate. In order to fit the S parameters, we chose BSIM3v3, which is successful in describing the small geometry effects, as the basic model. DC characteristics of Si MOSFET of various channel lengths and widths were measured, and BSIM3v3 model parameters were carefully extracted. A gate resistor originating from the NQS effect showing up at the frequency range of interest, and a network accounting for the substrate resistance are added. The measured S parameters are used as the guideline in determining the added components. Good fitting was obtained. The variation of the gate resistance with bias was investigated, and was in agreement with the theory.
Lo, Hung-Ming y 駱宏明. "n-MOSFET Performance Evaluation". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/96059871089398717314.
Texto completo國立高雄應用科技大學
電子與資訊工程研究所碩士班
92
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been widely used in ULSI semiconductor technology. The major advantages of MOSFET are high yield, low cost, dense packing, and low power consumption. The carrier mobility in the inversion charge layer of MOSFET has become increasingly important as device scale down to deep submicron due to its deterministic property in drain current. Therefore, the inversion-layer mobility is a vital important parameter to understand the mechanisms of charge transport in the surface inversion layer. In this thesis, we measure the current-voltage (I-V) characteristics of n-MOSFET with the gate lengths of 10μm and 4μm. A simple model is used to extract the effective carrier mobility (μeff) with respect to the gate voltage (VG). Our results show that the change of the mobility is strongly dependent on the gate bias, and its trend agrees well in comparison to other theoretical and experimental works. In the region of small VG, the mobility is mainly determined by impurity scattering, but the increase of surface roughness scattering in high field region instead of the role of impurity becomes a deterministic factor in mobility degradation. The fitting model proposed in the thesis enables reliable values in the changes of mobility, effective oxide capacitance, doping concentration, and threshold voltage with respect to the gate bias.
Lin, Sheng-Zhi y 林聖智. "p-MOSFET Performance Evaluation". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/00293290458545871034.
Texto completo國立高雄應用科技大學
電子與資訊工程研究所碩士班
92
In this paper , we measure the I-V characteristics of the p-MOSFETs with the gate lengths of 4μm and 10μm, and apply a simple model to extract the change of mobility with respect to the gate voltage. Our results show that the changes of the mobility for both p-MOSFETs are strongly dependent on the gate bias due to the interplay of interface roughness scattering, ionized impurity scattering, and the change of density-of-state. The strength of the impurity scattering is reduced by increasing VG due to the decrease of density of state, and the screening effect in increasing the carrier density, which results to the increase of mobility. However, the increasing VG enhances the interface roughness scattering, and results to the mobility degradation. Moreover, an anomaly around VG ~ 1.1V is observed in the plot of the mobility with respect to the gate bias. It is mainly attributed to the change of the oxide charge as the gate bias crossover 1.1V.
Yeh, Ting-Hsien y 葉婷銜. "Double-gate MOSFET Simulator". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23537537074173278742.
Texto completo國立交通大學
電子研究所
101
It is well known that the scaling of the traditional bulk MOSFETs would encounter several issues like the short channel effects (SCE). To deal with this problem, many of methods have been proposed, one of which is new device architectures, such as multi-gate structures. The aim of this work is to develop a double-gate n-MOSFET simulator by using self-consistent solving of Schrödinger and Poisson equations with some physical models taken into account. Besides, for many simulators in the literature, the boundary conditions of Schrödinger’s equation are often making an infinite potential barrier height at the silicon/gate-oxide interface. Nevertheless, we know that the actual barrier height is finite and is equal to a few electron-volts. Therefore, wave-function actually can penetrate into the gate-oxide dielectric. Hence, we also add wave-function penetration effect to our simulator, and discuss the influences of penetration effect and electron tunneling effective mass on the double-gate structure performance. Finally, we also build mobility and stress related model, and compare those with literature values. From the comparison results, our simulations are consistent with Schred as well as with some articles with and without wave-function penetration included, except for the mobility of thinner substrate thickness which should consider more scattering mechanisms. That is to say, our simulator comes to be reasonable for calculating fundamental properties in DG n-MOSFETs.
Tsai, Ming-Tsang y 蔡明蒼. "High Voltage Contact Gate MOSFET (CG-MOSFET) with Fully CMOS Logic Compatible Process". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/62642110513392707942.
Texto completo國立清華大學
電子工程研究所
99
In recent years, the improvement of power electronics and power devices is one of keys when the energy issues become more important. The cost down and the tradeoff between breakdown voltage and on-resistance have always been major concerns in designing power devices. Many studies have proposed their structure only needs few masks. However, it is still special process which needs wire bonding to connect the power device and main circuit. It is a limit for cost down. In this thesis, a novel 20V-class device with CMOS logic compatible process is proposed which called Contact Gate MOSFET (CGMOS). Since the device does not need the mask of drift region and wire bonding, it could be cost down substantially. By T-CAD simulation and measurement, the newly designed device has breakdown voltage up to 18 volt and 8.8mΩ∙mm2 specific on-resistance. From statistical distribution, the stability of device is up to 87%. And no characteristic variation can be observed after long term temperature stress at 125˚C for 1000 hours.
Yen, Wei-Ting y 顏瑋廷. "A Self-Aligned Nanowire MOSFET". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/h7jr5d.
Texto completo國立中央大學
電機工程研究所
94
In this thesis, the formation of NiSi silicide using rapid thermal annealing is investigated. The NiSi salicidation process is, then, incorporated into the fabrication of novel self-aligned nanowire MOSFET devices structure. A self-aligned nanowire MOSFET fabricated on a 70-nm-thick SOI wafer, features advanced process modules including recessed nitride spacer, fully silicided (NiSi) source/drain, and self-aligned poly silicon gate. In the pursuit of low series resistance in a thin SOI, it is critical to optimize spacer width and utilize fully-silicide S/D. Since LOCOS process is integrated in a nanowire MOSFET process flow, one doesn’t require e-beam lithography to do precise alignment for ultra narrow gate stacked structure. A self-aligned poly gate technology is utilized to improve manufacturing yield efficiently. A recessed spacer structure is carried out using hot phosphoric acid etching, which is highly selective between Si3N4 and Si. Edge effects of Ni polycide formation are enhanced by such recessed spacer and result in Rs reduction further. Finally, the device performance is evaluated.
"Simulação bidimensional de dispositivos MOSFET". Tese, Biblioteca Digital da Unicamp, 1990. http://libdigi.unicamp.br/document/?code=vtls000026459.
Texto completoChen, Hsun-Hsiang y 陳勛祥. "MOSFET characteristics at low temperature". Thesis, 1998. http://ndltd.ncl.edu.tw/handle/21445052136293516335.
Texto completoSung, Tung-Hao y 宋東壕. "Backscattering-Oriented MOSFET Mismatch Experiment". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/12720514739231663603.
Texto completo國立交通大學
電子工程系所
96
In this thesis, we have derived several mathematical models to express the mismatch properties of MOS transistors based on the backscattering theory. We have extracted the KBT layer’s width from the experimental analysis and we have found a simple model to express its mismatch properties based on the parabolic potential barrier. The mean-free-path and the backscattering coefficient have also been discussed in this thesis. For the purpose of the accuracy, the source/drain series resistance has been incorporated in to our parameters extraction. Straightforwardly, we have developed a drain current mismatch model based on backscattering theory in the saturation region.
"The extraction of MOSFET parameters". Chinese University of Hong Kong, 1988. http://library.cuhk.edu.hk/record=b5886228.
Texto completo