Artículos de revistas: "Modeling of processor design"

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Li, Lei, Hai-bin Shen, Kai Huang, Xiao-lang Yan, Han Sangil y Ahmed A Jerraya. "Distributed Memory Service Modeling in Multi-Processor Design". Journal of Electronics & Information Technology 30, n.º 11 (14 de abril de 2011): 2750–54. http://dx.doi.org/10.3724/sp.j.1146.2007.00596.

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Eyerman, Stijn y Lieven Eeckhout. "Probabilistic job symbiosis modeling for SMT processor scheduling". ACM SIGPLAN Notices 45, n.º 3 (5 de marzo de 2010): 91–102. http://dx.doi.org/10.1145/1735971.1736033.

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3

Lee, Je-Hoon. "Power Modeling Framework for an Asynchronous Processor". Journal of Circuits, Systems and Computers 25, n.º 06 (31 de marzo de 2016): 1650057. http://dx.doi.org/10.1142/s0218126616500572.

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This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster than the conventional low-level power simulator. It also shows similar results compared to the conventional power model for a synchronous processor. Even though the simulation speeds for the proposed power models are approximately 100–900 times faster than the low-level power simulator, the differences are less than 18% and 15%, respectively. Thus, the proposed power models can give a guide for SoC designers who want to integrate the asynchronous processor for low-power SoC design.

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LIN, S., Y. CHEN, C. YU, Y. LIU y C. LEE. "Dynamic modeling and control structure design of an experimental fuel processor". International Journal of Hydrogen Energy 31, n.º 3 (marzo de 2006): 413–26. http://dx.doi.org/10.1016/j.ijhydene.2005.06.027.

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5

Wu, Wei, Shu-Bo Yang, Jenn-Jiang Hwang y Xinggui Zhou. "Design, modeling, and optimization of a lightweight MeOH-to-H2 processor". International Journal of Hydrogen Energy 43, n.º 31 (agosto de 2018): 14451–65. http://dx.doi.org/10.1016/j.ijhydene.2018.05.135.

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So, Hwisoo, Yohan Ko, Jinhyo Jung, Kyoungwoo Lee y Aviral Shrivastava. "gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration". Electronics 12, n.º 22 (8 de noviembre de 2023): 4573. http://dx.doi.org/10.3390/electronics12224573.

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With aggressive technology scaling, soft errors have become a major threat in modern computing systems. Several techniques have been proposed in the literature and implemented in actual devices as countermeasures to this problem. However, their effectiveness in ensuring error-free computing cannot be ascertained without an accurate reliability estimation methodology. This can be achieved by using the vulnerability metric: the probability of system failure as a function of the time the program data are exposed to transient faults. In this work, we present a gemV-tool, a comprehensive toolset for estimating system vulnerability, based on the cycle-accurate gem5 simulator. The three main characteristics of the gemV-tool are: (i) fine-grained modeling: vulnerability modeling at a fine-grained granularity through the use of RTL abstraction; (ii) accurate modeling: accurate vulnerability calculation of speculatively executed instructions; and (iii) comprehensive modeling: vulnerability estimation of all the sequential elements in the out-of-order processor core. We validated our vulnerability models through extensive fault injection campaigns with <3% correlation error and 90% statistical confidence. Using the gemV-tool, we made the following observations: (i) the vulnerability of two microarchitectural configurations with similar performance can differ by 82%; (ii) the vulnerability of a processor can vary by more than 10×, depending on the implemented algorithm; and (iii) the vulnerability of each component in the processor varies significantly, depending on the ISA of the processor.

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Kumar, K. S. y J. H. Tracey. "Modeling and Description of Processor-Based Systems with DTMSII". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 1 (enero de 1987): 116–27. http://dx.doi.org/10.1109/tcad.1987.1270254.

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8

Martin, Grant. "Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors". Journal of Signal Processing Systems 53, n.º 1-2 (29 de noviembre de 2007): 113–27. http://dx.doi.org/10.1007/s11265-007-0153-7.

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Martono y Zulfi. "Perancangan Aplikasi Point of Sale (POS) pada Karya Maju Jaya". Jurnal PROCESSOR 17, n.º 2 (28 de octubre de 2022): 114–24. http://dx.doi.org/10.33998/processor.2022.17.2.1266.

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Karya maju jaya is one of the shops that engaged in the provision of services and goods in the form of workshops. Currently at karya maju Jaya, the process of managing transactions and financial reports still uses paper media as a means of storing data, causing many weaknesses in terms of security, effectiveness from the aspect of time, higher costs to the high possibility of errors in processing and processing information. Therefore, the author decided to conduct a research that the author gave the title point of sale (POS) application design on the work of karya maju jaya with the aim of answering all the problems above. The point of sale (POS) application in this study will be described using use case diagrams and class diagrams modeling. The final product of the research that the author did in this research is a point of sale (POS) application that allows application users to process product data, manage transaction data, manage reports, manage invoices, manage profiles, change passwords, login and logout.

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Oliveira, Marcio F. da S., Eduardo W. Brião, Francisco A. Nascimento y Flávio R. Wagner. "Model Driven Engineering for MPSoC Design Space Exploration". Journal of Integrated Circuits and Systems 3, n.º 1 (18 de noviembre de 2008): 13–22. http://dx.doi.org/10.29292/jics.v3i1.277.

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This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the ever-growing challenge of designing complex embedded systems. This approach allows the designer to automatically select the most adequate modeling solution for application, platform, and mapping between application and platform, in an integrated and simultaneous way and at a very early design stage, before system synthesis and code generation have been performed. The exploration is based on high-level estimates of physical characteristics of each candidate solution. In an experimental setting, the DSE tool automatically performs four design activities: it selects the number of processors, maps tasks to processors, allocates processors to bus segments, and sets the voltage of each processor. Experimental results, extracted from a DSE scenario for a real application, show that the proposed estimation and exploration approach may find a suitable solution regarding the design requirements and constraints in a very short time, with an acceptable accuracy, without relying on costly synthesis-and-simulation cycles.

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Fleury, M., A. C. Downton y A. F. Clark. "Modelling pipelines for embedded parallel processor system design". Electronics Letters 33, n.º 22 (1997): 1852. http://dx.doi.org/10.1049/el:19971249.

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Lakhdara, Zakaria y Salah Merniz. "A SysML and CLEAN Based Methodology for RISC Processor Micro-Architecture Design". International Journal of Embedded and Real-Time Communication Systems 6, n.º 1 (enero de 2015): 101–31. http://dx.doi.org/10.4018/ijertcs.2015010105.

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Nowadays, processor micro-architectures are becoming more and more complex. Consequently, designers increasingly need powerful abstraction and structuration mechanisms, as well as design methodologies that automatically and formally derive low-level concrete designs from high-level abstract ones. In this context, this paper proposes a methodology for RISC processor micro-architecture design. The proposed methodology uses mainly SysML to model both ISA and MA levels and the functional language CLEAN to describe them. Functional specifications in CLEAN are automatically generated from the ISA and MA models. These specifications, which are executable and formally verifiable, are used for simulation and verification. The proposed approach is validated by a case study that consists of designing the micro-architecture of MIPS processor. It shows how to easily model and generate CLEAN specifications describing the ISA and MA levels. It also illustrates, with multiple cases, how the generated specifications are used to simulate the MA. The results of the simulation phase prove the efficiency of the proposed modeling and code generation techniques.

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Eeckhout, Lieven, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere y Lizy K. John. "Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies". ACM SIGARCH Computer Architecture News 32, n.º 2 (2 de marzo de 2004): 350. http://dx.doi.org/10.1145/1028176.1006730.

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Conte, T. M., K. N. Menezes, S. W. Sathaye y M. C. Toburen. "System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, n.º 2 (abril de 2000): 129–37. http://dx.doi.org/10.1109/92.831433.

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Prado, Bruno, Edna Barros, Thiago Figueredo y André Aziz. "HdSC: A Fast and Preemptive Modeling for on Host HdS Development". Journal of Integrated Circuits and Systems 7, n.º 1 (27 de diciembre de 2012): 61–71. http://dx.doi.org/10.29292/jics.v7i1.356.

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In modern embedded systems, the Hardware-dependent Software (HdS) plays a critical role due to its processor and platform dependency, such as device drivers and boot initialization. To support HdS development starting in an initial system design phase, fast and accurate preemptive processor models should be provided for simulating the software. These models should provide a register level interface to enable a compatible programming view on the host machine environment. This paper presents a strategy for processor modeling that enables HdS development, using the host machine tool chain. The proposed approach supports the specification of platform components, such as processor, software and devices accessed through the data bus and interruption interfaces. An adaptive technique for timing estimation is being proposed, which is very accurate and show a high simulation performance. Supporting the device driver development and interruption service routines, these two features can be implemented and simulated at an early system design phase and requiring no Instruction Set Simulator (ISS). This ISS model would be required only for performance and accuracy comparison purposes. Experimental results show that the virtual platform specified using this proposed approach can perform faster (up to 760x speed up) and high accurate (up to 12%) software simulation on native host environment.

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Chakraborty, Bidesh, Mamata Dalui y Biplab K. Sikdar. "Design of a Reliable Cache System for Heterogeneous CMPs". Journal of Circuits, Systems and Computers 27, n.º 14 (23 de agosto de 2018): 1850219. http://dx.doi.org/10.1142/s0218126618502195.

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The embedded system-on-a-chip (SoC), that integrates heterogeneous processors with variation in coherence protocol, adds complexity in maintaining coherency in the data caches. It further complicates the task of coherence verification in such systems. This work targets effective solution for coherence verification in heterogeneous chip multiprocessors (CMPs) through introduction of highly efficient verification unit. It is developed around the modeling tool of cellular automaton (CA) invented by von Neumann in 1950s. The modular and cascadable structure of CA ensures high scalability and robustness in the proposed design. A CA segment is employed to analyze the states of a data block in different private caches of a heterogeneous processor cluster and to verify inconsistencies, if any, within the cluster. The outcomes of coherence verification for clusters are analyzed by the CA resulted out of augmentation of the CA segments. On the other hand, in this work, we further propose a CA-based coherence protocol processor (PP), which caters the need for determining the state of a data block with high accuracy. The PP designed for the heterogeneous CMPs, while computing the states of za block on every transaction (read/write), can capture defects, if any, and thereby realizes a fault-tolerant PP without introduction of additional hardware logic.

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17

Knopf, George K. y Madan M. Gupta. "Design of a multitask neurovision processor". Journal of Mathematical Imaging and Vision 2, n.º 2-3 (noviembre de 1992): 233–50. http://dx.doi.org/10.1007/bf00118592.

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Gadag, Shiva P., Susan K. Patra, Volkan Ozguz, Phillipe Marchand y Sadik Esener. "Design and Analysis: Thermal Emulator Cubes for Opto-Electronic Stacked Processor". Journal of Electronic Packaging 124, n.º 3 (26 de julio de 2002): 198–204. http://dx.doi.org/10.1115/1.1481894.

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3D finite element modeling of thermal emulator cube and its composition consisting of composite stack of multi-layer chip are developed. Thermal analysis of the Multi-Chip Module consisting of 16 alternate layers Si processor and heat sink layers with Si spacers and AlN ceramic cap is undertaken. The various alternatives for design of the emulator cubes such as thermal cube floating in free-space, thermal cube-on-substrate, thermal cube-on-flex cable with a continuous joint of solder and thermal cube embedded in rectangular Si-spacer are investigated for their heat extraction capability. Thermal modeling of a composite structural unit stack of chip offers first hand information as to the operating performance of the entire thermal emulator cube to be used in the construction of buffer cube. The scientific understanding of the mode of heat transfer of the emulator cube, heat extraction of the various heat sink materials, ceramic and the metallic substrates are investigated. A thin sheet of ceramic (AlN) substrate is at least three times more effective in extraction of heat than thick block of steel under similar conditions. The homogeneous and heterogeneous nature of the composite structure of thermal emulator in heat transfer is analyzed. The primary and secondary hotspots in thermal cubes with AlN heat sink are found in thermal simulations. The mode of heat transfer advances normal to lateral and transverse directions of stacking from the central core of the cube towards the outward face. The sharp corners of the cube typically exhibit edge convection due to chilling effect. Buffer-on-flex cable is modeled with a continuous solder joint and its further improvement with alternate hinges of solder joints and micro-channels is proposed for enhanced heat transfer analysis. The embedded emulator cubes are developed for thermal analysis of the optical layers on top of buffer. The optical layers with an interconnection of solder joints on top of the embedded emulator cubes coupled with micro-channels and hinged solder joints will be used for further enhanced heat transfer and higher dissipation of heat 1∼3W/layer resulting in efficient and cost effective thermal management technique.

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Fleury, M., R. P. Self y A. C. Downton. "Large-Scale, Parallel Embedded Applications: A Hardware Design Model for Software Engineers". International Journal of Electrical Engineering & Education 38, n.º 4 (octubre de 2001): 348–67. http://dx.doi.org/10.7227/ijeee.38.4.8.

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Parallel servers are becoming an important sector in the embedded systems marketplace. If software engineers are to implement the multi-algorithm applications that these servers support, then educators should provide clear design routes which inculcate system-level thinking. Pipelined Processor Farms (PPF) is one such top-down design strategy. The contemporary hardware diversity within both processor- and instruction-level parallellism requires incorporation of a coprocessor model at the node or sub-system layer. Two suitable software-based approaches are reviewed: one which maintains the traditional aspects of hardware modeling, SystemC, and the other, Handel-C, which introduces silicon compilation to the CAD laboratory.

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Reshadi, Mehrdad, Bita Gorjiara y Nikil D. Dutt. "Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 12 (diciembre de 2006): 2904–18. http://dx.doi.org/10.1109/tcad.2006.882597.

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Kim, Sung Je y Young Man Cho. "Optimal design of a rapid thermal processor via physics-based modeling and convex optimization". Control Engineering Practice 10, n.º 11 (noviembre de 2002): 1199–210. http://dx.doi.org/10.1016/s0967-0661(02)00098-9.

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Uma, S. y P. Sakthivel. "Hardware Evaluation and Software Framework Construction for Performance Measurement of Embedded Processor". Journal of Computational and Theoretical Nanoscience 15, n.º 2 (1 de febrero de 2018): 586–94. http://dx.doi.org/10.1166/jctn.2018.7126.

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A frame work for analysing the capabilities and area of improvements for working of an embedded processor is constructed, and also a methodology for comparative study of simulation of processor on load and hardware results are explained in this paper. The processor can be modelled as a standalone processor or as a group of processors working together to take parallel program execution mode. The proposed frame work and simulation method uses the processor representation of current embedded processor model which is relevant in product design and devices modelling. This system utilizes the ARM processor model which consists of programs used for computing and standardizing the operational quality of a processor for any particular domain of applications. This paper presents steps for creating experimental framework which uses a simulation system running on a Linux based operating system along with kernel for running test applications on the target which is run in simulation mode. To evaluate the simulation with respect to the real hardware, this paper has made an observation of cache related performance of a typical embedded processor. The processor which is taken for the study is ARM926EJ-S processor. The future architectural components will be designed and simulated in the framework as continuation of this experiment. Their ARM9 technology equivalent design parameters for configurable modules of CPU in 1.8 micro-meter and experimental nano-meter level implementation would be calculated with architecture component design tools.

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Jain, Abhishek y Richa Gupta. "Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors". VLSI Design 2016 (26 de septiembre de 2016): 1–14. http://dx.doi.org/10.1155/2016/7283471.

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In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal verification methodology- (UVM-) based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.

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Pon Pushpa, S. Ewins y Manamalli Devasikamani. "Schedulability Analysis for Rate Monotonic Algorithm-Shortest Job First Using UML-RT". Modelling and Simulation in Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/206364.

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System modelling with a unified modelling language (UML) is an active research area for developing real-time system development. UML is widely used modelling language in software engineering community, to specify the requirement, and analyse the target system successfully. UML can be used to provide multiple views of the system under design with the help of a variety of structural and behavioural diagrams at an early stage. UML-RT (unified modelling language-real time) is a language used to build an unambiguous executable specification of a real-time system based on UML concepts. This paper presents a unified modeling approach for a newly proposed rate monotonic scheduling algorithm-shortest job first (RMA-SJF) for partitioned, semipartitioned and global scheduling strategies in multiprocessor architecture using UML-RT for different system loads. As a technical contribution, effective processor utilization of individual processors and success ratio are analyzed for various scheduling principles and compared with EDF and D_EDF to validate our proposal.

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Yao, Wu-Sung. "Modeling and stabilization of eccentric gravity machinery". Advances in Mechanical Engineering 10, n.º 1 (enero de 2018): 168781401775178. http://dx.doi.org/10.1177/1687814017751782.

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In general, eccentric gravity machinery is a rotation mechanism with eccentric pendulum mechanism, which can be used to convert continuously kinetic energy generated by gravity energy to electric energy. However, a stable rotated velocity of the eccentric gravity machinery is difficult to be achieved only using gravity energy. In this article, a stable velocity control system applied to eccentric gravity machinery is proposed. The dynamic characteristic of eccentric gravity machinery is analyzed and its mathematical model is established, which is used to design the controller. A stable running velocity of the eccentric gravity machinery can be operated by the controlled servomotor. Due to disturbances being periodic, repetitive controller is installed to velocity control loop. The stability performance and control performance of the repetitive control system are discussed. The iterative algorithm of the repetitive control is executed by a digital signal processor TI TMS320C32 floating-point processor. Simulated and experimental results are reported to verify the performance of the proposed eccentric gravity machinery control system.

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Zou, An, Huifeng Zhu, Jingwen Leng, Xin He, Vijay Janapa Reddi, Christopher D. Gill y Xuan Zhang. "System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System". ACM Transactions on Architecture and Code Optimization 18, n.º 4 (31 de diciembre de 2021): 1–27. http://dx.doi.org/10.1145/3468145.

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Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called Ivory for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module– (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2 μs to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.

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Chadha, Ankit, Shreyas Gaonkar y Aditi Desai. "Design, Modeling and Implementation of 8-bit Processor for Intelligent Automatic Chocolate Vending Machine (AVM)". International Journal of Computer Applications 89, n.º 17 (26 de marzo de 2014): 1–7. http://dx.doi.org/10.5120/15720-4549.

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Zhang, Qi y Wenhui Pei. "DSP Processer-in-the-Loop Tests Based on Automatic Code Generation". Inventions 7, n.º 1 (11 de enero de 2022): 12. http://dx.doi.org/10.3390/inventions7010012.

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The digital signal processing (DSP) processor-in-the-loop tests based on automatic code generation technology are studied. Firstly, the idea of model-based design is introduced, and the principle and method of embedded code automatic generation technology are analyzed by taking the automatic code generation of the DSP control algorithm for pulse width modulation (PWM) output as an example. Then, the control system model is established on MATLAB/Simulink. After verifying the model through simulation, the target board platform is established with DSP as the core processor, and the automatically generated code is tested by the processor-in-the-loop (PIL). The results show that the technology greatly shortens the development cycle of the project, improves the robustness and consistency of the control code, and can be widely used in the complex algorithm development process of the controller, from intelligent design and modeling to implementation.

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Ogbodo, Mark, Khanh Dang, Fukuchi Tomohide y Abderazek Abdallah. "Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor". SHS Web of Conferences 77 (2020): 04003. http://dx.doi.org/10.1051/shsconf/20207704003.

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Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of synapses necessitates the building of small-sized low power spiking neuron processor core with efficient neuro-coding scheme and fault tolerance. This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems. The spiking neuron Processor core houses an array of leaky integrate and fire (LIF) neurons, and utilizes a crossbar memory in modelling the synapses, all within a chip area of 0.12mm2 and was able to achieves an accuracy of 95.15% on MNIST dataset inference.

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Liu, Shaohan y Dake Liu. "Design Space Exploration of 1-D FFT Processor". Journal of Signal Processing Systems 90, n.º 11 (23 de julio de 2018): 1609–21. http://dx.doi.org/10.1007/s11265-018-1393-4.

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Garrett, James H. y Steven J. Fenves. "A knowledge-based standards processor for structural component design". Engineering with Computers 2, n.º 4 (diciembre de 1987): 219–38. http://dx.doi.org/10.1007/bf01276414.

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Ziolek, Scott A. y Pieter C. Kruithof. "Human Modeling & Simulation: A Primer for Practitioners". Proceedings of the Human Factors and Ergonomics Society Annual Meeting 44, n.º 38 (julio de 2000): 825–27. http://dx.doi.org/10.1177/154193120004403839.

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More and more, digital human modeling and simulation is being used in conjunction with CAD systems to address ergonomic issues early within the development and manufacturing process. However, purchasing a human modeling software package does not guarantee a user-centered design anymore than purchasing a word processor makes someone an author. This paper addresses some of the practical issues that confront human modeling and simulation users, including the collection of geometry, posturing the manikin, and selection of an analysis. For the purposes of discussion, human simulation will be divided into three broad areas: the environment, manikin selection, and analysis.

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Duan, Feng Yang, Li Min Chang y Ye Zhan. "Realization of the Detecting Method for Aircraft Digital Image Transmission System Based on Multi-Processor". Advanced Materials Research 490-495 (marzo de 2012): 2352–56. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2352.

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The technologies of image block, pyramid and multi-threading were used in this program to design the high-speed image generation display module and the processes of image data scheduling and mapping and solve the problems of large-capacity image data modeling and high-speed displaying. The technology of direct digital frequency synthesis (DDS) was used to design the Doppler shifting signal generation module and the multi-processor parallel system architecture, which can analog the Doppler frequency shifting of the data communication signals and solve the problem of the authenticity of communication signals during the simulated flight.

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Srinivasan, V. Prasanna y A. P. Shanthi. "A BBN-Based Framework for Design Space Pruning of Application Specific Instruction Processors". Journal of Circuits, Systems and Computers 25, n.º 04 (2 de febrero de 2016): 1650028. http://dx.doi.org/10.1142/s0218126616500286.

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During the synthesis phase of the embedded system design process, the designer has to take early decisions for selecting the optimal system components such as processors, memories, communication interfaces, etc. from the available huge design alternatives. In order to obtain the optimal design configurations from the available huge design alternatives, an efficient design space pruning technique that will ease the design space exploration (DSE) process is required. The knowledge about the target architectural parameters affecting the overall objectives of the system should be considered during the design, so that the search process for finding the optimal system configurations will be rapid and more efficient. The Bayesian belief network (BBN)-based modeling framework for design space pruning proposed in this paper attempts to resolve the existing limitation in imparting domain knowledge and provides a pioneering effort to support the designer during the process of application specific system design. The Xtensa customizable processor architecture from Tensilica and a very long instruction word (VLIW) processor architecture are considered as example target platforms to impart the domain knowledge for the proposed model. Case studies in support of the proposed model are presented in order to understand how BBN can be used for design space pruning by propagating the evidence and arriving at probabilistic inferences to ease the decision-making process. The results show that the design space reduces drastically from a few million design options available to just less than one hundred for Xtensa architecture and from a few billions of design options available to just few thousands for VLIW architecture. The work also validates the pruned design points for their optimality.

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35

Hamblen, James O. "Using Vhdl Based Modeling, Synthesis, and Simulation in an Introductory Computer Architecture Laboratory". International Journal of Electrical Engineering & Education 33, n.º 3 (julio de 1996): 251–60. http://dx.doi.org/10.1177/002072099603300306.

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Using VHDL based modelling, synthesis, and simulation in an introductory computer architecture laboratory In many existing curricula, there is a notable lack of recent research advances in CAD tools and rapid prototyping using logic synthesis. This paper describes a novel introductory computer architecture laboratory that utilizes these new developments. VHDL based logic synthesis and timing simulations are used to design a RISC processor.

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36

Sarigul, N., M. Jin, G. R. Kolar y H. A. Kamel. "Design of array processor software for nonlinear structural analysis". Computers & Structures 20, n.º 6 (1985): 963–74. http://dx.doi.org/10.1016/0045-7949(85)90016-1.

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37

Ugwueze, Ogechukwu Kingsley, Chijindu C. V., Udeze C. C., Ahaneku A. M., Eneh N. J., Obinna M. Ezeja y Edward C. Anoliefo. "Modeling cache performance for embedded systems". Bulletin of Electrical Engineering and Informatics 10, n.º 5 (1 de octubre de 2021): 2910–20. http://dx.doi.org/10.11591/eei.v10i5.2459.

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This paper presents a cache performance model for embedded systems. The need for efficient cache design in embedded systems has led to the exploration of various methods of design for optimal cache configurations for embedded processor. Better users’ experiences are realized by improving performance parameters of embedded systems. This work presents a cache hit rate estimation model for embedded systems that can be used to explore optimal cache configurations using Bourneli’s binomial cumulative probability based on application of reuse distance profiles. The model presented was evaluated using three mibench benchmarks which are bitcount, basicmath and FFT for 4kb, 8kb, 16kb, 32kb and 64kb sizes of cache under 2-way, 4-ways, 8-ways and 16-ways set associative configurations, all using least recently-used (LRU) replacement policy. The results were compared with the results obtained using sim-cheetah from simplescalar simulators suite. The mean errors for bitcount, basicmath, and FFT benchmarks are 0.0263%, 2.4476%, and 1.9000% respectively. Therefore, the mean error for the three benchmarks is equal to 1.4579%. The margin of errors in the results was below 5% and within the acceptable limits showing that the model can be used to estimate hit rates of cache and to explore cache design options.

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KIM, H. Y. "Trace-Driven Performance Simulation Modeling for Fast Evaluation of Multimedia Processor by Simulation Reuse". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, n.º 12 (1 de diciembre de 2005): 3306–14. http://dx.doi.org/10.1093/ietfec/e88-a.12.3306.

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39

BAHN, JUN HO, SEUNG EUN LEE, YOON SEOK YANG, JUNGSOOK YANG y NADER BAGHERZADEH. "ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE". Parallel Processing Letters 18, n.º 02 (junio de 2008): 239–55. http://dx.doi.org/10.1142/s0129626408003363.

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As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion of utilizing Network-on-Chip (NoC) technologies for the future generation of high performance and low power chips for myriad of applications, in particular for wireless communication and multimedia processing, has been of great importance. In order for the NoC technologies to succeed, realistic specifications such as throughput, latency, moderate design complexity, programming model, and design tools are necessary requirements. For this purpose, we have covered some of the key and challenging design issues specific to the NoC architecture such as the router design, network interface (NI) issues, and complete system-level modeling. In this paper, we propose a multi-processor system platform adopting NoC techniques, called NePA (Network-based Processor Array). As a component of system platform, the fundamental NoC techniques including the router architecture and generic NI are defined and implemented adopting low power and clock efficient techniques. Using a high-level cycle-accurate simulation, various parameters relevant to its performance and its systematic modeling are extracted and analyzed. By combining various developed systematic models, we construct the tool chain to pursue hardware/software design tradeoffs necessary for better understanding of the NoC techniques. Finally utilizing implementation of parallel FFT algorithms on the homogeneous NePA, the feasibility and advantages of using NoC techniques are shown.

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40

Bai, Mingsian R. y Kwuen-Yieng Ou. "Design and Implementation of Electromagnetic Active Control Actuators". Journal of Vibration and Control 9, n.º 8 (agosto de 2003): 997–1017. http://dx.doi.org/10.1177/10775463030098006.

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We present the modeling, parameter identification and design procedure of a linear voice-coil motor. A numerical simulation has been carried out to facilitate system integration. In particular, we use electromechanical analogy and the time-domain identification procedure with the eigensystem realization algorithm to predict the system response. In order to evaluate the performance of the voice-coil motor, we conducted an experimental investigation. Voice-coil motors mounted on a ball bearing housing are used for generating counter forces to cancel the transverse vibrations of a shaft. A controller is designed by using generalized predictive control. Multiple channel active control systems are implemented on the platform of a digital signal processor. Numerical and experimental results indicated that the designed actuators were effective in suppressing the periodic disturbances in rotors.

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41

Dzitac, Pavel y Md Mazid Abdul. "Modeling of an Object Manipulation Motion Planner and Grasping Rules". Applied Mechanics and Materials 278-280 (enero de 2013): 664–72. http://dx.doi.org/10.4028/www.scientific.net/amm.278-280.664.

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This paper presents the development of a Motion Planning Module for object manipulation, which is a part of previously developed robotic grasping and manipulation controller. The Motion Planning Module consists of a sensing processor, decision making module, instinctive controller, motion planner and a planned motion controller. Details related to the design and modelling of the motion planning module have been offered. Results of experiments on human grasping rule, suitable for the grasping and manipulation controller, have been discussed. The output of this research may be useful to those developing motion planning strategies for their grasping and manipulation controllers.

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42

Haj Ahmad, Hanan, Ehab M. Almetwally y Dina A. Ramadan. "Investigating the Relationship between Processor and Memory Reliability in Data Science: A Bivariate Model Approach". Mathematics 11, n.º 9 (3 de mayo de 2023): 2142. http://dx.doi.org/10.3390/math11092142.

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Modeling the failure times of processors and memories in computers is crucial for ensuring the reliability and robustness of data science workflows. By understanding the failure characteristics of the hardware components, data scientists can develop strategies to mitigate the impact of failures on their computations, and design systems that are more fault-tolerant and resilient. In particular, failure time modeling allows data scientists to predict the likelihood and frequency of hardware failures, which can help inform decisions about system design and resource allocation. In this paper, we aimed to model the failure times of processors and memories of computers; this was performed by formulating a new type of bivariate model using the copula function. The modified extended exponential distribution is the suggested lifetime of the experimental units. It was shown that the new bivariate model has many important properties, which are presented in this work. The inferential statistics for the distribution parameters were obtained under the assumption of a Type-II censored sampling scheme. Therefore, point and interval estimation were observed using the maximum likelihood and the Bayesian estimation methods. Additionally, bootstrap confidence intervals were calculated. Numerical analysis via the Markov Chain Monte Carlo method was performed. Finally, a real data example of processors and memories failure time was examined and the efficiency of the new bivariate distribution of fitting the data sample was observed by comparing it with other bivariate models.

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43

Zhang, Zeng Nian, Zun Yi Wang, Mian Mian Chen y Jiong Shi. "Intelligent Transportation Video Detecting System Based on DSP". Applied Mechanics and Materials 701-702 (diciembre de 2014): 498–504. http://dx.doi.org/10.4028/www.scientific.net/amm.701-702.498.

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This paper proposes a method of realizing a moving vehicle video detecting system based on DSP processor, and describes the system's hardware architecture and software design in detail. Based on the characteristic of dual-core of DM6437 processor, the methods of communication protocol between ARM and DSP, as well as the double-buffer switching method are presented. Background modeling is made on the traffic video data from DM6437 via difference accumulation. Background subtraction is used to detect vehicle movement areas. With the adoption of algorithms such as Otsu, morphological filtering and region growing, the whole system is finally realized on the DM6446 hardware platform. Experimental results show that the system achieves good performance on moving vehicle detection.

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44

ISKANDARANI, MAHMOUD Z. "MATHEMATICAL MODELING OF THE PROGRAMING FIELD IN A NEURAL SWITCH USING THE SEMI-INFINITE COPLANAR ELECTRODE APPROXIMATION". Advances in Complex Systems 09, n.º 03 (septiembre de 2006): 193–207. http://dx.doi.org/10.1142/s021952590600080x.

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The design and mathematical modeling of the programing electric field in a neural switch is carried out. The specified function for the switch is to operate as a synaptic processor behaving in an adaptive manner and suitable to be used as a compact programable device with other artificial neural network hardware. Modeling of the switch is carried out by means of complex mathematical analysis employing the Schwarz–Christoffel transform. The effect of inter-electrode separation on the field strength is analyzed in two dimensions. The realized power law function of the programing field is discussed and explained.

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45

A S, Asif Ahmad. "A Cost Effective DVI interface on Virtex-5 FPGA Through Verilog HDL". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 13, n.º 2 (12 de abril de 2014): 4230–36. http://dx.doi.org/10.24297/ijct.v13i2.2905.

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There is a definite need for video and image processing technologies in today's world. However the computer vision technologies need to be tested and optimized. There is need for testing these interfaces for the platform which we work on. This modeling is a cost effective architecture for interfacing Digital Visual Interface(DVI) on Virtex5 FPGA's. The architecture is modeled in such a way that it does not use XPS micro blaze or Power PCÂ processor but simple pixel feeder design, configuration of the Chrontel 7301C chip design and the interface between them.

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46

Zaitsev, Vladimir y Evgeniy Tsybaev. "Estimation of timing characteristics in real-time computer systems using Petri nets". Management of Development of Complex Systems, n.º 54 (2 de junio de 2023): 48–62. http://dx.doi.org/10.32347/2412-9933.2023.54.48-62.

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The work is devoted to the problem of determining the time characteristics of tasks in real-time systems, the success of which depends not only on their logical correctness, but also on the time for which they receive the result. Determining such time characteristics of the system at the design stage is a rather difficult problem. Its solution is currently based on the use of two main methods: theoretical calculations related to the calculation of the so-called feasibility criteria and modeling of the system's operation on models. Among the models, statistical models of mass service systems are the most widespread. However, in both the first and second options, it is impossible to obtain a guaranteed result, which significantly complicates the design process. Recently, it has been proposed to use the methods of researching models based on the use of the Petri net apparatus. The paper proposes a method for estimating the time characteristics of tasks in real-time systems by means of data analysis. Obtained by modeling the distribution of processor time between tasks according to the selected algorithms of the scheduler by using a model of the software system in the form of a Petri net. The paper proposes a method for estimating the time characteristics of tasks in real-time systems by means of data analysis. Obtained by modeling the distribution of processor time between tasks according to the selected algorithms of the scheduler by using a model of the software system in the form of a Petri net. The method guarantees obtaining the time characteristics of the tasks when choosing specific types of processor and scheduler, which is required to start the technical design of the real-time system. The use of the proposed mathematical model and a package of application programs allow, at the early stages of the development of a real-time system, to determine the real terms of tasks and choose the optimal option for the implementation of technical and lost support. The proposed mathematical models are based on determining the time characteristics of program execution by modeling the distribution of processor time between tasks, subject to the prior selection of planning algorithms and the characteristics of a complex of technical means. The research is based on the use of simulated statistical models and Petri net models, The use of the proposed tools allows you to significantly reduce the time of analysis of possible options for real-time system implementation, increases the quality of the project and significantly reduces the overall time and cost of the entire development. The paper examines in detail the process of modeling a multitasking computer system using a Petri net device. A concrete example shows the simulation of the operation of a complex of programs, including the development of simulation algorithms, the listing of the simulation program, and the analysis of the obtained results.

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47

Lee, Ki Dong, Bum Hee Lee y Myoung Sam Ko. "A comparative model-based analysis and design for multi-robot systems". Robotica 13, n.º 1 (enero de 1995): 65–76. http://dx.doi.org/10.1017/s0263574700017495.

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SummaryFor a robotic workcell with multiple robots, several interconnection methods are presented in terms of a processor-based architecture. The concept of the multiple processor system (MPS) or multiple computer system (MCS) is used to formulate and analyze the multi-robot interconnection system (MRIS). The MRIS is modelled as a queueing network, and mathematical analysis is done on the basis of modelling. Performance evaluation is achieved for the MRIS through the mean value analysis with the response time and the probability of service failure under different workloads. The results together with some comments suggest a useful guideline for a selecting an appropriate interconnection method for the MRIS subject to the system environment and application.

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48

Diehl, Joao B. y Eduardo W. Bergamini. "The L language for parallel processor machines". SIMULATION 58, n.º 1 (enero de 1992): 49–61. http://dx.doi.org/10.1177/003754979205800108.

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49

YADAV, PRADEEP KUMAR, M. P. SINGH y KULDEEP SHARMA. "TASK ALLOCATION MODEL FOR RELIABILITY AND COST OPTIMIZATION IN DISTRIBUTED COMPUTING SYSTEM". International Journal of Modeling, Simulation, and Scientific Computing 02, n.º 02 (junio de 2011): 131–49. http://dx.doi.org/10.1142/s179396231100044x.

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A Distributed Computing System (DCS) is defined as a set of processing elements interconnected by communication links. Reliability analysis of these processing elements and communication links is one of the important parameters to achieve the system efficiency. The system efficiency can be improved by making the task allocation properly in DCS. In this paper, we have presented a mathematical model, considering DCS with heterogeneous processors in order to achieve optimal cost and optimal reliability by allocating the tasks to the processors, in such a way that the allocated load on each processor is balanced. The task allocation in DCS is known as NP-hard problem even in the best conditions, and based on the present model, an efficient algorithm have been proposed to obtain optimal solutions. To design the mathematical model, execution time of the tasks on each processor as well as communication time between the tasks has been taken in the form of matrices.

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Beaman, Brian y Jean Audet. "High Current Testing and Simulation for Land Grid Array Sockets". International Symposium on Microelectronics 2017, n.º 1 (1 de octubre de 2017): 000659–62. http://dx.doi.org/10.4071/isom-2017-poster3_002.

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Abstract Land grid array (LGA) sockets are commonly used for industry standard and custom microprocessors to meet the increased performance challenges for a variety of server applications. Along with the need for increased high speed signaling capabilities comes the challenge to support lower voltages and higher currents. Typical testing that is conducted by the LGA socket suppliers does not provide an accurate assessment of the maximum current capabilities in a real product application due to the test card design and construction limitations. Typical test card designs use daisy chain connections to wire multiple LGA socket contacts in series. The daisy chain wiring in the test card adds to the resistive heating and results in an inaccurate maximum current rating. Also, the test cards typically do not have a cross section construction that is representative of a real product application with multiple ground planes that provide improved thermal dissipation of the heat generated by the LGA socket interface. Hardware testing was conducted to better understand the performance limitations for a new product application. The test card was designed to use multiple voltage and ground planes in the circuit card cross section to provide a low impedance path for current flow and a low voltage drop through the LGA socket interface. In addition to the test card construction, the test hardware included a special test module with a shorted chip to provide a more accurate power distribution path through the socket and processor package. The test variables included different plating metallurgy options for the LGA socket and the processor module along with different configurations for the voltage supply and ground return contacts. Electrical and thermal modeling techniques were used to simulate the test hardware configuration with good correlation between the hardware and modeling results. Based on the positive correlation results, additional modeling was conducted to simulate the worst case power mapping conditions for the processor chip along with a more accurate power distribution. The additional modeling results provided further insights into the maximum current capabilities for the LGA socket based on the temperature increase from the resistive heating in the socket contacts.

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