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Literatura académica sobre el tema "Modeling of processor design"

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Publicado: 25 de mayo de 2024

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Artículos de revistas sobre el tema "Modeling of processor design"

Li, Lei, Hai-bin Shen, Kai Huang, Xiao-lang Yan, Han Sangil y Ahmed A Jerraya. "Distributed Memory Service Modeling in Multi-Processor Design". Journal of Electronics & Information Technology 30, n.º 11 (14 de abril de 2011): 2750–54. http://dx.doi.org/10.3724/sp.j.1146.2007.00596.

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Eyerman, Stijn y Lieven Eeckhout. "Probabilistic job symbiosis modeling for SMT processor scheduling". ACM SIGPLAN Notices 45, n.º 3 (5 de marzo de 2010): 91–102. http://dx.doi.org/10.1145/1735971.1736033.

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Lee, Je-Hoon. "Power Modeling Framework for an Asynchronous Processor". Journal of Circuits, Systems and Computers 25, n.º 06 (31 de marzo de 2016): 1650057. http://dx.doi.org/10.1142/s0218126616500572.

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This paper presents two power models for an asynchronous processor, A8051. The first one is a pipeline accurate model which models power consumption at each pipeline stage. The other one is a micro-architectural model which models power consumption at micro-operation level. Then, we demonstrate the feasibility of the proposed approach on an A8051 processor case study. The experimental results based on applying the proposed pipeline-accurate and micro-architectural power models on an A8051 processor demonstrate that the proposed power models have high accuracy with simulation times much faster than the conventional low-level power simulator. It also shows similar results compared to the conventional power model for a synchronous processor. Even though the simulation speeds for the proposed power models are approximately 100–900 times faster than the low-level power simulator, the differences are less than 18% and 15%, respectively. Thus, the proposed power models can give a guide for SoC designers who want to integrate the asynchronous processor for low-power SoC design.

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LIN, S., Y. CHEN, C. YU, Y. LIU y C. LEE. "Dynamic modeling and control structure design of an experimental fuel processor". International Journal of Hydrogen Energy 31, n.º 3 (marzo de 2006): 413–26. http://dx.doi.org/10.1016/j.ijhydene.2005.06.027.

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Wu, Wei, Shu-Bo Yang, Jenn-Jiang Hwang y Xinggui Zhou. "Design, modeling, and optimization of a lightweight MeOH-to-H2 processor". International Journal of Hydrogen Energy 43, n.º 31 (agosto de 2018): 14451–65. http://dx.doi.org/10.1016/j.ijhydene.2018.05.135.

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So, Hwisoo, Yohan Ko, Jinhyo Jung, Kyoungwoo Lee y Aviral Shrivastava. "gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration". Electronics 12, n.º 22 (8 de noviembre de 2023): 4573. http://dx.doi.org/10.3390/electronics12224573.

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With aggressive technology scaling, soft errors have become a major threat in modern computing systems. Several techniques have been proposed in the literature and implemented in actual devices as countermeasures to this problem. However, their effectiveness in ensuring error-free computing cannot be ascertained without an accurate reliability estimation methodology. This can be achieved by using the vulnerability metric: the probability of system failure as a function of the time the program data are exposed to transient faults. In this work, we present a gemV-tool, a comprehensive toolset for estimating system vulnerability, based on the cycle-accurate gem5 simulator. The three main characteristics of the gemV-tool are: (i) fine-grained modeling: vulnerability modeling at a fine-grained granularity through the use of RTL abstraction; (ii) accurate modeling: accurate vulnerability calculation of speculatively executed instructions; and (iii) comprehensive modeling: vulnerability estimation of all the sequential elements in the out-of-order processor core. We validated our vulnerability models through extensive fault injection campaigns with <3% correlation error and 90% statistical confidence. Using the gemV-tool, we made the following observations: (i) the vulnerability of two microarchitectural configurations with similar performance can differ by 82%; (ii) the vulnerability of a processor can vary by more than 10×, depending on the implemented algorithm; and (iii) the vulnerability of each component in the processor varies significantly, depending on the ISA of the processor.

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Kumar, K. S. y J. H. Tracey. "Modeling and Description of Processor-Based Systems with DTMSII". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 1 (enero de 1987): 116–27. http://dx.doi.org/10.1109/tcad.1987.1270254.

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Martin, Grant. "Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors". Journal of Signal Processing Systems 53, n.º 1-2 (29 de noviembre de 2007): 113–27. http://dx.doi.org/10.1007/s11265-007-0153-7.

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Martono y Zulfi. "Perancangan Aplikasi Point of Sale (POS) pada Karya Maju Jaya". Jurnal PROCESSOR 17, n.º 2 (28 de octubre de 2022): 114–24. http://dx.doi.org/10.33998/processor.2022.17.2.1266.

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Karya maju jaya is one of the shops that engaged in the provision of services and goods in the form of workshops. Currently at karya maju Jaya, the process of managing transactions and financial reports still uses paper media as a means of storing data, causing many weaknesses in terms of security, effectiveness from the aspect of time, higher costs to the high possibility of errors in processing and processing information. Therefore, the author decided to conduct a research that the author gave the title point of sale (POS) application design on the work of karya maju jaya with the aim of answering all the problems above. The point of sale (POS) application in this study will be described using use case diagrams and class diagrams modeling. The final product of the research that the author did in this research is a point of sale (POS) application that allows application users to process product data, manage transaction data, manage reports, manage invoices, manage profiles, change passwords, login and logout.

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Oliveira, Marcio F. da S., Eduardo W. Brião, Francisco A. Nascimento y Flávio R. Wagner. "Model Driven Engineering for MPSoC Design Space Exploration". Journal of Integrated Circuits and Systems 3, n.º 1 (18 de noviembre de 2008): 13–22. http://dx.doi.org/10.29292/jics.v3i1.277.

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This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the ever-growing challenge of designing complex embedded systems. This approach allows the designer to automatically select the most adequate modeling solution for application, platform, and mapping between application and platform, in an integrated and simultaneous way and at a very early design stage, before system synthesis and code generation have been performed. The exploration is based on high-level estimates of physical characteristics of each candidate solution. In an experimental setting, the DSE tool automatically performs four design activities: it selects the number of processors, maps tasks to processors, allocates processors to bus segments, and sets the voltage of each processor. Experimental results, extracted from a DSE scenario for a real application, show that the proposed estimation and exploration approach may find a suitable solution regarding the design requirements and constraints in a very short time, with an acceptable accuracy, without relying on costly synthesis-and-simulation cycles.

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Tesis sobre el tema "Modeling of processor design"

Chen, Yuan. "High level modelling and design of a low powered event processor". Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500939.

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With the fast development of semiconductor technology, more and more Intellectual Property (IP cores) can be integrated into one chip under the Globally Asynchronous and Locally Synchronous (GALS) architecture. Power becomes the main restriction of the System-on-Chip (SOC) performance especially when the chip is used in a portable device. Many low power technologies have been proposed and studied for IP core's design. However, there is a shortage of system level power management schemes (policies) for the GALS architecture. In particular, the area of using Dynamic Power Management (DPM) to optimize SOC power dissipation under latency restriction ains relatively unexplored. This thesis describes the work of modelling and design of an asynchronous event coprocessor to control the operations of an IP core in the GALS architecture.

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Popescu, Catalin Nicolae. "Modeling and control of extrusion coating". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13700.

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Yuan, Fangfang. "Assessing the impact of processor design decisions on simulation based verification complexity using formal modeling with experiments at instruction set architecture level". Thesis, University of Bristol, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.566838.

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The Instruction Set Architecture (ISA) describes the key functionalities of a processor design and is the most comprehensible format for enabling humans to understand the structure of the entire processor design. This thesis first introduces the construction of a generic ISA formal model with mathematical notations rather than programming languages, and demonstrates the extensions towards specific ISA designs. The stepwise refinement modeling technique gives rise to the hierarchically structured model, which eases the overall comprehensibility of the ISA and reduces the effort required for modeling similar designs. The ISA models serve as self-consistent, complete, and unambiguous specifications for coding, while helping engineers explore different design options beforehand. In the design phase, a selection of features is available to architects in order for the design to be trimmed towards a particular optimization target, e.g. low power consumption or fast computation, which can be assessed before implementation. However, taking verification into consideration, there is to my knowledge no way to estimate the difficulty of verifying a design before coding it. There needs to be a platform and a metric, from which both functional and non-functional properties can be quantitatively represented and then compared before implementation. Hence, this thesis secondly pro- poses a metric, based on the formally reasoned extension of the generic ISA models, as an estimator of some non-functional property, i.e. the verification complexity for achieving verification goals. The main claim of this thesis is that the verification complexity in simulation-based verification can be accurately retrieved from a hierarchically constructed ISA formal model in which the functionalities are fully specified with the correctness preserved. The modeling structure allows relative comparisons at a reasonably high level of abstraction brought by the hierarchically constructed formalization. The analysis on the experimental ISA emulator assesses the quality of the metric and concludes the applicability of the proposed metric.

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Prasai, Anish. "Methodologies for Design-Oriented Electromagnetic Modeling of Planar Passive Power Processors". Thesis, Virginia Tech, 2006. http://hdl.handle.net/10919/34164.

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The advent and proliferation of planar technologies for power converters are driven in part by the overall trends in analog and digital electronics. These trends coupled with the demands for increasingly higher power quality and tighter regulations raise various design challenges. Because inductors and transformers constitute a rather large part of the overall converter volume, size and performance improvement of these structures can subsequently enhance the capability of power converters to meet these application-driven demands. Increasing the switching frequency has been the traditional approach in reducing converter size and improving performance. However, the increase in switching frequency leads to increased power loss density in windings and core, with subsequent increase in device temperature, parasitics and electromagnetic radiation. An accurate set of reduced-order modeling methodologies is presented in this work in order to predict the high-frequency behavior of inductors and transformers. Analytical frequency-dependent expressions to predict losses in planar, foil windings and cores are given. The losses in the core and windings raise the temperature of the structure. In order to ensure temperature limitation of the structure is not exceeded, 1-D thermal modeling is undertaken. Based on the losses and temperature limitation, a methodology to optimize performance of magnetics is outlined. Both numerical and analytical means are employed in the extraction of transformer parasitics and cross-coupling. The results are compared against experimental measurements and are found to be in good accord. A simple near-field electromagnetic shield design is presented in order to mitigate the amount of radiation. Due to inadequacy of existing winding technology in forming suitable planar windings for PCB application, an alternate winding scheme is proposed which relies on depositing windings directly onto the core.
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Qian, Zhiguang. "Computer experiments [electronic resource] : design, modeling and integration /". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11480.

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The use of computer modeling is fast increasing in almost every scientific, engineering and business arena. This dissertation investigates some challenging issues in design, modeling and analysis of computer experiments, which will consist of four major parts. In the first part, a new approach is developed to combine data from approximate and detailed simulations to build a surrogate model based on some stochastic models. In the second part, we propose some Bayesian hierarchical Gaussian process models to integrate data from different types of experiments. The third part concerns the development of latent variable models for computer experiments with multivariate response with application to data center temperature modeling. The last chapter is devoted to the development of nested space-filling designs for multiple experiments with different levels of accuracy.

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Zhang, Qiang. "Process modeling of innovative design using systems engineering". Thesis, Strasbourg, 2014. http://www.theses.fr/2014STRAD007/document.

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Nous développons des modèles de processus pour décrire et gérer efficacement la conception innovante, en suivant la méthodologie DRM. D'abord, nous présentons un modèle descriptif de la conception innovante. Ce modèle reflète les processus fondamentaux qui sont utiles pour comprendre les différentes dimensions et étapes impliqués dans la conception innovante. Il permette aussi de localise les possibilités d'innovation dans ce processus, et se focalise sur les facteurs internes et externes qui influencent le succès. Deuxièmement, nous effectuons une étude empirique pour étudier la façon dont le contrôle et la flexibilité peuvent être équilibrés pour gérer l'incertitude dans la conception innovante. Après avoir identifié les pratiques de projets qui traitent de ces incertitudes en termes de contrôle et de flexibilité, des études de cas sont analysés. Cet exemple montre que le contrôle et la flexibilité peuvent coexister. En se basant sûr les résultats managériaux issu de cette étude empirique, nous développons un modèle procédurale de processus et un modèle adaptatif à base d’activité. Le premier propose le cadre conceptuel pour équilibrer l'innovation et le contrôle par la structuration des processus au niveau du projet et par l'intégration des pratiques flexibles au niveau opérationnel. Le second modèle considère la conception innovante comme un système adaptatif complexe. Il propose ainsi une méthode de conception qui construit progressivement l'architecture du processus de la conception innovante. Enfin, les deux modèles sont vérifiées en analysant un certain nombre de processus et en faisant des simulations au sein de trois projets de conception innovante
We develop a series of process models to comprehensively describe and effectively manage innovative design in order to achieve adequate balance between innovation and control, following the design research methodology (DRM). Firstly, we introduce a descriptive model of innovative design. This model reflects the actual process and pattern of innovative design, locates innovation opportunities in the process and supports a systematic perspective whose focus is the external and internal factors affecting the success of innovative design. Secondly, we perform an empirical study to investigate how control and flexibility can be balanced to manage uncertainty in innovative design. After identifying project practices that cope with these uncertainties in terms of control and flexibility, a case-study sample based on five innovative design projects from an automotive company is analyzed and shows that control and flexibility can coexist. Based on the managerial insights of the empirical study, we develop the procedural process model and the activity-based adaptive model of innovative design. The former one provides the conceptual framework to balance innovation and control by the process structuration at the project-level and the integration of flexible practices at the operation-level. The latter model considers innovative design as a complex adaptive system, and thereby proposes the method of process design that dynamically constructs the process architecture of innovative design. Finally, the two models are verified by supporting a number of process analysis and simulation within a series of innovative design projects

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Satyanarayana, Srinath. "Fixture-workpiece contact modeling for a compliant workpiece". Thesis, Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/17874.

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Panchal, Jitesh H. "A framework for simulation-based integrated design of multiscale products and design processes". Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-11232005-112626/.

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Thesis (Ph. D.)--Mechanical Engineering, Georgia Institute of Technology, 2006.
Eastman, Chuck, Committee Member ; Paredis, Chris, Committee Co-Chair ; Allen, Janet, Committee Member ; Rosen, David, Committee Member ; Tsui, Kwok, Committee Member ; McDowell, David, Committee Member ; Mistree, Farrokh, Committee Chair. Includes bibliographical references.

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Cui, Song. "Hardware mapping of critical paths of a GaAs core processor for solid modelling accelerator /". Title page, contents and abstract only, 1996. http://web4.library.adelaide.edu.au/theses/09PH/09phc9661.pdf.

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Perdikaki, Olga. "Modeling the work center design problems for thermal processes in semiconductor manufacturing". [Gainesville, Fla.] : University of Florida, 2003. http://purl.fcla.edu/fcla/etd/UFE0001451.

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Libros sobre el tema "Modeling of processor design"

Yagiu, Takaaki, ed. Modeling Design Objects and Processes. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-84420-1.

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Yagyū, T. Modeling design objects and processes. Berlin: Springer-Verlag, 1991.

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Yagyū, Takaaki. Modeling design objects and processes. Berlin: Springer-Verlag, 1991.

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Modeling Design Objects and Processes. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991.

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Modeling of chemical kinetics and reactor design. Boston, MA: Gulf Professional Pub., 2001.

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Modeling, analysis, design, and control of stochastic system. New York: Springer, 1999.

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Gigch, John P. Van. System design modeling and metamodeling. New York: Plenum Press, 1991.

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Mayr, Herwig. Virtual automation environments: Design, modeling, visualization, simulation. New York: Marcel Dekker, 2002.

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Environmental systems and processes: Principles, modeling, and design. New York: Wiley-Interscience, 2001.

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Johan, Marklund, ed. Business process modeling, simulation, and design. Upper Saddle River, NJ: Pearson/Prentice Hall, 2004.

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Capítulos de libros sobre el tema "Modeling of processor design"

Nurmi, Tero, Tapani Ahonen y Jari Nurmi. "Early-Estimation Modeling of Processors". En Processor Design, 391–404. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5530-0_17.

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Reijers, Hajo A. "Workflow Modeling". En Design and Control of Workflow Processes, 31–59. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-36615-6_2.

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Farrington, P. A., J. J. Swain y S. L. Messimer. "Systems modeling and simulation". En Integrated Product, Process and Enterprise Design, 435–64. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6383-9_14.

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Laguna, Manuel y Johan Marklund. "Introduction to Queuing Modeling". En Business Process Modeling, Simulation and Design, 187–256. Third Edition. | Boca Raton, FL : CRC Press, [2019] | Revised edition of the authors’ Business process modeling, simulation, and design, [2013]: Chapman and Hall/CRC, 2018. http://dx.doi.org/10.1201/9781315162119-6.

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Choi, W. P. y L. M. Cheng. "Modelling the Crypto-Processor from Design to Synthesis". En Cryptographic Hardware and Embedded Systems, 25–36. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48059-5_4.

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Ermolayev, Vadim, Eyck Jentzsch, Oleg Karsayev, Natalya Keberle, Wolf-Ekkehard Matzke y Vladimir Samoylov. "Modeling Dynamic Engineering Design Processes in PSI". En Perspectives in Conceptual Modeling, 119–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11568346_14.

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Schürmann, Bernd. "Modeling Design Data and Design Processes in the PLAYOUT CAD Framework". En Current Issues in Electronic Modeling, 161–89. Boston, MA: Springer US, 1996. http://dx.doi.org/10.1007/978-1-4613-1347-2_5.

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Chew, Eng, Igor Hawryszkiewycz y Michael Soanes. "Modeling Requirements for Value Configuration Design". En Business Process Management Workshops, 169–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78238-4_18.

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Kreimeyer, Matthias y Udo Lindemann. "Modeling the structure of design processes". En Complexity Metrics in Engineering Design, 101–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-20963-5_4.

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Aldini, Alessandro, Flavio Corradini y Marco Bernardo. "Component-Oriented Modeling". En A Process Algebraic Approach to Software Architecture Design, 127–67. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84800-223-4_4.

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Actas de conferencias sobre el tema "Modeling of processor design"

Rajesh, V. y R. Moona. "Processor modeling for hardware software codesign". En Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013). IEEE, 1999. http://dx.doi.org/10.1109/icvd.1999.745137.

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Pekkarinen, Esko y Timo D. Hamalainen. "Modeling RISC-V Processor in IP-XACT". En 2018 21st Euromicro Conference on Digital System Design (DSD). IEEE, 2018. http://dx.doi.org/10.1109/dsd.2018.00036.

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Noonan, L. "Modeling a network processor using object oriented techniques". En Euromicro Symposium on Digital System Design, 2004. DSD 2004. IEEE, 2004. http://dx.doi.org/10.1109/dsd.2004.1333314.

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Kitamichi, Junji, Koji Ueda y Kenichi Kuroda. "A Modeling of a Dynamically Reconfigurable Processor Using SystemC". En 2008 21st International Conference on VLSI Design. IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.13.

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Wang, Bingrui, Qihui Zhang, Tianyong Ao y Mingju Huang. "Design of Pipelined FFT Processor Based on FPGA". En 2010 Second International Conference on Computer Modeling and Simulation (ICCMS). IEEE, 2010. http://dx.doi.org/10.1109/iccms.2010.112.

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Zhou, Hu-lin y Mei Xie. "Iris Biometic Processor Enhanced Module FPGA-Based Design". En 2010 Second International Conference on Computer Modeling and Simulation (ICCMS). IEEE, 2010. http://dx.doi.org/10.1109/iccms.2010.79.

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Tsertov, Anton, Raimund Ubar, Artur Jutman y Sergei Devadze. "SoC and Board Modeling for Processor-Centric Board Testing". En 2011 14th Euromicro Conference on Digital System Design (DSD). IEEE, 2011. http://dx.doi.org/10.1109/dsd.2011.79.

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Xing, Yue, Huaixi Lu, Aarti Gupta y Sharad Malik. "Leveraging Processor Modeling and Verification for General Hardware Modules". En 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021. http://dx.doi.org/10.23919/date51398.2021.9474194.

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Cope, Ben, Peter Y. K. Cheung y Wayne Luk. "Systematic design space exploration for customisable multi-processor architectures". En 2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). IEEE, 2008. http://dx.doi.org/10.1109/icsamos.2008.4664847.

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Chen-Kang Lo, Li-Chun Chen, Meng-Huan Wu y Ren-Song Tsay. "Cycle-count-accurate processor modeling for fast and accurate system-level simulation". En 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763060.

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Informes sobre el tema "Modeling of processor design"

Barnes, Edwin, Sophia Economou, Nicholas Mayhall y Kyungwha Park. Ab Initio Quantum Information Processor Design with Single-Molecule Magnets: a Multiscale Modeling Approach: Final Technical Report. Office of Scientific and Technical Information (OSTI), enero de 2023. http://dx.doi.org/10.2172/1923906.

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Gattiker, James. Energy Systems Process Modeling, Analysis, and Experiment Design. Office of Scientific and Technical Information (OSTI), noviembre de 2021. http://dx.doi.org/10.2172/1832356.

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Sun, Lushan y Jean Parsons. 3D Printing for Apparel Design: Exploring Apparel Design Process using 3D Modeling Software. Ames: Iowa State University, Digital Repository, 2014. http://dx.doi.org/10.31274/itaa_proceedings-180814-915.

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Woods, Mark y Michael Matuszewski. Quality Guideline for Energy System Studies: Process Modeling Design Parameters. Office of Scientific and Technical Information (OSTI), enero de 2012. http://dx.doi.org/10.2172/1513276.

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Zoelle, Alexander. Quality Guidelines for Energy System Studies: Process Modeling Design Parameters. Office of Scientific and Technical Information (OSTI), junio de 2019. http://dx.doi.org/10.2172/1570826.

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Nordham, David J. Automated Ship Auxiliary Systems Design Process -- Ship Parametric Modeling Program. Fort Belvoir, VA: Defense Technical Information Center, marzo de 1993. http://dx.doi.org/10.21236/ada261834.

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Weijters, Bert. Survey Design and Analysis. Instats Inc., 2023. http://dx.doi.org/10.61700/hl5ql4rwahbm1469.

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This seminar will teach you the most current best practices for survey design and analysis. This involves conceptually and statistically modeling, through hands-on exercises, measurement as (a) the selection of indicators of latent constructs, (b) data collection as a psychological process of survey responding, and then (c) specifying and testing measurement models that are able to adequately reflect this process (using CFA). Day 1 offers a conceptual introduction and then a variety of hands-on applications are covered in Mplus on Day 2, and lavaan in R on Day 3. An official Instats certificate of completion is provided at the conclusion of the seminar. The seminar offers 2 ECTS Equivalent points for European PhD students.

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Thies, Mark C., J. P. O'Connell y Maximilian B. Gorensek. The Sulfur-Iodine Cycle: Process Analysis and Design Using Comprehensive Phase Equilibrium Measurements and Modeling. Office of Scientific and Technical Information (OSTI), enero de 2010. http://dx.doi.org/10.2172/969923.

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Weijters, Bert. Survey Design and Analysis + 2 Free Seminars. Instats Inc., 2022. http://dx.doi.org/10.61700/8i3fttx07v1y7469.

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This seminar will teach you the most current best practices for survey design and analysis. This involves conceptually and statistically modeling, through hands-on exercises, measurement as (a) the selection of indicators of latent constructs, (b) data collection as a psychological process of survey responding, and then (c) specifying and testing measurement models that are able to adequately reflect this process (using CFA). Day 1 offers a conceptual introduction and then a variety of hands-on applications are covered in Mplus on Day 2, and lavaan in R on Day 3. To help frame the exploration of measurement models, two free background seminars are provided when enrolling in this seminar: CFA/SEM in R and CFA/SEM in Mplus. An official Instats certificate of completion is provided at the conclusion of the seminar. The seminar offers 2 ECTS Equivalent points for European PhD students.

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Cherniavskyi, Ruslan, Yaroslav Krainyk y Anzhela Boiko. Modeling university environment: means and applications for university education. [б. в.], febrero de 2020. http://dx.doi.org/10.31812/123456789/3742.

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In the paper, we establish an investigation on the development of university 3D-model and its possible applications for educational and research fields. We assume that 3D-model of university can help in various scenarios and should be used to adopt modern immersing technologies into to university processes. Different means are employed for the development of the model. Bottom-up approach for using these means and their connection with each other are shown in the work. Then, details of the 3D-model design process are provided with peculiarities related to the university building location and corpuses positions. Finally, assembled models of university are shown in 3ds Max and Unity environments. In the final part of the paper, we suggest scenarios of model usage for educational and research fields. Universities can gain various benefits from integrating their research efforts to employ new technology and identify new development opportunities for both science and education in university. In case of the developed 3D-model, it is planned to use it in the projects connected with client-server applications, Internet-of-Things, Smart Grid, etc. In the educational process it will be a part of case-studies for learning 3D-modeling, development in Unity environment, training for emergency situations.

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