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Eby, Lawrence V. "MEMORIC FORM: POEM AS MEMORY." CSUSB ScholarWorks, 2014. https://scholarworks.lib.csusb.edu/etd/52.
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Machinist in the Snow is a narrative long poem, much like a novel in verse that deals with the loss of memory and environmental rebirth. In the book, the narrator exiles himself into a frozen nature and attempts to return the frozen wasteland into its former, flourishing environment. The poems take on the memoric form of memory in a wide range of poetic forms from the traditional sonnet, haiku, or villanelle, to a scattered projective verse. In the center of these poems is an attempt to mimic the mind in the way that it shifts, in its moments of clarity, and in its attempt to dissect and understand the surrounding realities. Through logic patterning, deep image, and introspection, these poems are meant to give insight into what it means to be human in the digital age and to highlight the dwindling connection to the pastoral that is so deeply rooted in American society.
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Emami, Kimia. "Memory." Thesis, Southern Illinois University at Edwardsville, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10128864.
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<p> I am a woman who was born and raised in Iran, a country that has undergone seismic changes throughout its history, from political to cultural ones, all of which have affected peoples’ ideologies for thousands of years. Like my peers, I have numerous personal concerns to explore in my work. I seek to represent the stark contrast between tradition and modernity in Iranian culture, which has leaked into different aspects of my life. Early on, this was the chief question that led me to develop a photography project while I was about to leave my home country. At that time my journey started based on this first series of work that I made. </p><p> After moving to the United States in 2013, I started to shape my ideas around my personal concerns over the cultural shock I had faced. Moving to a new nation and facing new people who think, act, behave, and talk differently altogether have all made me feel like a stranger. At that time I started to concentrate on issues revolving around the oppression of women throughout history by portraying my ideas through photos of human figures that later transformed into symbolic objects. At that phase, aesthetics of organic forms of Persian handwriting brought meanings into my abstraction. I employed poetry as a representation of the culture in which I belong. I dedicated my concentration to various layers of connotation through which form and content had a chance to shape and convey a cohesive reference. </p><p> Following my first year of graduate school I made a trip back to Iran during the summer of 2014. It dawned on me that the memories of my past versus the days of my present had generated a duality that transformed into an identity issue. This realization made me aware that I was becoming a totally different person while studying abroad. This transition led me to move from representing my inner feelings, and develop my language toward redefining my perception of time and space. This phase of my work was a mélange of photo and text presenting memory, culture, and history, and it formed the work in the thesis exhibition.</p>
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Weiss, Katherine. "Dieter Leisegang: Texts as Memory, Texts as Memoir." Digital Commons @ East Tennessee State University, 2012. https://dc.etsu.edu/etsu-works/2262.
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Morrison, Nia. "Ageing, memory performance and memory self-efficacy /." Title page, contents and abstract only, 1996. http://web4.library.adelaide.edu.au/theses/09ARPS/09arpsm881.pdf.
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Hall, Debbora. "Memory for rhythm and short-term memory." Thesis, University of York, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.495877.
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Griffiths, R. B. "Virtual memory systems using magnetic bubble memory." Thesis, Bucks New University, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.356215.
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Lee, Jack. "Smart Memory: An Inexact Content-Addressable Memory." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4605.
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The function of a Content-Addressable Memory (CAM) is to efficiently search the information stored in the memory, by using hardware rather than software with a corresponding improvement in searching speed. This hardware allows a parallel search by matching the data stored in memory to a search key rather than sequentially searching address by address as is done in a Random Access Memory. Although existing CAMs are more efficient in finding relevant information than RAM, there are additional improvements that can be made to further improve its efficiency. For example, previous CAMs use a word parallel searching scheme that can only identify exact matches. To find the best (closest) match, previous CAMs had to use bit serial approaches. Although still more efficient than RAM searching, these CAMs were limited by the word size (bit width) of the memory. Responding to this inefficiency, the CAM described in this thesis improves best-fit searching by using analog design in combination with digital design. This design retains a mismatch line to collect the result of the comparison of each bit of a word which is decoded by a simple flash A/D. This means that after a single operation the best-fit plus all words with zero to three bits of mismatch, are determined. This word/bit parallel searching makes this CAM more efficient than existing CAMs. The best-fit function of this CAM is good for database retrieval, communications and error correction circuitry. By using the high speed searching and the inexact match feature, this CAM also provides efficient sorting and set operations. The accumulated searching time is shortened when compared to regular CAM and RAM. The inexact CAM in this thesis is designed using mixed analog/digital design in a 2~ CMOS technology.
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Rocha, Carolina M. "Writing memory or memory writing Santo oficio de la memoria, La madriguera, El árbol de la gitana /." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3035969.
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Grilli, Matthew Dennis. "Self-Imagining, Recognition Memory, and Prospective Memory in Memory-Impaired Individuals with Neurological Damage." Thesis, The University of Arizona, 2009. http://hdl.handle.net/10150/193396.
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The present study investigated the reliability and robustness of a new mnemonic strategy - self-imagination - in a group of memory-impaired individuals with neurological damage. Despite severe memory deficits, almost all of the participants demonstrated a self-imagination effect (SIE) for recognition memory in study 1. Moreover, the ability to benefit from self-imagination was not affected by the severity of the memory deficit. In study 3, more than half of the participants showed a SIE on a task of event-based prospective memory. The data from study 2 suggest the SIE is not attributable to semantic processing or emotional processing and indicate that self-imagination is distinct from other mnemonic strategies. Overall the findings from the present study implicate self-imagination as a new and effective mnemonic strategy. The data also indicate that when it comes to memory there is something special about processing information in relation to the self.
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Lobe, Clifford. "Un-settling memory, cultural memory and post-colonialism." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ60207.pdf.
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Eastwood, Adrienne E. "Memory or attention?, understanding working memory in children." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/NQ65235.pdf.
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Manns, Joseph Robert. "Episodic memory, semantic memory, and the human hippocampus /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC IP addresses, 2002. http://wwwlib.umi.com/cr/ucsd/fullcit?p3061654.
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Schneider, Christiane N. "False-memory construction : the effect of memory confidence /." Electronic version (PDF), 2004. http://dl.uncw.edu/etd/2004/schneiderc/christianeschneider.pdf.
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Jag, Shaani. "Narrativising Episodic Memory: From Memory Episodes to Micronarratives." Thesis, School of Liberal Arts, 2023. https://ro.uow.edu.au/tharts/7.
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In the current literature on Episodic Memory (EM), mental representations are often assumed to stand out as the main view that promises to explain how we experience past personal events. However, proponents of Radical Enactive Cognition (REC) have argued that this view is empirically and theoretically inadequate due to issues with misremembering - failure to recall events in the past accurately - and the Hard Problem of Content (HPC) (Hutto & Myin 2013, 2017). This thesis aims to utilise REC’s already established framework and narrative formulations of memory to provide the tools needed to characterise episodic memory. The thesis turns to Narrativist Accounts (Gallagher 2008, 2003; Gallagher & Hutto 2008; Hutto 2016, Nelson & Fivush 2004; Rudd 2012; Schechtman 1996) and takes notice of the various capacities and requirements needed under these views and how they can serve as a model that can account for EM. However, under a Narrativist Account (NA), episodic memory is always embedded within autobiographical narratives. This raises the question of whether NAs can make room for any kind of episodic memory when conditions such as coherence, temporality and achievement of specific narrative capacities are required. By drawing from research on Dementia, Alzheimer’s, PTSD and Depression, along with non-pathological scenarios, this thesis demonstrates that stronger and moderate narrativist accounts do not provide room for explaining episodic memory. l propose that episodic experiences of the personal past can be seen in a different light when understood as Micronarratives. Micronarratives are marked out by being fixed or resistant to updating while identifying with a particular event in the past, even if it is not in the form of an accurate or true description. l defend that episodic memory, in this view, is not confronted with the same problems and offers a viable alternative.
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Sahrakorpi, Tiia. "Memory of the Third Reich in Hitler Youth memoirs." Thesis, University College London (University of London), 2018. http://discovery.ucl.ac.uk/10054634/.
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This thesis examines how the Hitler Youth generation represented their pasts in memoirs written in West Germany, post-unification Germany, and North America. Its aim is two-fold: to scrutinise the under-examined source base of memoirs and to demonstrate how representations of childhood, adolescence and maturation are integral to reconstructing memory of the Nazi past. It introduces the term ‘collected memoryscape’ to encapsulate the more nebulous multi-dimensional collective memory. Historical and literary theories nuance the reading of autobiography and memoirs as ego-documents, forming a new methodological basis for historians to consider. The Hitler Youth generation is defined as those individuals born between 1925 and 1933 in Germany, who spent the majority of their formative years under Nazi educational and cultural polices. The study compares published and unpublished memoirs, along with German and English-language memoirs, to examine constructions of personal and historical events. Some traumas, such as rapes, have only just resurfaced publicly - despite their inclusion in private memoirs since the 1940s. On a public level, West Germans underwent Vergangenheitsbewältigung (coming to terms with the past), these memoirs illustrate that, in the post-war period, private and generational memory reinterpretation continued in multitudinous ways. For example, even after the 1995 German Wehrmacht exhibitions, cohort members continued to express a fondness for the Waffen-SS or Wehrmacht in their writings. This thesis dialogically juxtaposes public and personal memory, also exploring how individuals experienced and represented controversial memories of Nazism. Overall, the cohort members employed three main narration methods: they normalised their childhood experiences; they silenced uncomfortable aspects of their past; and they cast themselves as victims as a coping mechanism, in order to achieve closure. This thesis argues for a more nuanced reading of Nazi-related memoirs and makes the case that public memory is not necessarily reflected on a personal level.
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Desiato, Pietro. "Memorie, supporting the practices of memory in the graveyard." Thesis, Malmö högskola, Institutionen för konst, kultur och kommunikation (K3), 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-23228.
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Due to its sensitive nature, the graveyard is often an avoided problem space within the field of design. This becomes evident from the lack of exploration and analysis in this domain. Anyhow, it represents an opportunity to test how design can mediate between sacred places, technology and people. Moreover, as a very specific context, the graveyard encompasses peculiar ways of interacting and experiencing space that deserve to be taken into account. This work discusses the notions of space and place and how the field of interaction design can benefit from them. In doing so, it investigates the hidden dimensions of the graveyard that make it a complex structure where spatial, personal and socio-cultural dimensions are intertwined. While the fieldwork aims at analysing the graveyard in its different tones of meaning (identity, memorial, cultural differences, on-site interaction) the focus of the work are the practices of memory and the role that the past has in our relation with the deceased. The result of the design process is an interactive audio system composed of a playback circuit based on Arduino and boxed into a seashell. The device is designed to be placed on the grave and store audio content. Once activated, the audio seashell allows listening and eventually recording vocal traces related to the deceased’s past. Taking into account the observed practices, rules and conventions that shape the graveyard, the role of personal and collective rituals and the meanings of all the identified artifacts, the designed system supports the experience of recalling memories in respect to the atmosphere, tempo and rhythm that characterise the graveyard.
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Pastawski, Fernando. "Quantum memory." Diss., lmu, 2012. http://nbn-resolving.de/urn:nbn:de:bvb:19-147039.
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Kellogg, Christopher James. "Visual memory." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/108869.
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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993.<br>Includes bibliographical references (leaves 90-92).<br>Visual memory supports computer vision applications by efficiently storing and retrieving spatiotemporal information. It is a unique combination of databases, spatial representation and indexing, and temporal representation and indexing. This thesis designs a visual memory architecture that meets the requirements of a number of computer vision applications. It also presents an implementation of part of this design in support of a scene monitoring prototype.<br>by Christopher James Kellogg.<br>M.S.
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Morel, Caroline Monique. "Walls || Memory." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/54032.
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We are all influenced by memories when we pursue acts of creation. However, these reminiscences are often fleeting and elusive; they rarely are formalized, nor are they explicit in the final artifact.
This work is based on a concrete representation of a childhood memory: the map of a city. The thesis explores ways to design and construct a place where others could, in turn, create their own memory. This place is located in Alexandria, VA, on South Fairfax Drive. It is an integrated mixed use program (Retails on the lower and ground levels, and residences on the 2 upper levels).
This experimentation invites further questions. How strictly should the concrete representation of the memory guide the design? What are the qualities of the spaces resulting of such rules? How to engage in the tension between the explicit memory's realm and the contemporary world? How to express their respective materiality?
|From| Memory of Walls |to| Walls of Memory<br>Master of Architecture
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Kastler, Robert Michael. "Photographic memory." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1316705103.
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Fabrizio, Maria. "Memory Created." VCU Scholars Compass, 2010. http://scholarscompass.vcu.edu/etd/2089.
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Memory is like afternoon light penetrating the windows of a fast moving car. The light coming through the trees creates images, reveals objects and faces, and introduces fluctuating sensations of warmth and coolness. Sometimes these images appear in logical sequences and at other times they are fleeting, surreal, and ambiguous. While memories are often presented linearly as fact, in actuality our stories only grasp at the truth. They are fragmented, imagined, and rearranged. By examining the intersection of reality and imagination in memories we see retelling as an act of creativity.
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Molenda, Morgan A. "Capturing Memory." VCU Scholars Compass, 2016. http://scholarscompass.vcu.edu/etd/4559.
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In my work, I present the moments of true emotional clarity and impactful memories from my life. I strive to provide insight into my experiences and my understanding of others’ motivations. The creative process helps safely guide me through memories of the past and understanding of others.
In my abstracted mixed media paintings and crafts, I use bold jewel tones to express strong feelings and passionate emotions. I also incorporate found objects and paints to communicate the layers and varied depth of memories. With the use of these varied materials, I have developed a personal symbolic language that allows me to relay aspects of my life and perceptions. My goal is to explore my past and invite the viewer into my experiences.
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Makin, Alexis David James. "Velocity memory." Thesis, University of Manchester, 2011. https://www.research.manchester.ac.uk/portal/en/theses/velocity-memory(c5c1c28d-0a23-44a5-93bc-21f993d2e7ad).html.
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It is known that primates are sensitive to the velocity of moving objects. We can also remember velocity information after moving objects disappear. This cognitive faculty has been investigated before, however, the literature on velocity memory to date has been fragmented. For example, velocity memory has been disparately described as a system that controls eye movements and delayed discrimination. Furthermore, velocity memory may have a role in motion extrapolation, i.e. the ability to judge the position of a moving target after it becomes occluded. This thesis provides a unifying account of velocity memory, and uses electroencephalography (EEG) to explore its neural basis. In Chapter 2, the relationship between oculomotor control and motion extrapolation was investigated. Two forms of motion extrapolation task were presented. In the first, participants observed a moving target disappear then reappear further along its path. Reappearance could be at the correct time, too early or too late. Participants discriminated reappearance error with a two-alternative forced choice button press. In the second task, participants saw identical targets travel behind a visible occluder, and they attempted to press a button at the exact time that it reached the other side. Tasks were completed under fixation and free viewing conditions. The accuracy of participant's judgments was reduced by fixation in both tasks. In addition, eye movements were systematically related to behavioural responses, and small eye movements during fixation were affected by occluded motion. These three results imply that common velocity memory and pre-motor systems mediate eye movements and motion extrapolation. In Chapter 3, different types of velocity representation were explored. Another motion extrapolation task was presented, and targets of a particular colour were associated with fast or slow motion. On identical-velocity probe trials, colour still influenced response times. This indicates that long-term colour-velocity associations influence motion extrapolation. In Chapter 4, interference between subsequently encoded velocities was explored. There was robust interference between motion extrapolation and delayed discrimination tasks, suggesting that common processes are involved in both. In Chapter 5, EEG was used to investigate when memory-guided tracking begins during motion extrapolation. This study compared conditions where participants covertly tracked visible and occluded targets. It was found that a specific event related potential (ERP) appeared around 200 ms post occlusion, irrespective of target location or velocity. This component could delineate the onset of memory guided tracking during occlusion. Finally, Chapter 6 presents evidence that a change in alpha band activity is associated with information processing during motion extrapolation tasks. In light of these results, it is concluded that a common velocity memory system is involved a variety of tasks. In the general discussion (Chapter 7), a new account of velocity memory is proposed. It is suggested that a velocity memory reflects persistent synchronization across several velocity sensitive neural populations after stimulus offset. This distributed network is involved in sensory-motor integration, and can remain active without visual input. Theoretical work on eye movements, delayed discrimination and motion extrapolation could benefit from this account of velocity memory.
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Muller, Felipe, and Federico Bermejo. "The Historical and Lived Sources of Collective Memory." Pontificia Universidad Católica del Perú, 2013. http://repositorio.pucp.edu.pe/index/handle/123456789/101565.
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The aim of the present paper is to study the role that lived and historical memories havein the conformation of collective memory through the participant’s appraisals in the recent past of Argentina. These memories operate as sources that nurture collective memory. Lived memories are related to live experiences, while historical memories are related to indirect sources that inform about the past. 60 participants, divided in two groups (above and below 46 years of age) appraised the present and recent past, based on lived and historical memories. Results show that lived or autobiographical and historical memories contribute differently to collective memory.<br>Se estudia el rol que desempeñan los recuerdos vividos e históricos en la memoria colectiva por medio de la valoración del pasado reciente argentino. Estos recuerdos operan como fuentes que nutren a la memoria colectiva. Los recuerdos vividos están vinculados a la experiencia directa, mientras que los recuerdos históricos a las fuentes indirectas que informan sobre el pasado. 60 participantes, divididos en dos grupos (mayores y menores de 46 años), realizaron valoraciones sobre el presente y el pasado reciente, en base a recuerdos vividos y en recuerdos históricos. Los resultados muestran que los recuerdos vividos o autobiográficos tienen una incidencia distinta en las valoraciones que los recuerdos históricos.
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Fredriksen, Lauren E. "The Impact of Memory Stereotype Threat on Memory and Memory Self-Efficacy in Older Adults." Xavier University Psychology / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=xupsy1593210266566016.
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Akhtar, Shazia. "Memory awareness and memory rehabilitation in mild cognitive impairment." Thesis, University of Leeds, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.424059.
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Gan, Yee Ling. "Redesigning the memory hierarchy for memory-safe programming languages." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/119765.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 69-75).<br>We present Hotpads, a new memory hierarchy designed from the ground up for modern, memory-safe languages like Java, Go, and Rust. Memory-safe languages hide the memory layout from the programmer. This prevents memory corruption bugs, improves programmability, and enables automatic memory management. Hotpads extends the same insight to the memory hierarchy: it hides the memory layout from software and enables hardware to take control over it, dispensing with the conventional flat address space abstraction. This avoids the need for associative caches and virtual memory. Instead, Hotpads moves objects across a hierarchy of directly-addressed memories. It rewrites pointers to avoid most associative lookups, provides hardware support for memory allocation, and unifies hierarchical garbage collection and data placement. As a result, Hotpads improves memory performance and efficiency substantially, and unlocks many new optimizations. This thesis contributes important optimizations for Hotpads and a comprehensive evaluation of Hotpads against prior work.<br>by Yee Ling Gan.<br>M. Eng.
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Sim, Jae Woong. "Architecting heterogeneous memory systems with 3D die-stacked memory." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53835.
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The main objective of this research is to efficiently enable 3D die-stacked memory and heterogeneous memory systems. 3D die-stacking is an emerging technology that allows for large amounts of in-package high-bandwidth memory storage. Die-stacked memory has the potential to provide extraordinary performance and energy benefits for computing environments, from data-intensive to mobile computing. However, incorporating die-stacked memory into computing environments requires innovations across the system stack from hardware and software. This dissertation presents several architectural innovations to practically deploy die-stacked memory into a variety of computing systems.
First, this dissertation proposes using die-stacked DRAM as a hardware-managed cache in a practical and efficient way. The proposed DRAM cache architecture employs two novel techniques: hit-miss speculation and self-balancing dispatch. The proposed techniques virtually eliminate the hardware overhead of maintaining a multi-megabytes SRAM structure, when scaling to gigabytes of stacked DRAM caches, and improve overall memory bandwidth utilization.
Second, this dissertation proposes a DRAM cache organization that provides a high level of reliability for die-stacked DRAM caches in a cost-effective manner. The proposed DRAM cache uses error-correcting code (ECCs), strong checksums (CRCs), and dirty data duplication to detect and correct a wide range of stacked DRAM failures—from traditional bit errors to large-scale row, column, bank, and channel failures—within the constraints of commodity, non-ECC DRAM stacks. With only a modest performance degradation compared to a DRAM cache with no ECC support, the proposed organization can correct all single-bit failures, and 99.9993% of all row, column, and bank failures.
Third, this dissertation proposes architectural mechanisms to use large, fast, on-chip memory structures as part of memory (PoM) seamlessly through the hardware. The proposed design achieves the performance benefit of on-chip memory caches without sacrificing a large fraction of total memory capacity to serve as a cache. To achieve this, PoM implements the ability to dynamically remap regions of memory based on their access patterns and expected performance benefits.
Lastly, this dissertation explores a new usage model for die-stacked DRAM involving a hybrid of caching and virtual memory support. In the common case where system’s physical memory is not over-committed, die-stacked DRAM operates as a cache to provide performance and energy benefits to the system. However, when the workload’s active memory demands exceed the capacity of the physical memory, the proposed scheme dynamically converts the stacked DRAM cache into a fast swap device to avoid the otherwise grievous performance penalty of swapping to disk.
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Roome, Hannah. "The accessibility of memory items in children's working memory." Thesis, Lancaster University, 2016. http://eprints.lancs.ac.uk/80979/.
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This thesis investigates the processes and systems that support recall in working memory. In particular it seeks to apply ideas from the adult-based dual-memory framework (Unsworth & Engle, 2007b) that claims primary memory and secondary memory are independent contributors to working memory capacity. These two memory systems are described as domain-general processes that combine control of attention and basic memory abilities to retain information. The empirical contribution comprises five experiments that specify how adults and children access, manage and report memory representations held in working memory. They provide a developmental perspective of the characteristics of these cognitive constructs. This thesis has combined traditional measures of primary and secondary memory (free recall) and methods used to classify individuals recall into the two independent systems, with new convergent paradigms in order to identify developmental trajectories of memory performance. The findings point towards qualitative and quantitative differences between how adults and children focus their recall from working memory. Primary and secondary memory capacities increase across childhood, but they seemingly develop at different rates. Between the ages of five- to ten-years children are reliant on the active maintenance of memory items within immediate memory, as controlled search and retrieval processes were far more demanding on children’s cognitive system. However, they did benefit from structured recall support and self-driven search processes, facilitating secondary memory. In addition, the experiments emphasised the impact of presentation modality on recall characteristics that are likely to be observed, and the susceptibility of information loss. Whilst auditory information reveals itself as highly accessible, it is also vulnerable to displacement and interference. In contrast visual representations appear to be more robust. Overall, the thesis will discuss the conceptual and empirical implications of whether the dual memory framework can help understand how working memory develops.
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Ritt, Jerome Simon Carleton University Dissertation Psychology. "Hypnosis, hypermnesia and memory distortion in long term memory." Ottawa, 1996.
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Whittemore, Stewart Neal. "Writing memory a study of memory tools in invention /." Diss., Connect to online resource - MSU authorized users, 2008.
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Klein, Olivier, Sabrina Pierucci, Cynthie Marchal, Alejandra Alarcón-Henríquez, and Laurent Licata. "“It had to happen”: Individual memory biases and collective memory." Pontificia Universidad Católica del Perú, 2012. http://repositorio.pucp.edu.pe/index/handle/123456789/100590.
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For the purpose of the study we varied the outcome of a sequence of ambiguous behaviors performed by an imaginary individual during World War II. Compared to a control condition where no outcome was presented, this person either ended up saving Jews (heroic behavior) or denouncing Jews to the Gestapo (cowardly behavior). After one week, behavioral antecedents that were consistent with the outcome were likely to be recalled and communicated. Results suggest a tendency towards forming extreme impressions of the target, depending on the outcome. These extreme impressions in turn guide the recall and evaluations of predictability, and also impact on communication about these episodes and thereby on the formation of collective memory.<br>Para el estudio se varió el resultado final de una secuencia ambigua de conductas realizadas por una persona ficticia durante la Segunda Guerra Mundial. Después de la secuencia ambigua de acciones, en una condición control no se producía ninguna consecuencia, en otra condición de heroísmo la persona salvaba la vida de Judíos y en otra condición de cobardía los denunciaba a la Gestapo. Los antecedentes congruentes con la conducta final se recordaron y comunicaron más una semana después. Esto sugiere una tendencia a inferir juicios extremos a partir de la conducta final del personaje, que a su vez influyen en el recuerdo en relación al nivel de previsibilidad de la conducta del personaje, e influyen en la comunicación sobre el hecho y la memoria colectiva.
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Crease, Michelle. "Thanks for the memory failures : priming memory fallibility and interpretations of prospective and retrospective memory failures." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44816.
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Retrospective memory is the cognitive function associated with recalling details from the past, (e.g., someone’s name) whereas prospective memory is the cognitive function associated with recalling an intention or plan in the future (e.g., attending a meeting). There is an interesting hypothesis that states prospective memory failures (e.g., forgetting about a meeting) tend to be interpreted as personality flaws while retrospective memory failures (e.g., forgetting someone’s name) tend to be interpreted as simply memory breakdowns. Recent research has supported this hypothesis, however little is known about the properties of the memory failures that might influence the biases in interpretations or the underlying cognitive processes of the effect.
Three experiments were designed to address these important issues. The first experiment examined sociality and importance of the memory failures as potential properties influencing interpretations. Participants were presented with memory failure vignettes that varied on these dimensions, and the bias towards personality flaw interpretations of prospective memory failures only occurred memory failures were social in nature. Furthermore, the effect was slightly weakened by the perspective from which the vignettes were written (the participant’s perspective). The second experiment developed a priming procedure that successfully induced a sense of self-perceived memory fallibility by requiring participants to generate examples of prospective and retrospective memory failures they had committed. In the third experiment this priming procedure was implemented prior to vignette interpretations with the objective of manipulating the interpretations bias. The results of Experiment 3 indicated that the priming manipulation reduced differences in the interpretations participants offered for prospective versus retrospective memory failures, particularly in terms of the seriousness, personality flaw, and poor memory interpretations of prospective failures. These results suggest that the priming procedure facilitated empathy the protagonist, and in this way reduced this interpretation bias.
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Ireland, Ryan P. "From Traditional Memory to Digital Memory Systems: A Rhetorical History of the Library as Memory Space." Miami University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=miami1461085550.
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Choi, David Suho. "Integration of non-volatile memory with volatile memory for embedded memory architectures and signal processing applications." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1692120591&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Shipstead, Zachary M. "The common elements of working memory capacity and fluid intelligence: primary memory, secondary memory and executive attention." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45757.
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Working memory is a mental system that is related to cognitive control and higher cognition. Although the topic of working memory is well researched, there is a great deal of debate about the mechanisms that drive individual differences in working memory capacity. Moreover, little is known about the direct relationships between different types of working memory tasks. The present study uses structural equation modeling to examine three varieties of working memory task: The complex span, running memory span, and visual arrays. It is found that, while complex and running span performance is directly predicted by immediate memory and retrieval from long-term memory, visual arrays is directly predicted by attention control. Despite these differences, all tasks are found to be united by executive attention, which is conceptualized as an executive process that is apparent across several types of attention and memory task. A second analysis examines the relationship between working memory and general fluid intelligence. It is concluded that, while executive attention accounts for the largest portion of the correlation between working memory and fluid intelligence, immediate memory and retrieval from long term memory are also critical to explaining this relationship.
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Dulong, Rémi. "Towards new memory paradigms : Integrating non-volatile main memory and remote direct memory access in modern systems." Electronic Thesis or Diss., Institut polytechnique de Paris, 2023. http://www.theses.fr/2023IPPAS027.
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Les ordinateurs modernes sont construits autour de deux éléments : leur CPU etleur mémoire principale volatile, ou RAM. Depuis les années 1970, ce principe a étéconstamment amélioré pour offrir toujours plus de fonctionnalités et de performances.Dans cette thèse, nous étudions deux paradigmes de mémoire qui proposent denouvelles façons d'interagir avec la mémoire dans les systèmes modernes : la mémoirenon-volatile et les accès mémoire distants. Nous mettons en œuvre des outils logicielsqui exploitent ces nouvelles approches afin de les rendre compatibles et d'exploiterleurs performances avec des applications concrètes. Nous analysons égalementl'impact des technologies utilisées, et les perspectives de leur évolution dans lesannées à venir.Pour la mémoire non-volatile, comme les performances de la mémoire sont essentiellespour atteindre le potentiel d'un CPU, cette fonctionnalité a historiquement été abandonnée.Même si les premiers ordinateurs ont été conçus avec des formes de mémoire nonvolatiles, les architectes informatiques ont commencé à utiliser la RAM volatilepour ses performances inégalées, et n'ont jamais remis en question cette décisionpendant des années. Cependant, en 2019, Intel a commercialisé un nouveau composantappelé Optane DCPMM qui rend possible l'utilisation de NVMM. Ce produit proposeune nouvelle façon de penser la persistance des données. Mais il remet égalementen question l'architecture de nos machines et la manière dont nous les programmons.Avec cette nouvelle forme de mémoire, nous avons implémenté NVCACHE, un cacheen mémoire non-volatile qui permet d'accélérer les interactions avec des supportsde stockage persistants plus lents, tels que les SSD. Nous montrons que NVCACHEest particulièrement performant pour les tâches qui nécessitent une granularitéélevée des garanties de persistance, tout en étant aussi simple à utiliser que l'interfacePOSIX traditionnelle. Comparé aux systèmes de fichiers conçus pour NVMM, NVCACHEpeut atteindre un débit similaire ou supérieur lorsque la mémoire non volatile estutilisée. De plus, NVCACHE permet aux programmes d'exploiter les performancesde NVMM sans être limité par la quantité de NVMM installée sur la machine.Un autre changement majeur dans le paysage informatique a été la popularité dessystèmes distribués. Alors que les machines ont individuellement tendance à atteindredes limites de performances, l'utilisation de plusieurs machines et le partage destâches sont devenus la nouvelle façon de créer des ordinateurs puissants. Bien quece mode de calcul permette d'augmenter le nombre de CPU utilisés simultanément,il nécessite une connexion rapide entre les nœuds de calcul. Pour cette raison,plusieurs protocoles de communication ont implémententé RDMA, un moyen delire ou d'écrire directement dans la mémoire d'un serveur distant. RDMA offre defaibles latences et un débit élevé, contournant de nombreuses étapes de la pileréseau.Cependant, RDMA reste limité dans ses fonctionnalités natives. Par exemple, iln'existe pas d'équivalent de multicast pour les fonctions RDMA les plus efficaces.Grâce à un switch programmable (le switch Intel Tofino), nous avons implémentéun mode spécial pour RDMA qui permet de lire ou d'écrire sur plusieurs serveursen même temps, sans pénalité de performances. Notre système appelé Byp4ss faitparticiper le switch aux transferts, en dupliquant les paquets RDMA. Grâce à Byp4ss,nous avons implémenté un protocole de consensus nommé DISMU. De par sa conception,DISMU est optimal en termes de latence et de débit, car il peut réduire au minimumle nombre de paquets échangés sur le réseau pour parvenir à un consensus.Enfin, en utilisant ces deux technologies, nous remarquons que les futures générationsde matériel pourraient nécessiter une nouvelle interface pour les mémoires detoutes sortes, afin de faciliter l'interopérabilité dans des systèmes qui ont tendanceà devenir de plus en plus hétérogènes et complexes<br>Modern computers are built around two main parts: their Central Processing Unit (CPU), and their volatile main memory, or Random Access Memory (RAM). The basis of this architecture takes its roots in the 1970's first computers. Since, this principle has been constantly upgraded to provide more functionnality and performance.In this thesis, we study two memory paradigms that drastically change the way we can interact with memory in modern systems: non-volatile memory and remote memory access. We implement software tools that leverage them in order to make them compatible and exploit their performance with concrete applications. We also analyze the impact of the technologies underlying these new memory medium, and the perspectives of their evolution in the coming years.For non-volatile memory, as the main memory performance is key to unlock the full potential of a CPU, this feature has historically been abandoned on the race for performance. Even if the first computers were designed with non-volatile forms of memory, computer architects started to use volatile RAM for its incomparable performance compared to durable storage, and never questioned this decision for years. However, in 2019 Intel released a new component called Optane DC Persistent Memory (DCPMM), a device that made possible the use of Non-Volatile Main Memory (NVMM). That product, by its capabilities, provides a new way of thinking about data persistence. Yet, it also challenges the hardware architecture used in our current machines and the way we program them.With this new form of memory we implemented NVCACHE, a cache designed for non-volatile memory that helps boosting the interactions with slower persistent storage medias, such as solid state drive (SSD). We find NVCACHE to be quite performant for workloads that require a high granularity of persistence guarantees, while being as easy to use as the traditional POSIX interface. Compared to file systems designed for NVMM, NVCACHE can reach similar or higher throughput when the non-volatile memory is used. In addition, NVCACHE allows the code to exploit NVMM performance while not being limited by the amount of NVMM installed in the machine.Another major change of in the computer landscape has been the popularity of distributed systems. As individual machines tend to reach performance limitations, using several machines and sharing workloads became the new way to build powerful computers. While this mode of computation allows the software to scale up the number of CPUs used simultaneously, it requires fast interconnection between the computing nodes. For that reason, several communication protocols implemented Remote Direct Memory Access (RDMA), a way to read or write directly into a distant machine's memory. RDMA provides low latencies and high throughput, bypassing many steps of the traditional network stack.However, RDMA remains limited in its native features. For instance, there is no advanced multicast equivalent for the most efficient RDMA functions. Thanks to a programmable switch (the Intel Tofino), we implemented a special mode for RDMA that allows a client to read or write in multiple servers at the same time, with no performance penalty. Our system called Byp4ss makes the switch participate in transfers, duplicating RDMA packets. On top of Byp4ss, we implement a consensus protocol named DISMU, which shows the typical use of Byp4ss features and its impact on performance. By design, DISMU is optimal in terms of latency and throughput, as it can reduce to the minimum the number of packets exchanged through the network to reach a consensus.Finally, by using these two technologies, we notice that future generations of hardware may require a new interface for memories of all kinds, in order to ease the interoperability in systems that tend to get more and more heterogeneous and complex
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Merali, Shamir. "Designing and implementing memory consistency models for shared-memory multiprocessors." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=23922.
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The most commonly assumed memory consistency model for shared-memory multiprocessors is Sequential Consistency (SC), which is a straightforward extension of the sequential programming model, and is therefore simple to reason with. However, SC places severe restrictions on the use of high-performance hardware and compiler optimizations. In order to mitigate the performance limitations of SC, designers have proposed relaxed consistency models that retain the SC programming interface for a restricted class of programs, and at the same time allow more aggressive hardware implementations by relaxing restrictions on memory access ordering.<br>In cache-based systems, the management of the cache is an important issue in the implementation of a consistency model, since the presence of multiple copies of the same location in multiple caches requires that these copies be managed in a way that does not violate the requirements of the consistency model. Aggressive cache management schemes can exploit looser constraints on event ordering by reducing consistency-related cache-coherence traffic.<br>Location Consistency (LC), a consistency model first presented in (GS93), was designed expressly to minimize the constraints on event ordering, in an attempt to improve performance. At the same time, LC presents a formally defined interface that is easy to understand and reason with. In this thesis, we present sufficiency conditions for LC, propose a cache coherence protocol that implements the model, and present a preliminary cost and performance analysis of the protocol.
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Garley, Claire Louise. "The effect of verbal memory impairments on memory for narrative." Thesis, Royal Holloway, University of London, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.414062.
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Bellamy, Katarina Jane. "Cognitive neuroscience of false memory : the role of gist memory." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4471.
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This thesis explores the role of gist memory and gist representation in the formation of false recognition, specifically in the Deese, Roediger and McDermott Paradigm. We found that normal individuals displayed a range of susceptibility to false recognition and true recognition and this was related to their scores on both the Autism Spectrum Quotient and the Toronto-Alexithymia Scale. More ‘male-brained’ participants exhibited less susceptibility to false recognition but also less veridical recognition. The reverse was true for more ‘female-brained’ participants. The idea of false recognition and gist memory lying along a continuum was further emphasised by work on individuals with Autism Spectrum Disorder. We found they were less susceptible to false recognition but also produced less veridical recognition. We also found differences in performance between two groups of autism individuals who also differed in age. The results of further manipulations using both picture and word paradigms suggested that gist memory could be improved in younger individuals with autism. We also examined a patient group with Functional Memory Disorder using the DRM paradigm and a confabulation task and found them less able to produce true recognition in the DRM compared with a control group. Their memory impairments could not be attributed to depression since none were clinically depressed, so we suggested that they represent the tale end of impairment to gist memory. We also explored gist memory in a patient with dense anterograde amnesia who showed reduced true recognition and a tendency to reduced false recognition, but through manipulation of the stimuli using word and pictorial material she could perform like controls due to improved item-specific discrimination. A new face recognition paradigm was also tested in which she showed a tendency towards increased false recognition in comparison with controls. Finally, we suggest the use of the DRM paradigm as a test for memory malingering since we found participants could not replicate the performance of amnesia patients without a cost in their response latencies. This is discussed through the case study of GC a man suspected of exaggerating his memory symptoms.
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Threadgold, Emma. "The relationship between processing and memory in working memory development." Thesis, Lancaster University, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.656860.
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Working memory is the ability to simultaneously process and store information (Baddeley, 1986). Complex span tasks, such as reading span, are a widely used paradigm to investigate working memory recall (Daneman & Carpenter, 1980). This thesis presents six experiments that investigate processing and memory relationships in children and adults complex span performance. Experiments 1 to 3 found processing speed significantly influences children's recall in a reading, operation and listening; span task. Evidence is provided for a developmental shift in the importance of processing speed in reading span performance between aged 8- to 14-years-old. However, processing speed is shown to be less important for adults 11' retention in complex span tasks. Furthermore, profiles in the relationship between processing speed and memory are demonstrated to differ according to the type of complex span task, and the relationship between the content of processing and memory. The relationship between the content of processing and memory, influences both children's and adults recall in a complex span task. Memoranda items integrated to the processed element (for example retention of the final word of the processed sentence) are subject to enhanced recall over items independent to the processing. This is demonstrated to be superior in a lexical based span task (reading span) over a non-lexical based span task (operation span). However, mixed evidence is provided in Experiments 2 and 3 for enhanced recall under circumstances in which the memoranda items are semantically associated to the processing. Experiments 4, 5 and 6 investigate the role of pro active interference in complex span task performance. A build up and release of PI is demonstrated in an operation span task, highlighting that inhibition of interference is likely to be a further important factor in complex span task performance.
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Seong, Nak Hee. "A reliable, secure phase-change memory as a main memory." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50123.
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The main objective of this research is to provide an efficient and reliable method for using multi-level cell (MLC) phase-change memory (PCM) as a main memory. As DRAM scaling approaches the physical limit, alternative memory technologies are being explored for future computing systems. Among them, PCM is the most mature with announced commercial products for NOR flash replacement. Its fast access latency and scalability have led researchers to investigate PCM as a feasible candidate for DRAM replacement. Moreover, the multi-level potential of PCM cells can enhance the scalability by increasing the number of bits stored in a cell. However, the two major challenges for adopting MLC PCM are the limited write endurance cycle and the resistance drift issue. To alleviate the negative impact of the limited write endurance cycle, this thesis first introduces a secure wear-leveling scheme called Security Refresh. In the study, this thesis argues that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. Security Refresh can avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. In addition to the secure wear-leveling scheme, this thesis also proposes SAFER, a hardware-efficient multi-bit stuck-at-fault error recovery scheme which can function in conjunction with existing wear-leveling techniques. The limited write endurance leads to wear-out related permanent failures, and furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data; thereby reducing the hardware overhead for error recovery. Another approach that this thesis proposes to address the lower write endurance is a hybrid phase-change memory architecture that can dynamically classify, detect, and isolate frequent writes from accessing the phase-change memory. This proposed architecture employs a small SRAM-based Isolation Cache with a detection mechanism based on a multi-dimensional Bloom filter and a binary classifier. The techniques are orthogonal to and can be combined with other wear-out management schemes to obtain a synergistic result. Lastly, this thesis quantitatively studies the current art for MLC PCM in dealing with the resistance drift problem and shows that the previous techniques such as scrubbing or error correction schemes are incapable of providing sufficient level of reliability. Then, this thesis proposes tri-level-cell (3LC) PCM and demonstrates that 3LC PCM can be a viable solution to achieve the soft error rate of DRAM and the performance of single-level-cell PCM.
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Vadakke, Kunninmel Gokuldev. "Chemically Programmed Memory Card and PC Connected Memory Card Reader." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-18577.
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Inkjet-printed memory cards have been developed previously by re-searchers at Mid Sweden University but, these did possess some limita-tions, as each resistive memory cell required one physical contact and the resistances were designed to be electrically programmed.This work overcomes the above limitations by developing chemically programmed printed memory cards and a PC connected memory card reader. Printed memory cards are inexpensive and are developed by inkjet printing the nano-silver ink onto the photo paper substrate. A matrix readout method is used to increase the num-ber of memory cells and, by using a chemical solvent, the resistances were programmed to the desired resistance values and, for which, each resistance value represents data on the cards, called, write once read many (WORM) memories. The memory card reader was developed to access the data (resistance value) of the memory card and also to trans-mit the data to a LabVIEW graphical user interface for displaying the resistance values. By using multiple resistance steps, in which each step represents a different state, it is possible to create a number of possible selectable combinations which can be programmed at a later stage for developing applications.
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Linck, Marcelo Melo. "Increasing memory access efficiency through a two-level memory controller." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2018. http://tede2.pucrs.br/tede2/handle/tede/7941.
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Previous issue date: 2018-03-22<br>Acessos simult?neos gerados por m?ltiplos clientes para um ?nico dispositivo de mem?ria
em um Sistema-em-Chip (SoC) imp?e desafios que requerem aten??o extra devido ao gargalo gerado
na performance. Considerando estes clientes como processadores, este problema torna-se mais
evidente, pois a taxa de crescimento de velocidade para processadores excede a de dispositivos de
mem?ria, criando uma lacuna de desempenho. Neste cen?rio, estrat?gias de controle de mem?ria
s?o necess?rias para aumentar o desempenho do sistema. Estudos provam que a comunica??o com a
mem?ria ? a maior causa de atrasos durante a execu??o de programas em processadores. Portanto, a
maior contribui??o deste trabalho ? a implementa??o de uma arquitetura de controlador de mem?ria
composta por dois n?veis: prioridade e mem?ria. O n?vel de prioridade ? respons?vel por interagir
com os clientes e escalonar requisi??es de mem?ria de acordo com um algoritmo de prioridade fixa.
O n?vel de mem?ria ? respons?vel por reordenar as requisi??es e garantir o isolamento de acesso ?
mem?ria para clientes de alta prioridade. O principal objetivo deste trabalho ? apresentar um modelo
que reduza as lat?ncias de acesso ? mem?ria para clientes de alta prioridade em um sistema altamente
escal?vel. Os experimentos neste trabalho foram realizados atrav?s de uma simula??o comportamental
da estrutura proposta utilizando um programa de simula??o. A an?lise dos resultados ? dividida em
quatro partes: an?lise de lat?ncia, an?lise de row-hit, an?lise de tempo de execu??o e an?lise de
escalabilidade.<br>Simultaneous accesses generated by memory clients in a System-on-Chip (SoC) to a single memory device impose challenges that require extra attention due to the performance bottleneck created. When considering these clients as processors, this issue becomes more evident, because the growth rate in speed for processors exceeds the same rate for memory devices, creating a performance gap. In this scenario, memory-controlling strategies are necessary to improve system performances. Studies have proven that the main cause of processor execution lagging is the memory communication. Therefore, the main contribution of this work is the implementation of a memory-controlling architecture composed of two levels: priority and memory. The priority level is responsible for interfacing with clients and scheduling memory requests according to a fixed-priority algorithm. The memory level is responsible for reordering requests and guaranteeing memory access isolation to high-priority clients. The main objective of this work is to provide latency reductions to high-priority clients in a scalable system. Experiments in this work have been conducted considering the behavioral simulation of the proposed architecture through a software simulator. The evaluation of the proposed work is divided into four parts: latency evaluation, row-hit evaluation, runtime evaluation and scalability evaluation.
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Linck, Marcelo Melo. "Increasing memory access efficiency through a two-level memory controller." Pontifícia Universidade Católica do Rio Grande do Sul, 2017. http://hdl.handle.net/10923/11744.
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Previous issue date: 2017<br>Simultaneous accesses generated by memory clients in a System-on-Chip (SoC) to a single memory device impose challenges that require extra attention due to the performance bottleneck created. When considering these clients as processors, this issue becomes more evident, because the growth rate in speed for processors exceeds the same rate for memory devices, creating a performance gap. In this scenario, memory-controlling strategies are necessary to improve system performances. Studies have proven that the main cause of processor execution lagging is the memory communication. Therefore, the main contribution of this work is the implementation of a memory-controlling architecture composed of two levels: priority and memory. The priority level is responsible for interfacing with clients and scheduling memory requests according to a fixed-priority algorithm. The memory level is responsible for reordering requests and guaranteeing memory access isolation to high-priority clients. The main objective of this work is to provide latency reductions to high-priority clients in a scalable system. Experiments in this work have been conducted considering the behavioral simulation of the proposed architecture through a software simulator. The evaluation of the proposed work is divided into four parts: latency evaluation, row-hit evaluation, runtime evaluation and scalability evaluation.<br>Acessos simultâneos gerados por múltiplos clientes para um único dispositivo de memória em um Sistema-em-Chip (SoC) impõe desafios que requerem atenção extra devido ao gargalo gerado na performance. Considerando estes clientes como processadores, este problema torna-se mais evidente, pois a taxa de crescimento de velocidade para processadores excede a de dispositivos de memória, criando uma lacuna de desempenho. Neste cenário, estratégias de controle de memória são necessárias para aumentar o desempenho do sistema. Estudos provam que a comunicação com a memória é a maior causa de atrasos durante a execução de programas em processadores. Portanto, a maior contribuição deste trabalho é a implementação de uma arquitetura de controlador de memória composta por dois níveis: prioridade e memória. O nível de prioridade é responsável por interagir com os clientes e escalonar requisições de memória de acordo com um algoritmo de prioridade fixa. O nível de memória é responsável por reordenar as requisições e garantir o isolamento de acesso à memória para clientes de alta prioridade. O principal objetivo deste trabalho é apresentar um modelo que reduza as latências de acesso à memória para clientes de alta prioridade em um sistema altamente escalável. Os experimentos neste trabalho foram realizados através de uma simulação comportamental da estrutura proposta utilizando um programa de simulação. A análise dos resultados é dividida em quatro partes: análise de latência, análise de row-hit, análise de tempo de execução e análise de escalabilidade.
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Brown, Judith Ashley. "Cultural memory in Crimea : history, memory and place in Sevastopol." Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.708062.
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Mcgahan, Jennifer Anne. "Exploring memory and memory rehabilitation in paediatric brain tumour survivors." Thesis, University of Manchester, 2014. https://www.research.manchester.ac.uk/portal/en/theses/exploring-memory-and-memory-rehabilitation-in-paediatric-brain-tumour-survivors(194abbcb-6a1a-47aa-bbe7-8cca023f659f).html.
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This collection of studies begins by exploring the development of recognition memory in a group of healthy children and adolescents using experimental memory tests developed as part of this thesis. Various versions of these recognition memory tests were trialled in order to establish age appropriate tests for children aged 6-14 years. In keeping with previous literature in this area, these tests showed relatively stable familiarity memory throughout childhood compared to a steep developmental course for recollection memory. Paediatric brain tumour survivors are known to suffer from significant memory deficits following treatment. However, a clear description of this clinical group’s deficits, in terms of recognition and recall (and therefore also familiarity and recollection), has not previously been established. Using standard clinical memory assessments, the current body of work contributes to this area by characterising this population’s memory deficits as primarily recall-based, particularly when recalling information presented as prose. A sex difference is also noted; with female brain tumour survivors being significantly more impaired than their age-matched male counterparts. This finding is discussed with respect to the differing neural development of males and females. The experimental memory tests developed with normal children were also administered to a group of paediatric brain tumour patients. They were found to have a varied pattern of performance, including auditory recognition impairments but intact visual recognition, even when the test format incorporated similar foils. Associative memory tests revealed impairments in recollection-based recognition; this effect was dependant on the type of information being associated and the length of the encoding-test delay. A learning intervention was developed (and trialled with healthy children), using a method known as the ‘testing effect’, in an attempt to enhance recall of prose at long delays in a group of paediatric brain tumour survivors. Structured repeated retrieval was compared to repeated study for prose passages. This was found, with some patients, to be a successful method of improving recall after a delay of one week. Taken together, the work described in this thesis provides further understanding of recognition memory development in healthy children, novel insights into the residual memory function of paediatric brain tumour survivors and an exciting foundation on which to build a rehabilitation programme for this vulnerable group.
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Oliveira, Junior Geraldo Francisco de. "A generic processing in memory cycle accurate simulator under hybrid memory cube architecture." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/170019.
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PIM - uma técnica onde elementos computacionais são adicionados perto, ou idealmente, dentro de dispositivos de memória - foi uma das tentativas criadas durante os anos 1990 visando mitigar o notório memory wall problem. Hoje em dia, com o amadurecimento do processo de integração 3D, um novo horizonte para novas arquiteturas PIM pode ser explorado. Para investigar este novo cenário, pesquisadores dependem de simuladores em software para navegar pelo espaço de exploração de projeto. Hoje, a maioria dos trabalhos que focam em PIM, implementam simuladores locais para realizar seus experimentos. Porém, esta metodologia pode reduzir a produtividade e reprodutibilidade. Neste trabalho, nós mostramos o desenvolvimento de um simulador de PIM preciso, modular e parametrizável. Nosso simulador, chamado CLAPPS, visa a arquitetura de memória HMC, uma memória 3D popular, que é amplamente utilizada em aceleradores PIM do estado da arte. Nós desenvolvemos nosso mecanismo utilizando a linguagem de programação SystemC, o que permite uma simulação paralela nativamente. A principal contribuição do nosso trabalho se baseia em desenvolver a interface amigável que permite a fácil exploração de arquiteturas PIM. Para avaliar o nosso sistema, nós implementamos um modulo de PIM que pode executar operações vetoriais com diferente tamanhos de operandos utilizando o proposto conjunto de ferramentas.<br>PIM - a technique which computational elements are added close, or ideally, inside memory devices - was one of the attempts created during the 1990s to try to mitigate the memory wall problem. Nowadays, with the maturation of 3D integration technologies, a new landscape for novel PIM architectures can be investigated. To exploit this new scenario, researchers rely on software simulators to navigate throughout the design evaluation space. Today, most of the works targeting PIM implement in-house simulators to perform their experiments. However, this methodology might hurt overall productivity, while it might also preclude replicability. In this work, we showed the development of a precise, modular and parametrized PIM simulation environment. Our simulator, named CLAPPS, targets the HMC architecture, a popular 3D-stacked memory widely employed in state-of-the-art PIM accelerators. We have designed our mechanism using the SystemC programming language, which allows native parallel simulation. The primary contribution of our work lies in developing a user-friendly interface to allow easy PIM architectures exploitation. To evaluate our system, we have implemented a PIM module that can perform vector operations with different operand sizes using the proposed set of tools.
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Larsson, Johan. "Modelling a memory." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1028.
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<p>The purpose of this master thesis is to describe the work behind the building of a scalable model of a memory designed at Zarlink Semiconductor AB. This model is to be part of a memory generator and used to extract timing parameters for all available memory sizes instead of simulating the layout, as layout simulation takes too much time. </p><p>The report starts with the basic theory of passive circuit elements that has to be considered in a model and what effect these elements have on functionality and robustness of the design. There’s also a short chapter on how to layout for optimisation towards high speed, minimal area or low power consumption. </p><p>After that, the work behind three different models of a memory is described. The models are a skeletal model, a mixed-mode model and a digital model. The skeletal model was the only one that could be finished and this model is then evaluated and compared to a simulation made on the original layout of the memory. </p><p>Included in the description of the mixed-mode and digital models are a description of how you characterise cells and how you include power information in digital simulation. </p><p>At the end there’s a short chapter on the future of modelmaking.</p>
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Sterne, Philip Jonathan. "Distributed associative memory." Thesis, University of Cambridge, 2011. https://www.repository.cam.ac.uk/handle/1810/265517.
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This dissertation modifies error-correcting codes and Bloom filters to create high-capacity associative memories. These associative memories use principled statistical inference and are distributed as no single component contains enough information to complete the task by itself, yet the components can collectively solve the task by passing information to each other. These associative memories are also robust to hardware failure as their distributed nature ensures there is no single point of failure. This dissertation starts by simplifying a Bloom filter so that it tolerates hardware failure (albeit with reduced performance). An efficient associative memory is created by performing inference over the set of items stored in the Bloom filter. This architecture suggests a modification which forgets old patterns stored in the associative memory (known as a palimpsest memory). It is shown that overwriting old patterns in an independent manner reduces performance, but is still comparable to the well-known Hopfield network. The lost performance can be regained using integer storage which allows the superposition of the pattern representation, or ensuring bits are not overwritten independently using concepts from errorcorrecting codes. The final task performs recall in continuous time using components which are more similar to neurons than used in the rest of the dissertation. The resulting memory has the exciting ability to recall many patterns simultaneously. Statistical inference ensures gradual degradation of the performance as an associative memory is overloaded. Since many definitions of associative memory capacity rely on the existence of catastrophic failure a new definition of capacity is provided. In spite of some biologically unrealistic attributes, this work is relevant to the understanding of the brain as it provides high performance solutions to the associative memory task which is known to be relevant to the brain.