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Tesis sobre el tema "Memory transistors"

Autor: Grafiati
Publicado: 25 de mayo de 2024

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1

Masani, Deekshitha. "Analysis of radiation induced errors in transistors in memory elements". OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2791.

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From the first integrated circuit which has 16-transistor chip built by Heiman and Steven Hofstein in 1962 to the latest 39.54 billion MOSFET’s using 7nm FinFET technology as of 2019 the scaling of transistors is still challenging. The scaling always needs to satisfy the minimal power constraint, minimal area constraint and high speed as possible. As of 2020, the worlds smallest transistor is 1nm long build by a team at Lawrence Berkeley National Laboratory. Looking at the latest trends of 14nm, 7nm technologies present where a single die holds more than a billion transistors on it. Thinking of it, it is more challenging for dyeing a 1nm technology. The scaling keeps going on and if silicon does not satisfy the requirement, they switch to carbon nanotubes and molybdenum disulfide or some newer materials. The transistor sizing is reducing but the pressure of radiation effects on transistor is in quench of more and more efficient circuits to tolerate errors. The radiation errors which are of higher voltage are capable of hitting a node and flipping its value. However, it is not possible to have a perfect material to satisfy no error requirement for a circuit. But it is possible to maintain the value before causing the error and retain the value even after occurrence of the error. In the advanced technologies due to transistor scaling multiple simultaneous radiation induced errors are the issue. Different latch designs are proposed to fix this problem. Using the CMOS 90nm technology different latch designs are proposed which will recover the value even after the error strikes the latch. Initially the errors are generally Single event upsets (SEUs) which when the high radiation particle strikes only one transistor. Since the era of scaling, the multiple simultaneous radiation errors are common. The general errors are Double Node Upset (DNU) which occurs when the high radiation particle strikes the two transistors due to replacing one transistor by more than one after scaling. Existing designs of SEUs and DNUs accurately determine the error rates in a circuit. However, with reference to the dissertation of Dr. Adam Watkins, proposed HRDNUT latch in the paper “Analysis and mitigation of multiple radiation induced errors in modern circuits”, the circuits can retain its error value in 2.13ps. Two circuits are introduced to increase the speed in retaining the error value after the high energy particle strikes the node. Upon the evaluation of the past designs how the error is introduced inside the circuit is not clear. Some designs used a pass gate to actually introduce the error logic value but not in terms of voltage. The current thesis introduces a method to introduce error with reduced power and delay overhead compared to the previous circuits. Introducing the error in the circuits from the literature survey and comparing the delay and power with and without introducing the error is shown. Introducing the errors in the two new circuits are also shown and compared with when no errors are injected.
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2

Fakher, Sundes Juma. "Advanced study of pentacene-based organic memory structures". Thesis, Bangor University, 2014. https://research.bangor.ac.uk/portal/en/theses/advanced-study-of-pentacenebased-organic-memory-structures(5319a571-2c4c-4f90-a26c-fa5e7da82cfb).html.

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A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.
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3

Almeida, Luciano Mendes. "Estudo de célula de memória dinâmica de apenas um transistor SOI de óxido enterrado ultrafino". Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18072013-144946/.

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Neste trabalho foi analisado o comportamento de um transistor UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo n, operando como uma célula de memória 1T-FBRAM (single transistor floating body random access memory). A memória em questão trata-se de uma evolução das memórias 1T1C-DRAM convencionais formada, porém, de apenas um transistor, sendo o próprio transistor o responsável pelo armazenamento da informação por meio do efeito de corpo flutuante. Assim, foram realizadas simulações numéricas bidimensionais, obtendo-se curvas dinâmicas e, a partir destas, foi possível extrair e analisar alguns dos principais parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Foram estudadas as polarizações da célula de memória. Dentre as possíveis maneiras de programação do dado 1 desta tecnologia foram abordadas neste trabalho a programação pelos métodos GIDL (Gate Induced Drain Leakage) e BJT (Bipolar Junction Transistor). Pelo método de escrita por GIDL foi possível operar a célula de memória em alta velocidade sem dissipar potência expressiva. Mostrou-se que esse método é bastante promissor para a tecnologia low-power high-speed. E ainda, obteve-se maior estabilidade na operação de leitura quando esta é polarizada no ponto ZTC (Zero Temperature-Coefficient) devido ao nível de corrente do dado 0 ficar estável mesmo com a variação da temperatura. Pelo método de escrita por BJT, estudou-se a influência das espessuras do filme de silício e também do óxido enterrado, notou-se uma forte dependência da tensão mínima de dreno para a programação do dado 1 em função destas espessuras e também em função da temperatura. Conforme a espessura do filme de silício torna-se mais fina, a tensão de disparo aplicada ao dreno aumenta devido ao maior acoplamento. Porém, observou-se que o nível da tensão de disparo do dreno pode ser modulada através da tensão aplicada ao substrato, tornando possível operar a célula em uma tensão de disparo menor aumentando a vida útil do dispositivo. Quanto à temperatura, com o seu aumento observou-se que a tensão mínima de dreno necessária para disparar a escrita do dado 1 diminuiu favorecendo a programação da célula. Porém o tempo de retenção é prejudicado (torna-se menor) por causa do aumento da corrente de fuga na junção PN. Na análise sobre o impacto que a primeira e a segunda porta causam na margem de sensibilidade de corrente e no tempo de retenção, verificou-se que dependendo da tensão aplicada à porta durante a condição de armazenamento do dado, o tempo de retenção pode ser limitado ou pela geração ou pela recombinação dos portadores (lacunas). Notou-se que há um compromisso entre a obtenção da melhor margem de sensibilidade de corrente e o melhor tempo de retenção. Como o tempo retenção é um parâmetro mais crítico, mais atenção foi dada para a otimização deste. Concluiu-se nesta análise que a melhor polarização para reter o dado por mais tempo é a primeira interface estar em modo acumulação e a segunda em modo depleção. No estudo da polarização de dreno durante a operação de leitura, observou-se que quando aplicado alta tensão de dreno é obtido alta margem de sensibilidade, porém ao mesmo tempo esta polarização prejudica o dado 0 devido ao alto nível de geração de lacunas induzidas pela ionização por impacto, o qual diminui o tempo de retenção e destrói o dado 0 quando operações de múltiplas leituras são realizadas. Já para baixo nível de tensão de dreno durante a leitura notou-se que é possível realizar múltiplas operações de leitura sem perder o dado armazenado e também maior tempo de retenção foi obtido.
In this study was analyzed the behavior of one transistor called UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) working as a 1T-FBRAM (Single Transistor Floating Body Random Access Memory). This memory device is an evolution from conventional memories 1T1C-DRAM, however formed by only one transistor, the device itself is responsible for the storage of the information through the floating body effect. Thus two dimensional simulations were performed, where were obtained dynamic curves, and from these curves it was possible to extract and analyze some of the main parameters, such as, trigger drain voltage, sense margin current, read window, and the retention time, beyond the mechanisms in each state of memory (write, read and hold). Among the possible ways to program the data 1 in this technology were used the methods GIDL (Gate Induced Drain Leakage) and BJT (Bipolar Junction Transistor). By the GIDL method it was possible to operate the memory cell at high speed without spending significant power, showing that this method is very promising for low-power high-speed. Furthermore, greater stability was obtained in read operation when it is biased at point ZTC (zero-Temperature Coefficient) due to the current level of datum \'0\' remain stable even with temperature variation. By the BJT method, it was studied the influence of the silicon film thickness and the buried oxide thickness, and it was noted a strong dependence on minimum drain voltage for programming the data \'1\' as a function of both thicknesses. As the thickness of the silicon film becomes thinner, the trigger drain voltage increases due to stronger coupling. However, it was observed that the level of the trigger drain voltage can be modulated by the substrate bias in this way it is possible to operate the cell with lower voltage avoiding the damage and increasing the lifetime of the device. About the temperature, with its increase it was observed that the minimum drain voltage required to trigger the writing datum \'1\' decreased favoring the programming the cell. However the retention time is harmed (becomes smaller) due to the increment of leakage current in the PN junction. Analyzing the impact of the first and second gate on sense margin current and retention time, it was verified that depending on the voltage applied to the gate during the hold condition, the retention time may be limited by the generation or recombination of the carriers (holes). It was noted that there is a compromise between obtaining the best sense margin current and the best retention time. Since the retention is the most critical parameter, more attention should be given in order to obtain the optimization of this latter. It is concluded in this analysis that the best bias to retain the datum for longer time is the first interface being in accumulation mode and the second in depletion mode. In the study of biasing the drain during the read operation, it has been observed that the use of high drain voltage provides high sense margin, but at the same time, this polarization affect the data \'0\' due to high level of holes generation induced by impact ionization, which shortens the retention time and destroys the data \'0\' in multiple read operations. However, for low drain voltage during read operations it was possible to perform multiple read operations without losing the stored data and also higher retention time was obtained.
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4

Sasaki, Kátia Regina Akemi. "Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI". Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26072013-173443/.

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Neste trabalho foi analisado o comportamento de um transistor UTBOX FD SOI MOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo N, em sua aplicação como uma célula de memória 1T-DRAM, dando ênfase no estudo das polarizações e propostas de melhorias de desempenho para viabilizar sua aplicação como uma célula de memória. Dessa forma, foram analisados os efeitos das diferentes polarizações (de porta, de dreno e de substrato), bem como a influência da concentração de uma região de extensão de fonte e dreno menos dopada (LDD Lightly Doped Drain), nos principais parâmetros da referida memória. Assim, foram analisados alguns parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Por fim, foram propostas algumas melhorias de desempenho para o tempo de retenção. Foi observado que o aumento da temperatura facilita a escrita na memória diminuindo a mínima tensão no dreno (até 72% para temperatura de 25 a 300°C, ficando limitada a 0,8V) e o tempo necessários para a escrita (até 95%), porém reduz a margem de sensibilidade (até 90%) e o tempo de retenção (até 2 ordens de grandeza). Verificou-se também que, apesar da menor espessura do filme de silício e do óxido enterrado aumentar a tensão no dreno necessária para ativar o efeito BJT (efeito bipolar parasitário), um potencial positivo no substrato pode reduzir este requisito (61% para tensão de substrato variando de 0 V até 1,5 V). Além disso, foi visto que pode haver uma geração ou uma recombinação de portadores, dependendo da tensão na porta durante o repouso, degradando o bit \'0\' ou \'1\'. Já a otimização da polarização de substrato demonstrou ser limitada pelo compromisso de ser alta o suficiente para ativar o efeito de corpo flutuante durante a escrita, sem prejudicar a leitura do \'0\'. Os resultados também demonstraram que a margem de sensibilidade é menos dependente da tensão do substrato que o tempo de retenção, levando a este último parâmetro ser considerado mais crítico. Com relação à leitura, maiores tensões no dreno resultaram na presença do efeito BJT também neste estado, aumentando a margem de sensibilidade (60%) e diminuindo o tempo de retenção (66%) e o número de leituras possíveis sem atualização do dado (de mais de 30 para 22 leituras). No tópico da concentração das extensões de fonte e dreno, os dispositivos sem extensão de fonte e dreno apresentaram uma taxa de geração de lacunas menor (aproximadamente 12 ordens de grandeza), levando a um tempo de retenção muito maior (aproximadamente 3 ordens de grandeza) quando comparado ao dispositivo referência. Em seu estudo no escalamento, verificou-se uma diminuição no tempo de retenção para canais mais curtos (quase 2 ordens de grandeza), demonstrando ser um fator limitante para as futuras gerações das memórias 1T-DRAM. Apesar disso, quando comparados com os dispositivos convencionais com extensão de fonte e dreno (com extensão), seu tempo de retenção aumentou (quase 1 ordem de grandeza), permitindo a utilização de menores comprimentos de canal (30nm contra 50nm do dispositivo com extensão) e polarizações de substrato menores. Outra proposta de melhoria no tempo de retenção apresentada foi a utilização da polarização de substrato pulsada apenas durante a escrita do nível \'1\', o que resultou no aumento do tempo de retenção em 17%. Finalmente, estudou-se também a variação da banda proibida motivado pela utilização de novos materiais para o filme semicondutor. Observou-se que o aumento da banda proibida aumentou o tempo de retenção em até 5 ordens de grandeza, possibilitando retenções mais próximas das DRAMs convencionais atuais.
In this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor), as a 1T-DRAM (Single Transistor Dynamic Random Access Memory) cell, focusing on the best biases and other proposals for enabling the 1T-DRAM applications. Therefore, it was analyzed the effects of different biases (gate, drain and substrate), as well as the influence of the concentration of a less doped source/drain extension region on the main parameters of this kind of memory. Thus, it was analyzed some of the main memory parameters such as the trigger drain voltage, the sense margin, the read window and the retention time, as well as the mechanisms operating in each state of the memory (writing, reading and holding). Finally, it were proposed some performance enhancements for the retention time of this kind of memory. It was observed that the increase in temperature facilitates the memory write decreasing the minimum drain bias and time required for writing, but reduces the sense margin. It was also verified that, despite the thinner silicon film and buried oxide increase the drain voltage required to activate the BJT effect (parasitic bipolar effect), a positive potential on the substrate may reduce this requirement (61% for back gate bias varying from 0 to 1,5V), being an alternative for solving the problem and allowing the use of smaller devices as a memory cell. Furthermore, it was seen that there can be a carriers generation or recombination, depending on the gate voltage during the holding state, degrading the bit \'0\' or \'1\'. Moreover, the optimization of substrate bias proved to be limited by enabling the writing state, without degrading the reading of \'0\'. The results also demonstrated the sense margin is less dependent on the substrate voltage than the retention time, therefore, the retention time was considered as a more critical parameter. With respect to the reading state, there was the presence of BJT effect also in this state, increasing the margin of sensitivity (60%) and reducing the retention time (66%) and the number of possible readings without updating the data (over 30 for 22 readings) in cases of higher drain bias. On the topic of the concentration of the source and drain extensions, the devices with source and drain extensions presented a generation rate lower (about 12 orders of magnitude), resulting in a retention time far longer than the reference one (about 3 orders of magnitude). About its downscaling, the retention time decreased for shorter channel lengths (almost 2 orders of magnitude), which is a limiting factor for 1T-DRAM future generations. Nevertheless, when it was compared to the conventional devices with source and drain extensions, theirs retention time increased (almost 1 order of magnitude), allowing the use of shorter channel lengths (30nm against 50nm of reference device) and lower back gate biases. Another proposal presented to improve the retention time was the pulsed back gate only during the writing \'1\' state, which resulted in an increase on the retention time by 17%. Finally, we also studied the band gap influence motivated by the use of new materials for the semiconductor film. It was observed that higher band gaps increase the retention time by up to 5 orders of magnitude, allowing a retention time closer to the current conventional DRAMs.
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5

Fullem, Travis Z. "Radiation detection using single event upsets in memory chips". Diss., Online access via UMI:, 2006.

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6

Kirschner, Johannes [Verfasser] y Marcus [Gutachter] Halik. "Block Copolymer Hybrid Dielectrics in Organic Memory Transistors / Johannes Kirschner ; Gutachter: Marcus Halik". Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2017. http://d-nb.info/1152079026/34.

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7

CASULA, SILVIA. "Non-volatile organic memory devices: from design to applications". Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266601.

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The research activity described in the attached dissertation focused on the development, fabrication and characterization of new non-volatile memory elements based on organic technology. During the last few decades, organic materials based devices have attracted considerable interest due to their great potential for future electronic systems. Low fabrication costs, high mechanical flexibility and versatility of the chemical structure, good scalability and easy processing are the unique advantages of organic electronics. As memory devices are essential elements of any kind of electronic system, the development of organic memory devices is fundamental in order to extend the application of organic materials to different electronic circuits. Research on organic electronic memories is currently at a rapid growth stage, since it is recognized that they may be an alternative or supplementary to the conventional memory technologies. Despite considerable progress in the advancement of novel memory technologies in recent years, some challenging tasks still need to be resolved. The Ph.D. research activity of this thesis is related to the still -opened challenges in the organic memories technologies. In particular, it focused mainly on the study, development, fabrication and characterization of new non-volatile organic memory elements based on resistive switching. The activity has been carried out in the frame of the European project “HYbrid organic/inorganic Memory Elements for integration of electronic and photonic Circuitry” (HYMEC), which involved the University of Cagliari during the last three years. The project goal was to realize new hybrid inorganic/organic resistive memory devices with functionality far beyond the state of the art. A complementary activity on transistor-based organic memory devices has been also carried out and described in this thesis. As regards resistive memory devices, the research activity included design, fabrication and testing of a novel non-volatile memory device based on the combination of an air-stable organic semiconductor and metal nanoparticles. This topic required the development of technology and procedures for easy and reliable production of devices as well as the definition of measurement protocols. The proposed structure was thoroughly characterized by morphological techniques, which allowed to interpret the resistive switching mechanisms in terms of formation and rupture of metallic filaments inside the organic layer assisted by the metal NPs. The obtained performances are the best reported so far in literature, and, to our knowledge, the statistics analysis is the largest ever reported for organic-based resistive memories. The developed technology was then successfully applied on flexible plastic substrates. The definition of technological processes for the reliable fabrication of high performance printed organic memory devices was also carried out: this work clearly demonstrates the real possibility of fabricating high performance printed memory elements. A significant effort was also devoted to the development of basic memory/sensor systems entirely fabricated on plastic substrates. The suitability of organic non-volatile memory devices for the detection and the storage of external parameters was demonstrated. The results definitely demonstrated the feasibility of the proposed technology for the fabrication of systems including organic memories for their final application in different industrial processes, including e-textile and smart packaging. As regards transistor memory devices, highly flexible Organic Field-Effect Transistor (OFET)-based memory elements with excellent mechanical stability and high retention time were developed. As main innovation with respect to the state of the art, low voltage operation of the OFET-based memory was investigated. Such an activity was also related to the development of reliable measurement procedures
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8

Marron, Dominique. "Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche". Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.

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Afin d'accroitre la complexite des composants electroniques, leur architecture utilise des elements redondants. On pallie ainsi les problemes de rendements. Cette these traite d'un element de reconfiguration, le transistor a grille flottante, et de sa programmation par un faisceau d'electrons. Les conditions de programmation, la tenue dans le temps de la charge deposee ainsi que les problemes pratiques rencontres sont etudies. Ce transistor est ensuite utilise dans la conception d'une memoire sram de 4. 5 mbit reconfigurable integree sur une tranche d=100. Les contraintes pratiques et l'architecture sont exposees de meme que la partie realisation et test. Cette etude est en fait une etude de faisabilite pour des circuits de type wsi industriels
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9

Couto, Andre Luis do. "Caracterização de memorias analogicas implementadas com transistores MOS floating gate". [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.

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Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005
Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área
Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Cheong, Kuan Yew y n/a. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material". Griffith University. School of Microelectronic Engineering, 2004. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050115.101233.

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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.
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11

Cheong, Kuan Yew. "Silicon Carbide as the Nonvolatile-Dynamic-Memory Material". Thesis, Griffith University, 2004. http://hdl.handle.net/10072/367177.

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This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
Faculty of Engineering and Information Technology
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12

Bosch, Daphnée. "Simulation, fabrication et caractérisation électrique de transistors MOS avancés pour une intégration 3D monolithique". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT077.

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De nos jours, l’industrie microélectronique doit maitriser un véritable « déluge de données » et une demande toujours en croissance de fonctionnalités ajoutées pour les nouveaux secteurs de marchés tels que la 5G, l’internet des objets, l’intelligence artificielle… Par ailleurs, l’énergie et sa gestion est un enjeu majeur au sein des architectures Von-Neumann traditionnelles. Dans ce cadre, ce travail de thèse explore l’intégration 3D monolithique ainsi que des dispositifs pour le calcul dans la mémoire. Premièrement, l’intégration 3D monolithique n’est pas perçue uniquement comme une alternative à la loi de Moore mais permet de diversifier les circuits. Les avantages de cette intégration sont analysés en détails et en particulier, une aide à la stabilité des mémoires SRAM (Static Random Access Memory) est proposée. Cette aide améliore significativement la stabilité ainsi que les performances des SRAM de l’étage supérieur, sans dégrader l’empreinte silicium. Secondement, des transistors sans jonctions (junctionless), compatibles avec une intégration 3D séquentielle sont étudiés. Les dispositifs sont simulés, fabriqués et caractérisés électriquement pour des applications digitales et analogiques. En particulier, l’impact du dopage canal sur la variabilité est analysée. Egalement des briques à basse température (<500°C) sont développées. Troisièmement, une structure 3D innovante combinant des transistors sans jonctions empilées et des mémoires résistives (RRAM) est étudiée. Cette technologie permet de faire des opérations Booléennes au sein de la mémoire en utilisant l’approche Scouting logique
Nowadays, Microelectronics industry must handle a real “data deluge” and a growing demand of added functionalities due to the new market sector of Internet Of Things, 5G but also Artificial Intelligence... At the same time, energy becomes a major issue and new computation paradigms emerge to break the traditional Von-Neumann architecture. In this context, this PhD manuscript explores both 3D monolithic integration and nano-electronic devices for In-Memory Computing. First, 3D monolithic integration is not seen only as an alternative to Moore’s law historic scaling but also to leverage circuit diversification. The advantages of this integration are analysed in depth and in particular an original top-tier Static Random Access Memories (SRAM) assist is proposed, improving significantly SRAM stability and performances without area overhead. In a second time, an original transistor architecture, called junctionless, suitable for 3D-monolithic integration is studied in detail. Devices are simulated, fabricated and electrically characterised for mixed digital/analog applications. In particular, the impact of channel doping density on mismatch is tackled. Also, low temperature (<500°C) junctionless bricks are developed and device optimization trade-off are discussed. In a third time, an innovative 3D structure combining state of the art devices: junctionless stacked Silicon nanowires and Resistive Random Access Memories (RRAM) is envisioned. This technology is proved to enable In-Memory Boolean operations through a so-called “scouting logic” approach
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13

Mikolajick, Thomas, Stefan Slesazeck, Min Hyuk Park y Uwe Schröder. "Ferroelectric hafnium oxide for ferroelectric random-access memories and ferroelectric field-effect transistors". Cambridge University Press, 2018. https://tud.qucosa.de/id/qucosa%3A70689.

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Ferroelectrics are promising for nonvolatile memories. However, the diffi culty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system.
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14

Khassanov, Artöm [Verfasser] y Marcus [Akademischer Betreuer] Halik. "Structural Characterization of Self-Assembled Monolayers and their Application in Organic Thin-Film Memory Transistors / Artöm Khassanov. Gutachter: Marcus Halik". Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2015. http://d-nb.info/1080362673/34.

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15

Yurchuk, Ekaterina. "Electrical Characterisation of Ferroelectric Field Effect Transistors based on Ferroelectric HfO2 Thin Films". Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-172000.

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Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.
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16

Tang, Andrew John. "Design and fabrication of polycrystalline material thin-film transistors for active matrix liquid-crystal display and static random access memory applications". Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36035.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Includes bibliographical references (leaves 81-82).
by Andrew John Tang.
M.S.
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17

Gong, Lin [Verfasser]. "Fabrication and Characterization of Organic Field-Efect Transistors with Modified Gate Dielectrics and Application for Organic Nonvolatile Memory Cells / Lin Gong". Hamburg : Helmut-Schmidt-Universität, Bibliothek, 2020. http://d-nb.info/1213048273/34.

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18

Conrad, Junior Eduardo. "Técnicas de redução de potência estática em memórias CMOS SRAM e aplicação da associação de MOSFETs tipo TST em nano-CMOS". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/49069.

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Em nossos dias a crescente busca por portabilidade e desempenho resulta em esforços focados na maximização da duração de bateria dos equipamentos em fabricação, ou seja, busca-se a conflitante solução de circuitos com baixo consumo e ao mesmo tempo com alto desempenho. Neste contexto usualmente na composição de equipamentos portáteis empregam-se SOC´s (Systems On Chip) o que barateia o custo de produção e integração destes circuitos. SOC´s são sistemas completos que executam uma determinada função integrados em uma pastilha de silício única, normalmente possuem memórias SRAM como componente do sistema, que são utilizadas como memórias de alta performance e baixa latência e/ou também como caches. O grande desafio de projeto em memórias SRAMS é a relação de desempenho versus potência consumida a ser otimizada. Basicamente por sua construção estes circuitos apresentam alto consumo de potência, dinâmica e estática, relacionada a primeira diretamente ao aumento de freqüência de operação. Um dos focos desta dissertação é explorar soluções para a redução de consumo de energia tanto dinâmica como estática, sendo a redução de consumo estático de células de memória em standby buscando desempenho, estabilidade e baixo consumo de energia. No desenvolvimento de técnicas para projeto de circuitos analógicos em tecnologias nanométricas, os TST´s (T-Shaped Transistors – Transistor tipo T) surgem como dispositivos com características potenciais para projeto analógico de baixa potência. TSTs / TATs (Trapezoidal Associations of Transistors – Associação Trapezoidal de transistores) são estruturas self-cascode que podem tornar-se uma boa escolha por apresentar redução do leakage, redução na área utilizada e com incremento na regularidade do layout e no casamento entre transistores, propriedade importantíssima para circuitos analógicos. Sendo este o segundo foco deste texto através do estudo e análise das medidas elétricas dos TSTs executadas para comprovação das características destes dispositivos. Também apresenta-se uma análise das possibilidades de utilização dos TSTs em projeto analógico para tecnologias nanométricas.
Nowadays the increasing needs for portability and performance has resulted in efforts to increase battery life, i. e., the conflicting demands for low power consumption and high performance circuits. In this context using SOC´s (System On Chip) in the development for portable equipments composition, an integration of an entire system for a given function in a single silicon die will provide less production costs and less integration costs. SOC´s normally include a SRAM memory as its building block and are used to achieve memories with low latency and short access time or (and) as caches. A performance versus power consumption analysis of SRAM memory building blocks shows a great challenge to be solved. The electrical design aspects of these blocks reveal high power consumption, dynamic and static, and the former is directly proportional to the operating frequency. The design space exploration for dynamic and leakage consumption reduction in these circuits is one of the focus of this work. The main contribution of this topic is the leakage reduction techniques based in performance, stability and low energy consumption for the memory cell stand-by mode. Among the electrical techniques developed for analog circuits at the 20-100 nanometer scale, the TST (T-Shaped Transistors) rises with potential characteristics for analog low power design. TST /TAT (Trapezoidal Associations of Transistors) are selfcascode structures and can be turning into a good alternative for leakage and area reduction. Another point is the increment in mismatch and layout regularity, all these characteristics being very important in analog designs. The TST electrical measurements study and analysis are developed to show the device properties. An analysis of the TST desired properties and extrapolation for nanometer technologies analog design are also presented.
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19

Liu, Qian. "Rational molecular design for multi-functional organic semiconducting materials". Thesis, Queensland University of Technology, 2021. https://eprints.qut.edu.au/208254/1/Qian_Liu_Thesis.pdf.

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This thesis demonstrates a comprehensive study of multifunctional applications of low-cost solution-processable organic semiconducting materials. It presents a series of rationally designed predominantly dye based innovative soft semiconductors with their generic optoelectronic properties. The performance of these materials’ application in various devices, including transistors, solar cells, memory devices and displays, are evaluated through world class collaboration to establish the structure-property relationship. In doing so, we not only developed several high-performance materials but also found that fused ring incorporation into the conjugated backbone is an effective strategy to construct multifunctional semiconductors towards flexible and printed electronics.
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20

Liu, Jheng-Sin. "Advanced Energy-Efficient Devices for Ultra-Low Voltage System: Materials-to-Circuits". Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/81858.

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The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications.
Ph. D.
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21

Najari, Montassar. "Modélisation compacte des transistors à nanotube de carbone à contacts Schottky et application aux circuits numériques". Phd thesis, Université Sciences et Technologies - Bordeaux I, 2010. http://tel.archives-ouvertes.fr/tel-00560346.

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Afin de permettre le développement de modèles manipulables par les concepteurs, il est nécessaire de pouvoir comprendre le fonctionnement des nanotubes, en particulier le transport des électrons et leurs propriétés électroniques. C'est dans ce contexte général que cette thèse s'intègre. Le travail a été mené sur quatre plans : • Développement de modèles permettant la description des phénomènes physiques importants au niveau des dispositifs, • Expertise sur le fonctionnement des nano-composants permettant de dégager les ordres de grandeurs pertinents pour les dispositifs, les contraintes, la pertinence de quelques procédés de fabrication (reproductibilité, taux de défauts), • Collection de caractéristiques mesurées et développement éventuel d'expériences spécifiques, • Expertise et conception des circuits innovatifs pour l'électronique numérique avec ces nano-composants. Mots clés — Modélisation compacte, transistor Schottky à nanotube de carbone, simulation circuit, cellule mémoire SRAM, effet tunnel, WKB.
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22

Hesse, Marjorie. "Développement de nouvelles architectures mémoires non-volatiles embarquées pour les plateformes technologiques avancées 40nm et 28nm". Thesis, Université Côte d'Azur (ComUE), 2019. http://www.theses.fr/2019AZUR4069.

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Les applications avancées à base de microcontrôleurs couvrent de multiples domaines. L’accroissement du champ d’application des microcontrôleurs s’accompagne d’une augmentation de la puissance consommée qui limite l’autonomie des systèmes nomades. L’avancée technologique vers des plateformes CMOS à ultra basse consommation est un défi majeur pour répondre aux exigences des marchés nomades et autres applications émergentes avec mémoires non volatiles embarquées. Ces mémoires sont en constante évolution, notamment par la diminution de leur dimension vers des nœuds technologiques avancés comme le 40nm et le 28nm. Dans cette thèse, nous présenterons une mémoire non volatile innovante appelée eSTM (embedded Select Trench Memory). Cette cellule possède un transistor mémoire et un transistor de sélection vertical. Ce dernier est un atout essentiel pour l’optimisation de la consommation de la cellule. Son architecture permet d’obtenir une mémoire du type 2T en minimisant la surface occupée. L’objectif de cette thèse est d’étudier cette cellule développée sur une plateforme technologique 40nm et d’identifier les différentes problématiques liées à la miniaturisation vers le nœud technologique 28nm. A travers la modélisation, la caractérisation électrique et les calculs théoriques, nous verrons qu’il est possible de trouver des solutions d’intégration notamment avec l’adaptation des divers implants et des dimensionnels du transistor mémoire. La réduction des paramètres dimensionnels peut engendrer de nouvelles architectures, comme la cellule à recouvrement. Cette optimisation de la cellule eSTM fera également l’objet de ces travaux de thèse
Advanced applications based on microcontrollers cover multiple domains. The increase of the field of microcontrollers application is accompanied by a growth of the power consumption. This is a limit of the autonomy of nomadic systems. The technological advance towards ultra-low-consumption CMOS platforms is a major challenge to the requirements of mobile markets and other emerging applications with embedded non-volatile memories. These memories are constantly evolving, particularly by the size shrinking to advanced technological nodes such as 40nm and 28nm. In this thesis, we will present an innovative non-volatile memory called eSTM (embedded Select Trench Memory). This cell possesses a memory transistor and a vertical select transistor. The select transistor is essential to the optimization of the cell consumption. This memory constitutes a 2T architecture with a reduction of area. The objective of this thesis is to study this cell developed on a 40nm technological platform. We will identify the various problems related to miniaturization towards the 28nm technological node. Through the modelling, the electrical characterization and the theoretical calculations, we will see that it is possible to find solutions as the adaptation of the various implants and the dimensions of the memory transistor. This optimization of the eSTM cell will also be the subject of this thesis work
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23

Srowik, Rico. "Modellierung von Transistoren mit lokaler Ladungsspeicherung für den Entwurf von Flash-Speichern". Doctoral thesis, Technische Universität Dresden, 2007. https://tud.qucosa.de/id/qucosa%3A24067.

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In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert.
In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.
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Srowik, Rico. "Modellierung von Transistoren mit lokaler Ladungsspeicherung für den Entwurf von Flash-Speichern". Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1206006642261-96038.

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In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert
In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples
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25

Dai, Wenhua. "Large signal electro-thermal LDMOSFET modeling and the thermal memory effects in RF power amplifiers". Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1078935135.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xix, 156 p.; also includes graphics (some col.). Includes bibliographical references (p. 152-156).
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26

Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device". Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.

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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.
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27

Sarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell". Thesis, Indian Institute of Science, 1995. https://etd.iisc.ac.in/handle/2005/124.

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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.
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28

Sarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell". Thesis, Indian Institute of Science, 1995. http://hdl.handle.net/2005/124.

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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.
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29

Vagts, Christopher Bryan. "A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory". Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/24038.

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Approved for public release; distribution is unlimited
This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.
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30

Hilgers, Brandon. "SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies". DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1423.

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This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates memory for two process technologies (IBM 180nm cmrf7sf and ON Semiconductor 600nm SCMOS) and requires a minimum number of specifications from the user for ease of use, while still offering the option to customize the performance for speed or area of the generated SRAM cell. By automatically creating SRAM arrays, the compiler saves the user time from having to layout and test memory and allows for quick updates and changes to a design. Memory compilers with various features already exist, but they have several disadvantages. Most memory compilers are expensive, usually only generate memory for one process technology, and don’t allow for user-defined custom SRAM cell optimizations. This free design makes it available for students and institutions that would not be able to afford an industry-made compiler. A compiler that offers multiple process technologies allows for more freedom to design in other processes if needed or desired. An attempt was made for this design to be modular for different process technologies so new processes could be added with ease; however, different process technologies have different DRC rules, making that option very difficult to attain. A customizable SRAM cell based on transistor sizing ratios allows for optimized designs in speed, area, or power, and for academic research. Even for an experienced designer, the layout of a single SRAM cell (1 bit) can take an hour. This command-line-based tool can draw a 1Kb SRAM block in seconds and a 1Mb SRAM block in about 15 minutes. In addition, this compiler also adds a manually laid out precharge circuit to each of the SRAM columns for an enhanced read operation by ensuring the bit lines have valid logic output values. Finally, an analysis on SRAM cell stability is done for creating a robust cell as the default design for the compiler. The default cell design is verified for stability during read and write operations, and has an area of 14.067 µm2 for the cmrf7sf process and 246.42 µm2 for the SCMOS process. All factors considered, this SRAM compiler design overcomes several of the drawbacks of other existing memory compilers.
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31

Liao, Si-yu. "Caractérisation électrique et électro-optique de transistor à base de nanotube de carbone en vue de leur modélisation compacte". Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14254/document.

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Afin de permettre de développer un modèle de mémoire non-volatile basée sur le transistor à nanotube de carbone à commande optique qui est utilisée dans des circuits électroniques neuromorphiques, il est nécessaire de comprendre les physiques électroniques et optoélectroniques des nanotubes de carbone, en particulier l’origine de l'effet mémoire que présente ces transistors. C’est dans ce contexte général que cette thèse s'intègre. Le travail est mené sur trois plans :• Caractériser électriquement et optoélectroniquement des structures de test des CNTFETs et des OG-CNTFETs.• Développer un modèle compact pour les contacts Schottky dans les transistors à nanotube de carbone de la façon auto-cohérente basé sur le diamètre et la nature du métal d’électrode en utilisant la méthode de la barrière effective avec les paramètres nécessaires calibrés.• Modéliser l'OG-CNTFET selon les régimes de fonctionnement, lecture, écriture, effacement ou programmation pour application à une mémoire non-volatile en intégrant le mécanisme de piégeage et dépiégeage à l’interface polymère/oxyde
This PhD thesis presents a computationally efficient physics-based compact model for optically-gated carbon nanotube field effect transistors (OG-CNTFETs), especially in the non-volatile memory application. This model includes memory operations such as “read”, “write”, “erase” or “program”, and “reset” which are modeled using trapping and detrapping mechanisms at the polymer/oxide interface. The relaxation of the memory state is taken into account. Furthermore, the self-consistent modeling of Schottky barriers at contacts between the carbon nanotube channel and metal electrodes is integrated in this model applying the effective Schottky barrier method. The Schottky contact model can be included in CNTFET based devices for a typical biasing range of carbon nanotube transistors. This compact model is validated by the good agreement between simulation results and experimental data (I-V characteristics). In the non-volatile memory application, this model can fully reproduce device behaviors in transient simulations. A prediction study of the key technological parameter, the CNT diameter variety is established to expect its impact on the transistor performance, and more importantly, on the memory operation. In the other hand, this thesis presents a preliminary electric characterization (I-V) of CNTFETs and OG-CNTFETs for the device modeling database. A preliminary optoelectronic characterization method is proposed
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32

Boubaker, Aimen. "Modelisation des composants mono-electroniques : Single-Electron Transistor et Single-Electron Memory". Lyon, INSA, 2010. http://theses.insa-lyon.fr/publication/2010ISAL0046/these.pdf.

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[Ce travail concerne le développement des mémoires à un électron de type SET/SEM pour les technologies CMOS silicium. Le premier chapitre du manuscrit est consacré à la présentation d' une revue bibliographique des phénomènes apparaissant dans les nanodispositifs électroniques (effets quantiques, blocage de Coulomb) de type transistors et mémoires à un électron. Dans le deuxième chapitre, nous nous intéressons aux diffë rents modèles électriques proposés pour les SETs. Grâce à des simulations numériques développées sous SPICE, nous avons approfondi notre compréhension du fonctionnement des SETs dans quelques exemples d'applications. Il s' agissait notamment de comparer les modèles dans le cas de SETs métalliques et semiconducteurs. Le troisième chapitre concerne la définition de l' architecture mémoire à un électron de type SET/SEM que nous proposons d'étudier. Après avoir présenté le concept de la structure SET/SEM, et expliqué le principe de fonctionnement dans les modes de lecture et de programmation, nous détaillons les résultats de simulations des caractéristiques du dispositif proposé. Après avoir opté pour une mémoire utilisant deux îlots métalliques pour les opérations de stockage de charge et de lecture respectivement, nous avons utilisé le logiciel SIMON afi n de proposer une architecture optimisée. Les travaux de simulations de l'architecture SET/SEM nous ont permis de calculer les éléments de circuits du modèle électrique équivalent permettant un fonctionnement optimal de la mémoire. Un aspect fondamental pour cette étude était en effet d'optimiser le décalage OVg des caractéristiques Ig-Vg observé lors de l' injection d'électrons uniques dans le point mémoire. Finalement, nous avons démontré qu'un décalage de quelques dizaines de m V/ électron était possible dans notre architecture. Dans le quatrième chapitre, nous présentons une étude détaillée des mécanismes de transport dans le bloc de mémorisation. Un modèle électrique de la cinétique de charge et décharge a été utilisé en prenant en compte l'effet du champ électrique. Finalement, nous avons étudié l' influence des paramètres technologiques comme les épaisseurs d'oxyde et la surface de l' îlot de mémorisation afin de proposer un dimensionnement de l'architecture SET/SEM. Ces simulations faites dans un premier temps à partir du système Ti / Tiüx utilisé dans la technologie nanodamascène développée à l'Université de Sherbrooke, ont pu dans un second temps être étendues à d'autres systèmes de matériaux afin de pro poser les matériaux présentant les meilleurs temps de rétention théoriques. Après avoir comparé les simulations d'îlots métalliques en Pt, Au, TiSi2, NiSi et Ti, nos travaux montrent que titane associé au Ti02 présente les meilleurs temps de rétention à 85% y compris à des températures aussi élevées que 430K qui représente actuellement la température maximale de fonctionnement des SETs réalisés à l'uni versité de Sherbrooke. ]
[This work concerns the study of SET/SEM single electron memories for CMOS technologies. The first part presents a review of quantum and Coulomb blockade effects in electronic nanodevices. In a second part, we present the main electrical models proposed for single electron devices. A comparison between semiconductor-based and metall ic-based single electron transistors. The third part of the thesis presents the SET/SEM memory structure on the basis of SIMON simulations. The device consists on the coupling of a metallic SET operating at high temperature with a metalli c memory node. Finnaly, an optimized memory device has been proposed in the Ti/Tiüx system. The proposed memory is able to write and erase a discrete number of electrons varying from 0 to 7 at room temperature. This opens the possibility of multilevel memory circuits. Finally, we have studied the data retenti on performances of the memory in the last part of this thesis. After the first simulations with the Ti/Tiüx materials system, we have simulated various metallic systems such as Pt, Au, TiSi2, and NiSi. We have shown that finally, the Ti/Ti02 systems gives the best data retention performances even at high temperatures, up to 430K. . ]
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33

Candelier, Philippe. "Contribution à l'amélioration de la fiabilité des mémoires non volatiles de type flash EEPROM". Université Joseph Fourier (Grenoble ; 1971-2015), 1997. http://www.theses.fr/1997GRE10245.

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L'augmentation continue de la densite d'integration des memoires non-volatiles de type flash eeprom passe par la comprehension des mecanismes de degradation intervenant dans le cadre du fonctionnement de ces memoires. Nous avons pu correler les degradations observees sur des dispositifs elementaires (transistors et capacites) aux derives des caracteristiques de la cellule flash. Cette etude demontre que de nouveaux modes de fonctionnement devront etre envisages. Le mode d'effacement par la source, habituellement utilise, pose des problemes d'optimisation technologique pour les cellules de faible longueur de grille (generation de trous chauds difficile a controler). Il devra vraisemblablement etre remplace par l'effacement fn qui est plus fiable pour les criteres d'endurance et de retention apres endurance. Parmi les degradations observees, le probleme principal est l'augmentation de la perte de charge avec l'amincissement des dielectriques et avec la degradation de l'oxyde de grille lors des cycles ecriture/effacement. Face au premier probleme, la mise en place d'une fonction de rafraichissement periodique semble necessaire. Face au second probleme, l'effacement fn a ete optimise en minimisant le champ electrique dans l'oxyde de grille par l'utilisation d'impulsions trapezoidales. Des progres technologiques importants (dielectriques interpolysilicium deposes, isolation laterale de type box) ont ensuite ete introduits dans le procede de fabrication afin permettre une integration plus poussee. La validation de ces evolutions technologiques ouvre les portes de la generation de cellules flash 0. 25 m. Finalement, face au probleme d'augmentation de la densite d'integration, la programmation multi-niveaux est une solution simple dont la fiabilite a ete amelioree grace a la realisation d'un systeme de programmation convergente. La faisabilite d'un doublement de capacite memoire a alors ete demontree.
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34

ZHAO, CHUAN-ZHEN y 趙傳珍. "Floating-gate mos transistors as analog memory devices". Thesis, 1992. http://ndltd.ncl.edu.tw/handle/33712669387087189947.

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35

(7046639), Feng Zhang. "Transition Metal Dichalcogenide Based Memory Devices and Transistors". Thesis, 2019.

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Silicon based semiconductor technology is facing more and more challenges to continue the Moore's law due to its fundamental scaling limitations. To continue the pace of progress of device performance for both logic and memory devices, researchers are exploring new low-dimensional materials, e.g. nanowire, nanotube, graphene and hexagonal boron nitride. Transition metal dichalcogenides (TMDs) are attracted considerable attention due their atomically thin nature and proper bandgap at the initial study. Recently, more and more interesting properties are found in these materials, which will bring out more potential usefulness for electronic applications. Competing with the silicon device performance is not the only goal in the potential path finding of beyond silicon. Low-dimensional materials may have other outstanding performances as an alternative materials in many application realms.

This thesis explores the potential of TMD based devices in memory and logic applications. For the memory application, TMD based vertical devices are fully studied. Two-terminal vertical transition metal dichalcogenide (TMD) based memory selectors were firstly built and characterized, exhibiting better overall performance compared with some traditional selectors. Polymorphism is one of unique properties in TMD materials. 2D phase engineering in TMDs attracted great attention. While electric switching between semiconductor phase to metallic phase is the most desirable. In this thesis, electric field induced structural transition in MoTe2 and Mo1-xWxTe2 is firstly presented. Reproducible bipolar resistive random access (RRAM) behavior is observed in MoTe2 and Mo1-xWxTe2 based vertical devices. Direct confirmation of a phase transition from a 2H semiconductor to a distorted 2Hd metallic phase was obtained after applying an electric field. Set voltage is changed with flake thickness, and switching speed is less than 5 ns. Different from conventional RRAM devices based on ionic migration, the MoTe2-based RRAMs offer intrinsically better reliability and control. In comparison to phase change memory (PCM)-based devices that operate based on a change between an amorphous and a crystalline structure, our MoTe2-based RRAM devices allow faster switching due to a transition between two crystalline states. Moreover, utilization of atomically thin 2D materials allows for aggressive scaling and high-performance flexible electronics applications. Both of the studies shine lights on the new application in the memory field with two-dimensional materials.

For the logic application, the ultra thin body nature of TMDs allows for more aggressive scaling compared with bulk material - silicon. Two aspects of scaling properties in TMD based devices are discussed, channel length scaling and channel width scaling. A tunability of short channel effects in MoS2 field effect transistor (FET) is reported. The electrical performance of MoS2 flakes is governed by an unexpected dependence on the effective body thickness of the device which in turn depends on the amount of intercalated water molecules that exist in the layered structure. In particular, we observe that the doping stage of a MoS2 FET strongly depends on the environment (air/vacuum). For the channel width scaling, the impact of edge states in three types of TMDs, metallic Td-phase WTe2 as well as semiconducting 2H-phase MoTe2 and MoS2 were explored, by patterning thin flakes into ribbons with varying channel widths. No obvious charge depletion at the edges is observed for any of these three materials, which is different from what has been observed in graphene nanoribbon devices.
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36

Po-KangHuang y 黃柏綱. "Memory and electrical effects in organic n-type memory transistors with pn heterojunctions". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/14050039273469963372.

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碩士
國立成功大學
光電科學與工程學系
104
The relationship between the thickness of pentacene in p-n heterojuntions and the electrical performance of non-volatile organic transistor memories (NVOTMs) was investigated in this study. The pentacene layer was deposited onto a 2.5 nm-thick PTCDI–C13H27 film to construct a heterostructure. The thicknesses of discontinuous pentacene films were found in the range between 2 and 5 nm measured by using atomic force microscope, while the completely continuous pentacene layer was about 10 nm. An ambipolar behavior in the output characteristics was observed in the NOVM with the continuous pentacene layer. Only n-type output characteristic was obtained in the NOVMs with the discontinuous pentacene layers. These results show that the continuous pentacene layer can improve the transport of holes, whereas the discontinuous pentacene layer cannot produce sufficient holes within the conductive channel. The memory windows of all NOVMs with p-n heterojunctions were studied. Among all the devices, the NOVM embedded the 5 nm-thick pentacene layer within the PTCDI–C13H27 has the largest memory window. This significant performance could be attributed to the appearance of discontinuous pentacene layer, which can provide the minority, i.e. holes, to promote the erasing ability. On the contrary, the continuous pentacene layer screens the trapped electrons during the programming operation and reduces the injection of holes during the erasing operation, yielding a decrease of memory window. In summary, we demonstrated an effective method to control the memory window by inserting p-n-heterojunction structure at polyimide/PTCDI-C13H27 interface.
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37

Chen, Chao-Fu y 陳昭福. "Ambipolar germanium nanowire transistors and their nonvolatile memory applications". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/chqe54.

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碩士
國立中興大學
物理學系所
103
Germanium (Ge) has recently re-gained significant amount of interests in the semiconductor research and industrial community due to its great potential and distinct characteristics in nature. High carrier mobility makes germanium become much better channel material for developing high-performance field effect transistors (FETs). Besides, its Bohr radius of 24.3 nm is much larger than that of Si (4.9 nm), which implies that quantum confinement effects will be more essential in further nanoelectronics. Herein, Ge nanowries (NWs) with an average diameter of 70 nm were investigated. Standard electron-beam lithography and thermal evaporation were used to fabricate Ge NW FETs. To improve electrical contacts between Ge NW and Cu electrodes, the as-made FETs were suffered from a post-annealing process at 150 OC for 30 mins in high vacuum. Surprisingly, the ambiopolar charge transport has been observed in the Ge NW FETs for the first time. Such an ambipolarity can be mainly ascribed to the formation of Schottaky barriers in both NW-electrode contacts. Besides, a non-ignored hysteresis loop with a memory windows up to 70 V has been observed in transfer characteristics and then Ge-NWs-based nonvolatile memories have been realized.
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38

Tu, Cheng-Hui y 凃政暉. "Micro-crystalline silicon thin film transistors and memory devices". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/65667588506075349791.

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Resumen
碩士
國立交通大學
光電工程學系
100
In this thesis, high crystallinity and low resistivity of intrinsic and n-type microcrystalline silicon (μc-Si:H) thin films were deposited at 265oC by inductively coupled plasma chemical vapor deposition system (ICPCVD). The high crystallinity of μc-Si:H and thin incubation layer of amorphous silicon (a-Si) were examined by the analysis of X-Ray diffraction (XRD) and transmission electron microscope (TEM), respectively. In addition, after systematically optimizing the parameters of dielectric, such as Ar flow, RF power, chamber pressure and the ratio of SiH4/N2O, the high quality dielectric was developed. The dielectric with ultra-thin thickness (5nm), low leakage current dielectric (10-8A/cm2 within 10 V operation) and compact film were examined by interface trap state density by high/low frequency method, analysis of leakage current and etching rate evaluation. Therefore, we use plasma to developed low leakage current and defect and successfully construct a series of top-gate thin film transistors (TFTs) with different thickness. This plasma technology will be able to achieve the vision of the 3D stacking device. This dielectric with low interface trap states enables the reduction of threshold voltage of 1 V. By integration of active layer with high crystallinity and dielectric with high quality, the staggered top- and bottom- gate TFTs achieved mobility of 466 cm2/V-s and 123 cm2/V-s, sub-threshold swing of 0.1~0.2 V/decade and on/off ratio of 106. Nonvolatile memories such as flash memories and electrically erasable programmable read-only memories (EEPROMs) on silicon wafers have been extensively utilized in high-density memories, programmable logic, and microcontrollers. However, fabricating nonvolatile memory devices with favorable electrical characteristics on glass substrates is difficult because of the limit on the glass transition temperature (Tg) of glass substrates. Finally, we implement this dielectric and active layer technology in metal-oxide-nitride-oxide-semiconductor (MONOS) type nonvolatile memory (NVM), successfully reduce the program/erase voltage, and constructi low temperature SONOS-memory operated with low and fast programmable pulses. Since SOP technology is primarily used for portable electronics, low power consumption is a basic requirement to ensure a long battery life. This breakthrough not only reduces the cost of device fabrication but also is very promising for industrial application.
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39

Li-ZhenYu y 游力蓁. "Investigation of bistable organic thin film transistors and organic memory devices". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/26503818225943833213.

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Resumen
博士
國立成功大學
微電子工程研究所碩博士班
98
The current?voltage characteristics of the gate?controlled three?terminal organic?based transistors with memory effect and negative differential resistances (NDR) were studied. Gold and 9,10-di(2-naphthyl)anthracene (ADN) were used as the metal electrode and active channel layer of the transistors, respectively. By using various gate?source voltages, the memory and NDR characteristics of the transistors can be modulated. The memory and NDR characteristics of the transistors were attributed to the formation of trapping sites in the interface between Au electrode and ADN active layer caused by the defects, when Au metal deposited on the ADN active layer. However, the different in the current values for the ON and OFF states can be improved. The vertical structure was used to improve the memory characteristics of the transistors. Three?terminal vertical organic memory transistors were fabricated to investigate the memory mechanisms and the relation between memory behavior and applied electrical field. The 9,10-di(2-naphthyl)anthracene (ADN) was used as the active channel layer for the organic memory transistors. In both the ON and OFF state of the organic memory transistors, the drain?source currents (IDS) were modulated by applying various gate?source voltages (VGS). The switching drain?source voltage (VDS) decreased with an increase in applied VGS voltages. The ON/OFF IDS current ratio of the organic memory transistors could be modulated up to the maximum value of 2.02x105 by applying VGS voltage bias. To investigate the memory bistable mechanisms of organic memory devices, the structure of [top Au anode/9,10-di(2-naphthyl)anthracene (ADN) active layer/bottom Au cathode] was deposited using a thermal deposition system. The Au atoms migrated into the ADN active layer was observed from the secondary ion mass spectrometry. The density of 9.6×1016 cm-3 and energy level of 0.553 eV of the induced trapping centers caused by the migrated Au atoms in the ADN active layer were calculated. The the memory bistable behaviors of the organic memory devices were attributed to the induced trapping centers. The energy diagram was established to verify the mechanisms.
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40

Chen, Yen-Ting y 陳彥廷. "The Non-volatile Capacitorless Memory by Poly-Si Thin Film Transistors". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/74236583796303918780.

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Resumen
碩士
國立臺灣大學
電子工程學研究所
97
In recent years, low temperature polycrystalline silicon thin film transistors (LTPS TFTs) have been widely used in flat panel display driving circuit. The a-Si film is recrystallized to the poly-Si film by excimer laser crystalline method and achieves the advanced display technology. First, we will discuss the basic model and current conduction mechanism of grain boundaries in the poly-Si film. Due to the influence of grain boundaries, the subthreshold characteristics are explained by the gate and drain induced barrier lowering. The leakage current is also investigated by trap generation and emission in the drain depletion region. A novel capacitor-less random access memory has been developed in recent years and used in the storage devices. This memory exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The nonvolatile memory is utilized extensively in the electronic systems because of its long retention time and low power consumption. Therefore, we constructed a new memory device which is compatible with TFT fabrication processes. The new operation mode is to realize the memory characteristics by operating the poly-Si TFTs in the accumulation region. The application of capacitorless non-volatile memory based on poly-Si TFTs shows more advantages, such as low operation current, long retention time, low power consumption, and excellent endurance characteristics. Finally, drain avalanche hot carrier stress of n-channel TFTs is investigated. This degradation depends with the drain stress voltage, channel length and stress temperature. The stress-induced degradation in the on-state current may be attributed to the hot carriers inject into the grain boundaries to create amount defect states. The threshold voltage shift can be explained that the hot carriers inject to the interface and create the negative interface states. The reliability issue must be taken into consideration for process and circuit design.
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41

Chen, Hung-Bin y 陳弘斌. "Gate-All-Around Nano-wire Channel Transistors and Nonvolatile Memory Devices". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/39836199160952168576.

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博士
國立交通大學
電子工程學系 電子研究所
101
This thesis is divided into five parts to demonstrate 3D IC applicable nonvolatile memories and thin-film transistors with nanostructures. In the first part, a poly-Si thin-film flash NVM with a Si-nanocrystal (Si-NC) embedded charge trapping layer through self-assembly processes has been presented. Experimental results indicate that memories with the Si-NC charge trapping layer exhibits high retention and endurance characteristics. After 10k P/E cycles, the data retention is remarkable for NVM applications due to the deep quantum well of Si-NC encapsulated in the Si3N4 layer and immunity to the enhanced electric field underneath the disk-shaped Si-NCs. In addition, reducing the thickness of the tunnel oxide can further lower the P/E voltage. This investigation examines the feasibility of poly-Si thin-film nonvolatile memory with the Si-NC embedded charge trapping layer on 3-D layer-to-layer stacked high-density NAND memory applications. In the second part, the bimodal shape of bent NWs has an impact on the electrical characteristics of GAA flash memory. Since the dielectric strength is not reduced in the dual-gate cell, the dual-gate GAA poly-Si NWs flash memory has better P/E characteristics and reliability performance than the single-gate memory. Additionally, the incorporation of the Si3N4/Si-NC/Si3N4 hybrid discrete trap layer causes dual-gate devices to exhibit excellent retention (>108 seconds for 17% charge loss). In the third part, The 2-bit effect of GAA NVM with Si NCs through self-assembly processes is investigated. The experimental results reveal that the GAA Si-NCs NVM performs clear 2-bit effect with gate length of 0.5 μm by CHE programming and channel hot holes erasing. At large gate length of 1 μm, F-N tunneling occurred and dominated which resulted in the absence of the 2-bit effect. In the programming and erasing characteristics studies, the gate-all-around structure can reduce operation voltage and shorten pulse time. In the retention characteristics studies, the Si-NCs of confining electrons in the narrow region assist the gate length scaling and lateral migration. In the forth part, A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The planar and GAA structure with ultra-thin channel and a Si3N4/Si-NC/Si3N4 hybrid discrete trap layer are introduced to poly-Si TFT flash memories. The experimental results indicate that ultra-low voltage operation for 3-nm Tch device by drain avalanche hot electron injection (DAHE) condition (Vg, Vd) = (0, <-3V) can process quantum programming. The ultra-thin channel device satisfies with both ultra-low power and high performance applications, and that with Si-NCs performs large memory window and data retention. Finally, the LTPS JL-GAA TFTs with ultra-thin channel are successfully fabricated by oxidation thinning method. Our junctionless device shows quasi-crystal channel due to the reduction of grain boundaries and defects, beneficial for excellent electrical performance. This process is simple and compatible with existing CMOS processes. Such a GAA JL feature simplifies the S/D engineering and the DIBL is very small. The low IOFF and the steep SS in JL-GAA TFTs result in high on/off current ratio up to 108, which can be used in high-speed and low power consumption applications.
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42

Ya-TingHsu y 許亞庭. "Investigation and Fabrication of Quantum Dot Optical Memory Thin Film Transistors". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/08213345638839286281.

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碩士
國立成功大學
微電子工程研究所
103
The main purpose of this thesis was focused on the deposition of quantum dots (QDs) thin film in organic optical memory thin film transistors by micro-contact printing technique and spin coating method. The QDs plays an important role in capturing the charge carriers in the transistor device. We compared the current increment and threshold voltage shift under illumination condition of the devices which were deposited QDs by these two methods. And investigated which of these device structures is more suitable for optical memory thin film transistors application. In the study of contact printing method, we used polydimethylsiloxane (PDMS) as the stamps. After spin coating the QDs on the PDMS stamp, the QDs were transfer onto the dielectric layer by means of using counterweight and dip coater, respectively. Because of the better distribution and uniformity of QDs monolayers which were printed by dip coater, we chose contact printing technique to transfer QDs by using dip coater to fabricate the devices. The basic structure was composed by n+-Si (gate electrode) / SiO2 (dielectric later) / pentacene (channel layer) / Au (source and drain electrodes). After transferring QDs between dielectric layer and channel layer, the device with QDs showed more obvious current increment and threshold voltage shift under illumination than conventional structure in the measurements of output and transfer characteristics. For the hysteresis test, the memory window could be increased from 9 V of conventional structure to 101 V of the device with QDs. This large memory window indicated that the structure using contact printing technique to transfer QDs on dielectric layer had the potential to be used for memory devices application. However, both structures showed poor characteristics, i.e. under illumination of white light or different wavelengths of light, the currents didn’t increase as expected but declined to even lower than the initial state. As the result, we investigated floating gate structure to improve this disadvantage. In the study of spin coating technique, the structure was n+-Si (gate electrode) / SiO2 (dielectric layer) / QDs-PMMA blends (floating gate) / PMMA (tunneling layer) / pentacene (channel layer) / Au (source and drain electrodes). Among the device structure, the films of floating gate and tunneling layer were formed by spin coating method. In electrical measurement, the current increment and threshold voltage shift under illumination were increased by the increasing concentrations of QDs of the devices. Memory windows and dynamic responses also showed identical tendencies, especially for the dynamic response under white light illumination, the current increased by 134.7 times for the device using QDs-PMMA blends (with 20 mg/ml QDs)as floating gate. And current under illumination of different wavelengths of lights also had obvious increments. In addition, the device with QDs-PMMA blends (with 20 mg/ml QDs) demonstrated the properties of “optical-writing” and “electrical-erasing”, as a result, it can be viewed as an optical memory thin film transistor. Due to the PMMA layer was used as blocking layer, after turning off the light, electrons were trapped by QDs and difficult to be transferred to the active layer and recombined with holes. Therefore, the current could maintain for a period of time and didn’t decline to the initial state. According to the results of atomic force microscopy (AFM) measurement, after spinning PMMA as modified layer, the Rrms could be reduced under 1.5 nm which was benefit to the growth of pentacene layer and device performance.
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43

Yi-ShengLin y 林益生. "Functional polymer dielectrics applied in PTCDI-C13H27-based sensors, memory, and transistors". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/32060341542438600449.

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博士
國立成功大學
光電科學與工程學系
103
This thesis focuses on the applications of N,N’-ditridecyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C13H27)-based optoelectronic devices and the evaluation of anisotropic charge transport capability in a pentacene cluster via electronic coupling energy mapping using quantum chemical calculation. PTCDI-C13H27 is a potential n-type organic semiconductor with high electron mobility. In this thesis, the applications of PTCDI-C13H27-based optoelectronic devices are grouped into three subjects, with particular focus on functional dielectric layers for organic thin-film transistors (OTFTs). The three subjects are (a) the time-dependent current growth phenomenon of PTCDI-C13H27-based OTFTs using a dielectric buffer layer consisting of strong and weak dipole units, (b) the optoelectronic properties of PTCDI-C13H27-based OTFTs, which include a switch OTFT and a sensor OTFT, with potential for use in in-cell devices, and (c) a photoinduced memory effect in PTCDI-C13H27-based OTFTs through phenolic dielectric buffer layers. Besides, charge transport capability of pentacene in various crystal polymorphisms was also discussed in the thesis by quantum chemical calculation. In the first part of this thesis, we describe an unusual phenomenon of time-dependent current growth that was first observed in OTFTs, particularly n-type transistors. We obtained the time-dependent growth of the drain current and nearly hysteresis-free electricity under DC bias stress for PTCDI-C13H27-based OTFTs with a polyimide (PI) dielectric layer. These phenomena are attributed to (a) a reduction in trap state density located at the interface between the PI layer and semiconductor, (b) the effective gate field enhanced by electric dipoles within the PI, and (c) a low interface trap lifetime. A polymer dielectric with moderate polar groups is suitable for application in stable organic devices. In the second part, we demonstrated that the control of the operating voltage for OTFT-based photosensors (photo-OTFT) is an essential factor that can enhance the photocurrent/dark current ratio (P). This phenomenon is due to the reduction of the contribution of field-effect current to output current under dark state. In this study, we analyzed a highly sensitive, flexible, organic photosensor made from cross-linked poly(4-vinylphenol) (C-PVP) as a polymer dielectric layer and PTCDI-C13H27 as an n-type active layer on a transparent polyethersulfone (PES) substrate, by tuning both source-drain and source-gate voltages to the neighbor of threshold voltage (Vt = 3.0 V). Interestingly, a maximum P was obtained when the operating voltage was reduced to around Vt. The time-response characteristics and sensitivity of the PTCDI-C13H27-based photosensor were clearly investigated. Considerable interest has been given to the flexible in-cell remote touch screen that comprises both photosensitive and switch OTFTs. In this work, both OTFT-based switch (switch-OTFT) and photo-OTFT were shown to form on the flexible PES substrate using the same fabrication process. The electrical characteristics of switch-OTFT under bending states were discussed in terms of photoluminescence and time-resolved photoluminescence measurements, as well as quantum theory calculations. In the third part, we discussed our discovery on the photoinduced phenomenon of current enhancement and memory effect, in which was discovered in a PTCDI-C13H27-based OTFT structure of non-volatile memory (NVM) devices. This phenomenon was observed after illumination with 532 nm laser for 2 min. The C-PVP electret layer, which consists of hydroxyphenyl group was assembled in NVM. The retention of photoinduced memory effect in C-PVP-based NVM was more than 1 day. Two kinds of dipoles, namely, instantaneously strong and quasi-permanent, caused the photoinduced memory effect in C-PVP-based NVM. An instantaneously strong dipole (27.9 D) was introduced by the excitation process of PTCDI-C8H17 dimer (a derivative of PTCDI family). The quasi-permanent dipole in C-PVP electret layer was generated and aligned by the instantaneously strong dipole. The accumulated charge varied with electric field, time-dependent capacitance measurement, and quantum chemical simulation, which were used to analyze the photoinduced memory effect. To further verify whether the hydroxyphenyl group is the key factor of photoinduced memory effect in NVM, we employed four types of electret layers [poly(4-vinylphenol) (PVP), poly(styrene) (PS), poly(vinyl alcohol) (PVA), and PS doped with 1 wt% 1,2-dihydroxybenzene (catechol)] to fabricate NVMs. Results indicated that only the electret of NVMs had hydroxyphenyl group or similar group, and the photoinduced memory effect could be observed. The results in this study could be used as reference in designing electret materials for photoinduced n-type NVMs. In the fourth part, We proposed an approach for evaluating the charge transport capability of pentacene molecules in various crystal polymorphisms in the framework of Marcus theory of electron-transfer reactions. Crystal-induced reorganization energy (reg) and electronic coupling energy (J), which are the key factors that determine charge hopping mobility in various molecular configurations of crystal clusters, are calculated by using quantum chemical calculation. In particular, we examined the effects of the edge-to-face angle (ef) and tilt angles (tilt) of pentacene molecules in crystal clusters on charge mobility because the two parameters are difficult to determine experimentally. In addition to the effects of lattice constants, we found that tilt and ef exert a large impact on the charge mobility capability of pentacene in various crystal polymorphisms. Our mapping results provide a complete understanding of crystal-induced ambipolar transport capability of pentacene molecules. We highlight that the electron mobility of pentacene molecules are possibly as fast as hole mobility, i.e., balanced ambipolar transport, unlike the previous idea of hole-dominated transport.
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44

Meng-HuiShen y 沈孟慧. "Solution-processed Melanin for Pentacene-based Thin Film Transistors and Memory Applications". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/52919387650089125209.

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Resumen
碩士
國立成功大學
微電子工程研究所碩博士班
101
Solution-processed melanin, one of environmentally friendly and biocompatible biomaterial, was applied in pentacene-based organic thin film transistors (OTFTs) as gate dielectrics, and resistive random-access memories (RRAMs). The chemical composition of the solution-processed melanin thin film (C64N11O24) was verified through energy dispersive spectrometer and Raman spectra. The smooth surface morphology was analyzed by atomic force microscope, while the amorphous thin film was also observed via X-ray diffraction. The electrical properties of thin film transistors show high field-effect mobility of 18.19 cm2V-1s-1, low threshold voltage of -0.4 V, and low subthreshold swing of 280 mV/decade. The good performance of OTFTs can be attributed to the negatively-charged melanin film due to the absence of H3O+ ions after baking treatment. On the other hand, different top electrodes, bottom electrodes, as well as baking temperatures have been discussed in melanin thin film RRAMs. The best performance was obtained by using ITO/melanin/Al structure, which can be attributed to smooth surface and lower work function of top electrode than bottom electrode. The set/reset voltage and on/off ratio are -1.24/2.4 V and 4.7 x 103, respectively. The easily-formed filament results from the existence of ions in melanin, especially in film without baking.
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45

Huang, Cheng-Chieh y 黃證潔. "Study on Nonvolatile Memory Characteristics of Few-layered InSe Field Effect Transistors Devices". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/29491784282725727758.

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碩士
國立中山大學
物理學系研究所
104
Abstract Two-dimensional materials serve not only as good platforms for exploration of condensed matter physics, but also alternative materials to keep up with Moore’s Law due to their low dimensional characteristics. Recently, our group have found that the indium selenide (InSe) belonged to III-VI groups has high photo-responsivity (~ 12.3 A/W) in wavelengths from visible to infrared light. Based on these results, we take one step further to investigate the fundamental electrical properties and hysteresis phenomenon of the back-gate field-effect transistors to be possible applications for memory devices. InSe exhibits N-type semiconductor characteristic, high switching current ratio, and the carrier mobility is 0.75 (cm2/Vs) based on the ID-VG measurements. Interestingly, our devices show hysteresis phenomenon and long retention time. Such phenomenon is because that carriers are captured by surface defects. Furthermore, we find the InSe devices with different channel thickness (5 nm, 6 nm and 11 nm) all have long retention time (2315 days, 300 days, and 234 days, respectively). We conclude the reason is because of the highest the ratio of the surface defects and carrier concentration. Moreover, retention time of devices with different thickness (5 nm, 6 nm and 11 nm) can be further extended (9250 days, 4600 days, and 1850 days, respectively) after oxygen plasma treatments. We further determined the structure of the defects is indium oxide (In2O3) through X-ray photoelectron spectroscopy (XPS). To sum up, we demonstrated that InSe field-effect transistors have potential applications in memory devices. Unlike the traditional flash memory devices which need a storage layer to store charge, this proposed device has advantage of simplified process steps and vertical scaling down. Keywords：Two-dimensional materials, Indium Selenium, InSe-FET, Hysteresis, defects, memory.
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46

YU, TING-FENG y 余庭鳳. "Doped Donor-Acceptor Conjugated Polymers for Non-volatile Memory and Field-Effect Transistors". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/9bbr7j.

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碩士
國立臺北科技大學
化學工程與生物科技系化學工程碩士班
107
In resent year, organic semiconductor materials have attracted great attention due to their advantage, such as solution-process, large-area coating, low-temperature process, low-cost and flexibility. Therefore, they are widely used in organic electronic devices, such as organic filed effect transistors(OFETs), non-volatile OFET memory devices and organic light-emitting devices(OLED). The doping method can improve the charge transporting ability, improve the stability and electrical properties of organic semiconductor materials. Therefore, the influence of doping system on the transistor and memory components is mainly discussed in this study. 　　The first part of the experiment we used Diketopyrrolopyrrole (DPP)-based conjugated polymer to dope with ionic salts of different anions. This method can simplify the process of memory devices and reduce the cost, so that the semiconductor layer can also serve as a “charge storage site” at a same time to control the VTH shift. By Doping with 5 wt% of TBAP salts, the p-type diketopyrrolopyrrole (DPP)-based conjugated polymers boosts their memory window to up to 32V with an on/off current ratio larger than 104 without significant mobility degradation. Furthermore, the charge retention time can maintain over 106 s, indicating stable charge storage capability and great endurance of the device. From the write-read-erase-read (WRER) cycles, the ON and OFF states can be reversibly switched over 100 cycles without showing significant current degradation, indicating great reversibility in our doped memory devices. From the AFM image, we observed significant fiber-like morphology. After doping ionic dopant, there were small aggregates formed on the PDBT-co-TT/TBAP film. The aggregates may create charge trapping sites and enhance memory windows. The dopant did not damage the crystalline structure from GIXD analysis. This study provides an efficient and facile method to produce solution-processable low-cost non-volatile organic field effect transistor memory device through ionic doping. 　　The second part is made into a transistor by doping a small molecule of naphthalene diimides with photo-sensitive properties into an NDI conjugated polymer. This NDI small molecular can induce a stable radical anion through photo-induce and provide electron to polymer, thus enhance electron transport. The current will increase as the doping concentration increase. The most significant increase is the doping of 50 wt% of small molecule additives. The charge mobility increases to 0.331 cm2V-1s-1 due to the influence of electric field and ultraviolet light. The charge mobility is six times larger than pure PNDI2T. After doping, we found that both aggregate and roughness will increase from the AFM image, but does not decrease the electric properties of the device. It was observed by GIXD that part of the polymer crystals will changed from face-on to edge-on. It is speculated that after doping, small molecules enter the polymer layer structure, and the polymer may be propped up. This is might be the reason for the increase in charge mobility. In order to improve the mixability of the polymer, this experiment synthesizes a self-doped conjugated polymer by copolymerized three different ratios of NDI-AP and NDI-OD (PNDI2TAP10%, PNDI2TAP25%, PNDI2TAP50%)and compared with commercially available PNDI2T. In this study, thermal stability, optical and electrochemical properties of conjugated polymers were investigated by TGA, UV and CV. In our system, PNDI2TAP10% exhibited the highest mobility of (4.24±0.59)×10-1 cm2V-1s-1 through solution shearing. From the AFM image, we observed significant fiber-like morphology. In this study, the NDI small molecule doping system was used to enhance the charge mobility, and the self-doped copolymer was also successfully synthesized.
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47

Shih, Jay Wen-chieh y 施文傑. "The Electrical Properties of Lead Zirconate Titanate Ferroelectric Transistors for Non-Volatile Memory Application". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/88062759597945372024.

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博士
國立清華大學
電子工程研究所
96
In this thesis, the electrical properties of Al/Pb(ZrTi)O3/insulator/Si capacitors and field effect transistors with various surface treatments were studied. The wafers were given a H2O2 pre-treatment before insulator layer deposition and a HCl post-treatment after deposition. For the case of Al/ZrO2/Si capacitors with surface treatments, the interface state density was reduced from 5.62x1013/cm2 to 4.0x1012/cm2 and the composite dielectric constant of ZrO2 film (about 7 nm) plus interfacial layer was increased from 5.54 to 7.3. The binding energy of the Zr-O bond was increased and the Zr out-diffusion was decreased based on X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) results, respectively. The leakage current density of Al/PZT/ZrO2/Si capacitors with both treatments was improved from 10-1 A/cm2 to 5.4x10-6 A/cm2 at 5 V and the retention time of Al/PZT/ZrO2/Si capacitors was improved from 13.3 hours to 17.1 days. The longer retention time of Al/PZT/ZrO2/Si capacitor with surface treatments was attributed to the reduced gate leakage current. The FeFETs with both treatments maintain a threshold voltage window of about 1.1 V after an elapsed time of 3000 sec. The subthreshold slope was improved from 311 mV/dec to 91 mV/dec. The drain current on/off ratio of FeFETs with both treatments was about 103. The improvements are most likely due to the reduction of the leakage current and the interface states at the ZrO2/Si interface. Al/PZT/Y2O3/Si FeFETs with both treatments were also fabricated. The leakage current density at 5 V is reduced from 10-3 A/cm2 to 10-6 A/cm2. Samples with no treatment show a much larger flat band voltage shift ΔVFB of 1.5 V compared to that of 0.8 V with both treatments. It means more electrons are injected into the insulator layer with no treatment as the positive bias is increased. The best FeFETs maintain a threshold voltage window of about 1.5 V after an elapsed time of 5000 sec. The drain current on/off ratio of FeFETs with both treatments after applying writing pulses of +8 V and -8 V with a duration of 100 ns was about 105. The improvements are most likely due to the reduction of the gate leakage current and the charge injection effect.
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48

Chang, Chin-Wei y 張晉偉. "Study of Nanowire Poly-Si Thin Film Transistors Nonvolatile Memory with Nitride trapping layer". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/23412393208577624137.

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49

Chih-KaiYang y 楊智凱. "Solution-processed Barium Zirconate Titanate for Pentacene-based Thin Film Transistors and Memory Applications". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/98630328538667154645.

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50

Huang, Chien-Jen y 黃建仁. "Fabrication of Multiple Nano-Channel SONOS Thin Film Transistors Memory by Nano Imprint Technology". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/18915701182485532743.

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碩士
國立暨南國際大學
電機工程學系
98
In this thesis, the multiple nano-channel SONOS thin film transistor memories were fabricated by combing UV nano imprint and conventional photolithography. The multiple nano-channels were fabricated by UV NIL and reactive ion etching. Then, the SONOS thin film transistor memories were fabricated. The electrical characteristics were measured by HP-4156, HP-4284, and Agilent B1500. In our results, the mold with the line/space width of about 100/50 nm and the nano-channel with the line/space width of about 70/70 nm were both fabricated successfully. The SONOS TFT memories with multiple nano-channels have higher on/off ratio (~3.6×107), lower threshold voltage (~0.6V), higher mobility (~42 cm2/V-sec), sharper sub-threshold swing (~270 mV/dec), larger memory window (1.7V), and faster program/erase efficiency than the SONOS with the simple channels. This technique will be suitable for the future SOP applications of the flat panel display.
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