Literatura académica sobre el tema "Memory transistor"
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Artículos de revistas sobre el tema "Memory transistor"
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Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold y Thomas Schimmel. "Copper atomic-scale transistors". Beilstein Journal of Nanotechnology 8 (1 de marzo de 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.
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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.
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Choi, Young Jin, Jihyun Kim, Min Je Kim, Hwa Sook Ryu, Han Young Woo, Jeong Ho Cho y Joohoon Kang. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications". Micromachines 12, n.º 3 (12 de marzo de 2021): 301. http://dx.doi.org/10.3390/mi12030301.
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Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer was used as a charge trapping layer for the non-volatile memory device applications. The non-volatile memory device showed clear memory window formation as applied gate voltage increases, and electrical stability was evaluated by performing retention and cycling tests. In summary, we demonstrate that a donor–acceptor-type organic semiconductor molecule shows great potential for ambipolar field-effect transistors and non-volatile memory device applications as an important class of materials.
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Kim, Woojo, Jimin Kwon y Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors". Journal of Flexible and Printed Electronics 2, n.º 2 (diciembre de 2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.
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Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.
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Kim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong y Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure". ECS Meeting Abstracts MA2023-02, n.º 30 (22 de diciembre de 2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.
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The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR). In this study, we propose a 3-terminal 2T0C DRAM to enhance its memory characteristics, where RBL was combined with WBL, enabling 2T0C memory operation with only three metal lines as shown in Fig. 1(b). In addition, we investigated the dependency of retenetion time of the proposed 2T0C DRAM on channel length. In particular we evaluated the dependency of the sneak current of 2T0C DRAM on off-current of transistor. For the fabrication of 3-terminal IGZO 2T0C DRAM, a top gate IGZO transistor was fabricated using RF sputtering and two transistors were connected by storage node and bit line bridge as shown in Fig. 1(d).The storage node was formed by connecting the gate of RTR to drain of WTR. And source electrodes of both transistors were coupled. To determine the voltage values for memory operation, the transfer curve of each transistor was characterized and the threshold voltages for both RTR and WTR were around 1 V. The write and read voltages were set to 3 and 2 V, respectively. The retention time was measured by performing periodic read operations after writing and measuring the RTR currents. In addition, the retention time of transistors for varying channel length and gate capacitance was characterized. The retention time was defined as the time to be taken for decreasing the currents by 90 %. Furthermore, the disturbance of 2T0C DRAM with 2x2 array structure was investigated. The RTR currents of selected cells were measured depending on the memory state of adjacent cells. It was found that the retention times of transistors with 10- and 100-um RTR channel lengths were approximately 15 and 30 seconds, respectively. It was observed that the memory state was not changed from “0“ to “1“ by disturbant currents, but, RTR currents of “0“ state cell increased slightly when an adjacent cell was turned on. However, as shown in Fig.1(i) and (j), when off-currents of transistor of 2T0C DRAM decreased from 20 nA to 200 pA, it was confirmed the sneak current of 2T0C decreased. Finally, several technical apporaches how to suppress the disturbant currents will be presented in detail. Acknowledgement This research was supported by BrainKorea21 Four. Figure 1
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Al-shawi, Amjad, Maysoon Alias, Paul Sayers y Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors". Micromachines 10, n.º 10 (25 de septiembre de 2019): 643. http://dx.doi.org/10.3390/mi10100643.
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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).
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Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs". Journal of Electrical Engineering 64, n.º 5 (1 de septiembre de 2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.
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Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplified if we consider the lossless transistors or if the y21 -parameter of one transistor is alpha multiple of second ones.
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Grudanov, Oleksandr. "Stability Parameters of Register File Bit Cell with Low Power Consumption Priority". Electronics and Control Systems 3, n.º 77 (27 de septiembre de 2023): 40–46. http://dx.doi.org/10.18372/1990-5548.77.17963.
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This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.
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Fuller, Elliot J., Scott T. Keene, Armantas Melianas, Zhongrui Wang, Sapan Agarwal, Yiyang Li, Yaakov Tuchman et al. "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing". Science 364, n.º 6440 (25 de abril de 2019): 570–74. http://dx.doi.org/10.1126/science.aaw5581.
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Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.
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Srinivasarao, B. N. y K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture". Journal of VLSI Design and Signal Processing 8, n.º 1 (30 de marzo de 2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.
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SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.
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Seo, Yeongkyo y Kon-Woo Kwon. "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application". Electronics 12, n.º 20 (12 de octubre de 2023): 4223. http://dx.doi.org/10.3390/electronics12204223.
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This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin.
Tesis sobre el tema "Memory transistor"
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Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device". Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.
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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs)
with copper electrodes prepared by a novel plasma etching process have been fabricated
and studied. Their characteristics are similar to those of TFTs with molybdenum
electrodes. The reliability was examined by extended high-temperature annealing and
gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this
plasma etching method.
Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different
experimental stages have been measured. The gamma-ray irradiation damaged bulk
films and interfaces and caused the shift of the transfer characteristics to the positive
voltage direction. The field effect mobility, on/off current ratio, and interface state
density of the TFTs were deteriorated by the irradiation process. Thermal annealing
almost restored the original state's characteristics.
Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a-
Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The
hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large
charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been
detected. Charge storage is related to properties of the embedded a-Si:H layer and its
interfaces in the gate dielectric structure. Discharge efficiencies with various methods,
i.e., thermal annealing, negative gate bias, and light exposure, separately, were
investigated. The charge storage and discharge efficiency decrease with the increase of
the drain voltage under a dynamic operation condition. Optimum operating temperatures
are low temperature for storage and higher temperature for discharge.
a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film
embedded in the silicon nitride gate dielectric stack has been characterized for memory
functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage
curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded
a-Si:H layer had a charge storage capacity six times that of the capacitor without the
embedded layer. The nonvolatile memory device has potential for low temperature
circuit applications.
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Sarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell". Thesis, Indian Institute of Science, 1995. https://etd.iisc.ac.in/handle/2005/124.
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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the
possibility of fabrication of LBTs with a CMOS technology is established.
Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same.
A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.
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Sarkar, Manju. "Lambda Bipolar Transistor (LBT) in Static Random Access Memory Cell". Thesis, Indian Institute of Science, 1995. http://hdl.handle.net/2005/124.
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With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the
possibility of fabrication of LBTs with a CMOS technology is established.
Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same.
A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.
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Vagts, Christopher Bryan. "A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory". Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/24038.
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Approved for public release; distribution is unlimitedThis thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.
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Chaudhary, Mahima. "Colloidal nanocrystals for optoelectronic devices optically controlled at the nanometric scale". Electronic Thesis or Diss., Université Paris sciences et lettres, 2022. http://www.theses.fr/2022UPSLS072.
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L'optoélectronique est un domaine technologique en croissance rapide qui implique l'utilisation d'appareils électroniques pour générer, détecter et contrôler la lumière. Ces dispositifs peuvent être utilisés dans une variété d'applications telles que les commutateurs photoconducteurs, les systèmes de contrôle d'accès automatique, les télécommunications, la mémoire et bien d'autres. Parce qu'il s'agit d'un domaine si vaste, la variété des dispositifs qui relèvent de l'optoélectronique est vaste. Dans ceThèse de doctorat, Je suis particulièrement intéressédanstraitable en solutionnanomatériaux colloïdaux qui peuventpermettre les interactions lumière-matière.Pour commencer, je me suis d'abord concentré sur la synthèse colloïdale. Latravailler sur cette partie rendementsdeux types différents de nanocristaux colloïdaux :(1)NaYF4 dopé Er3+ nanocristaux, capables d'absorberet up-convertphotons infrarouges à ondes courtes tels que ceux avec= 1,5 µmaux photons visibles ; (2)points quantiques de carbone(CQD)avec dopage à l'azote, capable d'absorber les photons UVet les rétrograder en visiblefluorescence.Dès l'obtention du résultat souhaitécolloïdalnanocristaux aux propriétés optiques adaptées, j'ai ensuiteles a appliqués dansdeux types dedispositifs optoélectroniques : (je) Pcommutateurs thermoconducteurs, qui permettent un contrôle optique de l'amplitude et de la phase des signaux micro-ondes à transmettre. Pour obtenir des commutateurs photoconducteurs micro-ondes fonctionnels à = 1,55µm éclairage,le NaYF4 dopé Er3+ mentionné ci-dessusnanocristaux de conversion ascendanteétaientdéposé directement sur l'arséniure de gallium cultivé à basse température (LT-GaAs)pour réaliser des interrupteurs photoconducteurs. Les propriétés de ces appareils ont ensuite étécaractérisé. Grâce aux propriétés d'upconversion des photons de ces nanocristaux,l'exposition sur les interrupteurs photoconducteurs hybrides unRapport marche/arrêtplus de 2 fois plus élevé en décibels queladispositif de commande sansnanocristals appliqué. (ii) Effet de champmémoires optoélectroniques à base de transistors (FET).Dans ce champ,le support de stockage de chargejoue uncritiquerôleaude la mémoireperformance.Dans cette partie,jeexploite les propriétés uniques de piégeage et de rétention de charge dele susmentionnédes CQD colloïdaux dopés à l'azote (dopé N) pour réaliser des mémoires optoélectroniques fonctionnelles programmables par illumination UV et avec une possibilité d'écriture à plusieurs niveaux. En particulier, une fonction de mémoire de longue durée peut être obtenue grâce aux vastes sites de piégeage de trous fournis par ces CQD et à l'effet de photo-gating qui en résulte.excercised sur le graphène FET, tandis que l'effacement de la mémoire peut être réalisé via une polarisation de grille positive qui fournit suffisamment de porteurs pour la recombinaison de charge.Le résultat de cette thèse de doctoratpoints fortsles contrôles techniques et chimiques pour obtenirhaute performancedispositifs optoélectroniques tels que micro-ondescommutateurs photoconducteurs etmémoires optoélectroniques à base de FET non volatiles tout carbone par manipulation etrécoltelapropriétés optiques et électroniques des nanomatériaux colloïdauxOptoelectronics is a rapidly growing technology field that involves the use of electronic devices to source, detect, and control light. These devices can be used in a variety of applications such as photoconductive switches, automatic access control systems, telecommunications, memory, and many others. Because this is such a broad field, the variety of devices that fall under optoelectronics is vast. In this, PhD thesis, I am particularily intrested in solution processed colloidal nanomaterials that can allow light-matter intraction. To begin, I first focused on colloidal synthesis. The work on this part yileds two different types of colloidal nanocrystals : (1) Er3+-doped NaYF4 nanocrystals, capable to absorb and up-convert short-wave infrared photons such as those with = 1.5 µm to visible photons; (2) carbon quantum dots (CQDs) with nitrogen-doping, capable to absorb UV photons and down-shift them into visible fluorescence. Upon obtaining the desired colloidal nanocrystals with suitable optical properties, I subsequently applied them into two type of optoelectronic devices: Photoconductive switches, which allow optical control over the magnitude and phase of microwave signals to be transmitted. To achieve microwave photoconductive switches functional at = 1.55 µm illumination, the above-mentioned Er3+-doped NaYF4 upconversion nanocrystals were deposited directly onto low-temperature-grown gallium arsenide (LT-GaAs) to achieve photoconductive switches. The properties of these devices were then characterized. Thanks to the photon upconversion properties of these nanocrystals, the hybrid photoconductive switch exhibit an ON/OFF ratio more than 2-fold higher in decibels than the control device without nanocrystals applied. (ii) Field-effect transistor (FET)-based optoelectronic memories. In this field, the charge storage medium plays a critical role to the memory’s performance. In this part, I harnessed the unique charge-trapping and charge-retention properties of the above-mentioned colloidal nitrogen-doped (N-doped) CQDs to achieve functional optoelectronic memories programmable by UV illumination and with a multilevel writing possibility. In particular, a long-lasting memory function can be achieved thanks to the vast hole trapping sites provided by these CQDs and the resultant photo-gating effect excercised on the graphene FET, while memory erasing can be achieved via a positive gate bias that provides sufficient carriers for charge recombination. The result of this PhD thesis highlights the engineering and chemical controls to obtain high-performance optoelectronic devices such as microwave photoconductive switches and all-carbon non-volatile FET-based optoelectronic memories through manipulating and harvesting the optical and electronic properties of colloidal nanomaterials
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Almeida, Luciano Mendes. "Estudo de célula de memória dinâmica de apenas um transistor SOI de óxido enterrado ultrafino". Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18072013-144946/.
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Neste trabalho foi analisado o comportamento de um transistor UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo n, operando como uma célula de memória 1T-FBRAM (single transistor floating body random access memory). A memória em questão trata-se de uma evolução das memórias 1T1C-DRAM convencionais formada, porém, de apenas um transistor, sendo o próprio transistor o responsável pelo armazenamento da informação por meio do efeito de corpo flutuante. Assim, foram realizadas simulações numéricas bidimensionais, obtendo-se curvas dinâmicas e, a partir destas, foi possível extrair e analisar alguns dos principais parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Foram estudadas as polarizações da célula de memória. Dentre as possíveis maneiras de programação do dado 1 desta tecnologia foram abordadas neste trabalho a programação pelos métodos GIDL (Gate Induced Drain Leakage) e BJT (Bipolar Junction Transistor). Pelo método de escrita por GIDL foi possível operar a célula de memória em alta velocidade sem dissipar potência expressiva. Mostrou-se que esse método é bastante promissor para a tecnologia low-power high-speed. E ainda, obteve-se maior estabilidade na operação de leitura quando esta é polarizada no ponto ZTC (Zero Temperature-Coefficient) devido ao nível de corrente do dado 0 ficar estável mesmo com a variação da temperatura. Pelo método de escrita por BJT, estudou-se a influência das espessuras do filme de silício e também do óxido enterrado, notou-se uma forte dependência da tensão mínima de dreno para a programação do dado 1 em função destas espessuras e também em função da temperatura. Conforme a espessura do filme de silício torna-se mais fina, a tensão de disparo aplicada ao dreno aumenta devido ao maior acoplamento. Porém, observou-se que o nível da tensão de disparo do dreno pode ser modulada através da tensão aplicada ao substrato, tornando possível operar a célula em uma tensão de disparo menor aumentando a vida útil do dispositivo. Quanto à temperatura, com o seu aumento observou-se que a tensão mínima de dreno necessária para disparar a escrita do dado 1 diminuiu favorecendo a programação da célula. Porém o tempo de retenção é prejudicado (torna-se menor) por causa do aumento da corrente de fuga na junção PN. Na análise sobre o impacto que a primeira e a segunda porta causam na margem de sensibilidade de corrente e no tempo de retenção, verificou-se que dependendo da tensão aplicada à porta durante a condição de armazenamento do dado, o tempo de retenção pode ser limitado ou pela geração ou pela recombinação dos portadores (lacunas). Notou-se que há um compromisso entre a obtenção da melhor margem de sensibilidade de corrente e o melhor tempo de retenção. Como o tempo retenção é um parâmetro mais crítico, mais atenção foi dada para a otimização deste. Concluiu-se nesta análise que a melhor polarização para reter o dado por mais tempo é a primeira interface estar em modo acumulação e a segunda em modo depleção. No estudo da polarização de dreno durante a operação de leitura, observou-se que quando aplicado alta tensão de dreno é obtido alta margem de sensibilidade, porém ao mesmo tempo esta polarização prejudica o dado 0 devido ao alto nível de geração de lacunas induzidas pela ionização por impacto, o qual diminui o tempo de retenção e destrói o dado 0 quando operações de múltiplas leituras são realizadas. Já para baixo nível de tensão de dreno durante a leitura notou-se que é possível realizar múltiplas operações de leitura sem perder o dado armazenado e também maior tempo de retenção foi obtido.In this study was analyzed the behavior of one transistor called UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) working as a 1T-FBRAM (Single Transistor Floating Body Random Access Memory). This memory device is an evolution from conventional memories 1T1C-DRAM, however formed by only one transistor, the device itself is responsible for the storage of the information through the floating body effect. Thus two dimensional simulations were performed, where were obtained dynamic curves, and from these curves it was possible to extract and analyze some of the main parameters, such as, trigger drain voltage, sense margin current, read window, and the retention time, beyond the mechanisms in each state of memory (write, read and hold). Among the possible ways to program the data 1 in this technology were used the methods GIDL (Gate Induced Drain Leakage) and BJT (Bipolar Junction Transistor). By the GIDL method it was possible to operate the memory cell at high speed without spending significant power, showing that this method is very promising for low-power high-speed. Furthermore, greater stability was obtained in read operation when it is biased at point ZTC (zero-Temperature Coefficient) due to the current level of datum \'0\' remain stable even with temperature variation. By the BJT method, it was studied the influence of the silicon film thickness and the buried oxide thickness, and it was noted a strong dependence on minimum drain voltage for programming the data \'1\' as a function of both thicknesses. As the thickness of the silicon film becomes thinner, the trigger drain voltage increases due to stronger coupling. However, it was observed that the level of the trigger drain voltage can be modulated by the substrate bias in this way it is possible to operate the cell with lower voltage avoiding the damage and increasing the lifetime of the device. About the temperature, with its increase it was observed that the minimum drain voltage required to trigger the writing datum \'1\' decreased favoring the programming the cell. However the retention time is harmed (becomes smaller) due to the increment of leakage current in the PN junction. Analyzing the impact of the first and second gate on sense margin current and retention time, it was verified that depending on the voltage applied to the gate during the hold condition, the retention time may be limited by the generation or recombination of the carriers (holes). It was noted that there is a compromise between obtaining the best sense margin current and the best retention time. Since the retention is the most critical parameter, more attention should be given in order to obtain the optimization of this latter. It is concluded in this analysis that the best bias to retain the datum for longer time is the first interface being in accumulation mode and the second in depletion mode. In the study of biasing the drain during the read operation, it has been observed that the use of high drain voltage provides high sense margin, but at the same time, this polarization affect the data \'0\' due to high level of holes generation induced by impact ionization, which shortens the retention time and destroys the data \'0\' in multiple read operations. However, for low drain voltage during read operations it was possible to perform multiple read operations without losing the stored data and also higher retention time was obtained.
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Hilgers, Brandon. "SRAM Compiler For Automated Memory Layout Supporting Multiple Transistor Process Technologies". DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1423.
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This research details the design of an SRAM compiler for quickly creating SRAM blocks for Cal Poly integrated circuit (IC) designs. The compiler generates memory for two process technologies (IBM 180nm cmrf7sf and ON Semiconductor 600nm SCMOS) and requires a minimum number of specifications from the user for ease of use, while still offering the option to customize the performance for speed or area of the generated SRAM cell. By automatically creating SRAM arrays, the compiler saves the user time from having to layout and test memory and allows for quick updates and changes to a design. Memory compilers with various features already exist, but they have several disadvantages. Most memory compilers are expensive, usually only generate memory for one process technology, and don’t allow for user-defined custom SRAM cell optimizations. This free design makes it available for students and institutions that would not be able to afford an industry-made compiler. A compiler that offers multiple process technologies allows for more freedom to design in other processes if needed or desired. An attempt was made for this design to be modular for different process technologies so new processes could be added with ease; however, different process technologies have different DRC rules, making that option very difficult to attain. A customizable SRAM cell based on transistor sizing ratios allows for optimized designs in speed, area, or power, and for academic research. Even for an experienced designer, the layout of a single SRAM cell (1 bit) can take an hour. This command-line-based tool can draw a 1Kb SRAM block in seconds and a 1Mb SRAM block in about 15 minutes. In addition, this compiler also adds a manually laid out precharge circuit to each of the SRAM columns for an enhanced read operation by ensuring the bit lines have valid logic output values. Finally, an analysis on SRAM cell stability is done for creating a robust cell as the default design for the compiler. The default cell design is verified for stability during read and write operations, and has an area of 14.067 µm2 for the cmrf7sf process and 246.42 µm2 for the SCMOS process. All factors considered, this SRAM compiler design overcomes several of the drawbacks of other existing memory compilers.
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Sasaki, Kátia Regina Akemi. "Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI". Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-26072013-173443/.
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Neste trabalho foi analisado o comportamento de um transistor UTBOX FD SOI MOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo N, em sua aplicação como uma célula de memória 1T-DRAM, dando ênfase no estudo das polarizações e propostas de melhorias de desempenho para viabilizar sua aplicação como uma célula de memória. Dessa forma, foram analisados os efeitos das diferentes polarizações (de porta, de dreno e de substrato), bem como a influência da concentração de uma região de extensão de fonte e dreno menos dopada (LDD Lightly Doped Drain), nos principais parâmetros da referida memória. Assim, foram analisados alguns parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Por fim, foram propostas algumas melhorias de desempenho para o tempo de retenção. Foi observado que o aumento da temperatura facilita a escrita na memória diminuindo a mínima tensão no dreno (até 72% para temperatura de 25 a 300°C, ficando limitada a 0,8V) e o tempo necessários para a escrita (até 95%), porém reduz a margem de sensibilidade (até 90%) e o tempo de retenção (até 2 ordens de grandeza). Verificou-se também que, apesar da menor espessura do filme de silício e do óxido enterrado aumentar a tensão no dreno necessária para ativar o efeito BJT (efeito bipolar parasitário), um potencial positivo no substrato pode reduzir este requisito (61% para tensão de substrato variando de 0 V até 1,5 V). Além disso, foi visto que pode haver uma geração ou uma recombinação de portadores, dependendo da tensão na porta durante o repouso, degradando o bit \'0\' ou \'1\'. Já a otimização da polarização de substrato demonstrou ser limitada pelo compromisso de ser alta o suficiente para ativar o efeito de corpo flutuante durante a escrita, sem prejudicar a leitura do \'0\'. Os resultados também demonstraram que a margem de sensibilidade é menos dependente da tensão do substrato que o tempo de retenção, levando a este último parâmetro ser considerado mais crítico. Com relação à leitura, maiores tensões no dreno resultaram na presença do efeito BJT também neste estado, aumentando a margem de sensibilidade (60%) e diminuindo o tempo de retenção (66%) e o número de leituras possíveis sem atualização do dado (de mais de 30 para 22 leituras). No tópico da concentração das extensões de fonte e dreno, os dispositivos sem extensão de fonte e dreno apresentaram uma taxa de geração de lacunas menor (aproximadamente 12 ordens de grandeza), levando a um tempo de retenção muito maior (aproximadamente 3 ordens de grandeza) quando comparado ao dispositivo referência. Em seu estudo no escalamento, verificou-se uma diminuição no tempo de retenção para canais mais curtos (quase 2 ordens de grandeza), demonstrando ser um fator limitante para as futuras gerações das memórias 1T-DRAM. Apesar disso, quando comparados com os dispositivos convencionais com extensão de fonte e dreno (com extensão), seu tempo de retenção aumentou (quase 1 ordem de grandeza), permitindo a utilização de menores comprimentos de canal (30nm contra 50nm do dispositivo com extensão) e polarizações de substrato menores. Outra proposta de melhoria no tempo de retenção apresentada foi a utilização da polarização de substrato pulsada apenas durante a escrita do nível \'1\', o que resultou no aumento do tempo de retenção em 17%. Finalmente, estudou-se também a variação da banda proibida motivado pela utilização de novos materiais para o filme semicondutor. Observou-se que o aumento da banda proibida aumentou o tempo de retenção em até 5 ordens de grandeza, possibilitando retenções mais próximas das DRAMs convencionais atuais.In this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor), as a 1T-DRAM (Single Transistor Dynamic Random Access Memory) cell, focusing on the best biases and other proposals for enabling the 1T-DRAM applications. Therefore, it was analyzed the effects of different biases (gate, drain and substrate), as well as the influence of the concentration of a less doped source/drain extension region on the main parameters of this kind of memory. Thus, it was analyzed some of the main memory parameters such as the trigger drain voltage, the sense margin, the read window and the retention time, as well as the mechanisms operating in each state of the memory (writing, reading and holding). Finally, it were proposed some performance enhancements for the retention time of this kind of memory. It was observed that the increase in temperature facilitates the memory write decreasing the minimum drain bias and time required for writing, but reduces the sense margin. It was also verified that, despite the thinner silicon film and buried oxide increase the drain voltage required to activate the BJT effect (parasitic bipolar effect), a positive potential on the substrate may reduce this requirement (61% for back gate bias varying from 0 to 1,5V), being an alternative for solving the problem and allowing the use of smaller devices as a memory cell. Furthermore, it was seen that there can be a carriers generation or recombination, depending on the gate voltage during the holding state, degrading the bit \'0\' or \'1\'. Moreover, the optimization of substrate bias proved to be limited by enabling the writing state, without degrading the reading of \'0\'. The results also demonstrated the sense margin is less dependent on the substrate voltage than the retention time, therefore, the retention time was considered as a more critical parameter. With respect to the reading state, there was the presence of BJT effect also in this state, increasing the margin of sensitivity (60%) and reducing the retention time (66%) and the number of possible readings without updating the data (over 30 for 22 readings) in cases of higher drain bias. On the topic of the concentration of the source and drain extensions, the devices with source and drain extensions presented a generation rate lower (about 12 orders of magnitude), resulting in a retention time far longer than the reference one (about 3 orders of magnitude). About its downscaling, the retention time decreased for shorter channel lengths (almost 2 orders of magnitude), which is a limiting factor for 1T-DRAM future generations. Nevertheless, when it was compared to the conventional devices with source and drain extensions, theirs retention time increased (almost 1 order of magnitude), allowing the use of shorter channel lengths (30nm against 50nm of reference device) and lower back gate biases. Another proposal presented to improve the retention time was the pulsed back gate only during the writing \'1\' state, which resulted in an increase on the retention time by 17%. Finally, we also studied the band gap influence motivated by the use of new materials for the semiconductor film. It was observed that higher band gaps increase the retention time by up to 5 orders of magnitude, allowing a retention time closer to the current conventional DRAMs.
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Boubaker, Aimen. "Modelisation des composants mono-electroniques : Single-Electron Transistor et Single-Electron Memory". Lyon, INSA, 2010. http://theses.insa-lyon.fr/publication/2010ISAL0046/these.pdf.
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[Ce travail concerne le développement des mémoires à un électron de type SET/SEM pour les technologies CMOS silicium. Le premier chapitre du manuscrit est consacré à la présentation d' une revue bibliographique des phénomènes apparaissant dans les nanodispositifs électroniques (effets quantiques, blocage de Coulomb) de type transistors et mémoires à un électron. Dans le deuxième chapitre, nous nous intéressons aux diffë rents modèles électriques proposés pour les SETs. Grâce à des simulations numériques développées sous SPICE, nous avons approfondi notre compréhension du fonctionnement des SETs dans quelques exemples d'applications. Il s' agissait notamment de comparer les modèles dans le cas de SETs métalliques et semiconducteurs. Le troisième chapitre concerne la définition de l' architecture mémoire à un électron de type SET/SEM que nous proposons d'étudier. Après avoir présenté le concept de la structure SET/SEM, et expliqué le principe de fonctionnement dans les modes de lecture et de programmation, nous détaillons les résultats de simulations des caractéristiques du dispositif proposé. Après avoir opté pour une mémoire utilisant deux îlots métalliques pour les opérations de stockage de charge et de lecture respectivement, nous avons utilisé le logiciel SIMON afi n de proposer une architecture optimisée. Les travaux de simulations de l'architecture SET/SEM nous ont permis de calculer les éléments de circuits du modèle électrique équivalent permettant un fonctionnement optimal de la mémoire. Un aspect fondamental pour cette étude était en effet d'optimiser le décalage OVg des caractéristiques Ig-Vg observé lors de l' injection d'électrons uniques dans le point mémoire. Finalement, nous avons démontré qu'un décalage de quelques dizaines de m V/ électron était possible dans notre architecture. Dans le quatrième chapitre, nous présentons une étude détaillée des mécanismes de transport dans le bloc de mémorisation. Un modèle électrique de la cinétique de charge et décharge a été utilisé en prenant en compte l'effet du champ électrique. Finalement, nous avons étudié l' influence des paramètres technologiques comme les épaisseurs d'oxyde et la surface de l' îlot de mémorisation afin de proposer un dimensionnement de l'architecture SET/SEM. Ces simulations faites dans un premier temps à partir du système Ti / Tiüx utilisé dans la technologie nanodamascène développée à l'Université de Sherbrooke, ont pu dans un second temps être étendues à d'autres systèmes de matériaux afin de pro poser les matériaux présentant les meilleurs temps de rétention théoriques. Après avoir comparé les simulations d'îlots métalliques en Pt, Au, TiSi2, NiSi et Ti, nos travaux montrent que titane associé au Ti02 présente les meilleurs temps de rétention à 85% y compris à des températures aussi élevées que 430K qui représente actuellement la température maximale de fonctionnement des SETs réalisés à l'uni versité de Sherbrooke. ][This work concerns the study of SET/SEM single electron memories for CMOS technologies. The first part presents a review of quantum and Coulomb blockade effects in electronic nanodevices. In a second part, we present the main electrical models proposed for single electron devices. A comparison between semiconductor-based and metall ic-based single electron transistors. The third part of the thesis presents the SET/SEM memory structure on the basis of SIMON simulations. The device consists on the coupling of a metallic SET operating at high temperature with a metalli c memory node. Finnaly, an optimized memory device has been proposed in the Ti/Tiüx system. The proposed memory is able to write and erase a discrete number of electrons varying from 0 to 7 at room temperature. This opens the possibility of multilevel memory circuits. Finally, we have studied the data retenti on performances of the memory in the last part of this thesis. After the first simulations with the Ti/Tiüx materials system, we have simulated various metallic systems such as Pt, Au, TiSi2, and NiSi. We have shown that finally, the Ti/Ti02 systems gives the best data retention performances even at high temperatures, up to 430K. . ]
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CASULA, SILVIA. "Non-volatile organic memory devices: from design to applications". Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266601.
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The research activity described in the attached dissertation focused on the development, fabrication and characterization of new non-volatile memory elements based on organic technology. During the last few decades, organic materials based devices have attracted considerable interest due to their great potential for future electronic systems. Low fabrication costs, high mechanical flexibility and versatility of the chemical structure, good scalability and easy processing are the unique advantages of organic electronics. As memory devices are essential elements of any kind of electronic system, the development of organic memory devices is fundamental in order to extend the application of organic materials to different electronic circuits. Research on organic electronic memories is currently at a rapid growth stage, since it is recognized that they may be an alternative or supplementary to the conventional memory technologies. Despite considerable progress in the advancement of novel memory technologies in recent years, some challenging tasks still need to be resolved.
The Ph.D. research activity of this thesis is related to the still -opened challenges in the organic memories technologies. In particular, it focused mainly on the study, development, fabrication and characterization of new non-volatile organic memory elements based on resistive switching. The activity has been carried out in the frame of the European project “HYbrid organic/inorganic Memory Elements for integration of electronic and photonic Circuitry” (HYMEC), which involved the University of Cagliari during the last three years. The project goal was to realize new hybrid inorganic/organic resistive memory devices with functionality far beyond the state of the art. A complementary activity on transistor-based organic memory devices has been also carried out and described in this thesis.
As regards resistive memory devices, the research activity included design, fabrication and testing of a novel non-volatile memory device based on the combination of an air-stable organic semiconductor and metal nanoparticles. This topic required the development of technology and procedures for easy and reliable production of devices as well as the definition of measurement protocols. The proposed structure was thoroughly characterized by morphological techniques, which allowed to interpret the resistive switching mechanisms in terms of formation and rupture of metallic filaments inside the organic layer assisted by the metal NPs. The obtained performances are the best reported so far in literature, and, to our knowledge, the statistics analysis is the largest ever reported for organic-based resistive memories. The developed technology was then successfully applied on flexible plastic substrates. The definition of technological processes for the reliable fabrication of high performance printed organic memory devices was also carried out: this work clearly demonstrates the real possibility of fabricating high performance printed memory elements. A significant effort was also devoted to the development of basic memory/sensor systems entirely fabricated on plastic substrates. The suitability of organic non-volatile memory devices for the detection and the storage of external parameters was demonstrated. The results definitely demonstrated the feasibility of the proposed technology for the fabrication of systems including organic memories for their final application in different industrial processes, including e-textile and smart packaging.
As regards transistor memory devices, highly flexible Organic Field-Effect Transistor (OFET)-based memory elements with excellent mechanical stability and high retention time were developed. As main innovation with respect to the state of the art, low voltage operation of the OFET-based memory was investigated. Such an activity was also related to the development of reliable measurement procedures
Libros sobre el tema "Memory transistor"
1
Vagts, Christopher Bryan. A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory. Monterey, Calif: Naval Postgraduate School, 1992.
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2
Maeda, Shigenobu. Teishōhi denryoku kōsoku MOSFET gijutsu: Takesshō shirikon TFT fukagata SRAM to SOI debaisu. Tōkyō: Sipec, 2002.
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3
Vuillaume, D. Molecular electronics based on self-assembled monolayers. Editado por A. V. Narlikar y Y. Y. Fu. Oxford University Press, 2017. http://dx.doi.org/10.1093/oxfordhb/9780199533060.013.9.
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This article considers molecular electronics based on self-assembled monolayers. It begins with a brief overview of the nanofabrication of molecular devices, followed by a discussion of the electronic properties of several basic devices, from simple molecules such as molecular tunnel junctions and molecular semiconducting wires, to more complex ones such as molecular rectifying diodes. It also describes molecular switches and memories, focusing on three approaches called ‘conformational memory’, ‘charge-based memory’ and ‘RTD-based memory’ (RTD is resonant tunnelling diode). It shows that memory can be implemented from resonant tunnelling diodes following cell architecture already used for semiconductor devices. The article concludes with a review of molecular transistors.
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Launay, Jean-Pierre y Michel Verdaguer. The mastered electron: molecular electronics and spintronics, molecular machines. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198814597.003.0005.
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After a historical account of the evolution which led to the concept of Molecular Electronics, the “Hybrid Molecular Electronics” approach (that is, molecules connected to nanosized metallic electrodes) is discussed. The different types of transport (one-step, two-step with different forms of tunnelling) are described, including the case where the molecule is paramagnetic (Kondo resonance). Several molecular achievements are presented: wires, diodes, memory cells, field-effect transistors, switches, using molecules, but also carbon nanotubes. A spin-off result is the possibility of imaging Molecular Orbitals. The emerging field of molecular spintronics is presented. Besides hybrid devices, examples are given of electronic functionalities using ensembles of molecules, either in solution (logical functions) or in the solid state (memory elements). The relation with the domain of Quantum Computing is presented, including the particular domain of Quantum Hamiltonian Computing. The chapter finishes by an introduction to molecular machines, with the problem of the directional control of their motion.
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Forrest, Stephen R. Organic Electronics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198529729.001.0001.
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Organic electronics is a platform for very low cost and high performance optoelectronic and electronic devices that cover large areas, are lightweight, and can be both flexible and conformable to irregularly shaped surfaces such as foldable smart phones. Organics are at the core of the global organic light emitting device (OLED) display industry, and also having use in efficient lighting sources, solar cells, and thin film transistors useful in medical and a range of other sensing, memory and logic applications. This book introduces the theoretical foundations and practical realization of devices in organic electronics. It is a product of both one and two semester courses that have been taught over a period of more than two decades. The target audiences are students at all levels of graduate studies, highly motivated senior undergraduates, and practicing engineers and scientists. The book is divided into two sections. Part I, Foundations, lays down the fundamental principles of the field of organic electronics. It is assumed that the reader has an elementary knowledge of quantum mechanics, and electricity and magnetism. Background knowledge of organic chemistry is not required. Part II, Applications, focuses on organic electronic devices. It begins with a discussion of organic thin film deposition and patterning, followed by chapters on organic light emitters, detectors, and thin film transistors. The last chapter describes several devices and phenomena that are not covered in the previous chapters, since they lie outside of the current mainstream of the field, but are nevertheless important.
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Gang, Yung-jin. Ultra low voltage DRAM current sense amplifier with body bias techniques. 1998.
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7
Huster, Carl R. A parallel/vector Monte Carlo MESFET model for shared memory machines. 1992.
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8
Launay, Jean-Pierre y Michel Verdaguer. Electrons in Molecules. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198814597.001.0001.
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The book treats in a unified way electronic properties of molecules (magnetic, electrical, photophysical), culminating with the mastering of electrons, i.e. molecular electronics and spintronics and molecular machines. Chapter 1 recalls basic concepts. Chapter 2 describes the magnetic properties due to localized electrons. This includes phenomena such as spin cross-over, exchange interaction from dihydrogen to extended molecular magnetic systems, and magnetic anisotropy with single-molecule magnets. Chapter 3 is devoted to the electrical properties due to moving electrons. One considers first electron transfer in discrete molecular systems, in particular in mixed valence compounds. Then, extended molecular solids, in particular molecular conductors, are described by band theory. Special attention is paid to structural distortions (Peierls instability) and interelectronic repulsions in narrow-band systems. Chapter 4 treats photophysical properties, mainly electron transfer in the excited state and its applications to photodiodes, organic light emitting diodes, photovoltaic cells and water photolysis. Energy transfer is also treated. Photomagnetism (how a photonic excitation modifies magnetic properties) is introduced. Finally, Chapter 5 combines the previous knowledge for three advanced subjects: first molecular electronics in its hybrid form (molecules connected to electrodes acting as wires, diodes, memory elements, field-effect transistors) or in the quantum computation approach. Then, molecular spintronics, using, besides the charge, the spin of the electron. Finally the theme of molecular machines is presented, with the problem of the directionality control of their motion.
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Advanced Technologies for Next Generation Integrated Circuits. Institution of Engineering & Technology, 2020.
Buscar texto completoCapítulos de libros sobre el tema "Memory transistor"
1
Julien, Levisse Alexandre Sébastien, Xifan Tang y Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices". En Emerging Computing: From Devices to Systems, 47–83. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.
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AbstractSince the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (Faynot et al. 2010) transistors have therefore been proposed. All these solutions enabled Moore’s law scaling to continue. However, when approaching sub-10nm technology nodes, the story starts again. Again, process costs and electrical issues reduce the profitability of such solutions, and new technologies such as Gate-All-Around (GAA) (Sacchetto et al. 2009) transistors are seen as future FinFET replacement candidates.
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Li, Mengyao y Yating Zhang. "CHAPTER 17. Non-volatile Bipolar Transistor Memory". En Ambipolar Materials and Devices, 393–427. Cambridge: Royal Society of Chemistry, 2020. http://dx.doi.org/10.1039/9781788019279-00393.
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Sugahara, Satoshi, Yusuke Shuto y Shuu'ichirou Yamamoto. "Spin-Transistor Technology for Spintronics/CMOS Hybrid Logic Circuits and Systems". En Nanomagnetic and Spintronic Devices for Energy-Efficient Memory and Computing, 65–90. Chichester, UK: John Wiley & Sons, Ltd, 2016. http://dx.doi.org/10.1002/9781118869239.ch3.
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Li, Yiming, Chih-Hong Hwang y Shao-Ming Yu. "Numerical Simulation of Static Noise Margin for a Six-Transistor Static Random Access Memory Cell with 32nm Fin-Typed Field Effect Transistors". En Computational Science – ICCS 2007, 227–34. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-72590-9_33.
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Yamazato, Masaaki, Alexander M. Grishin, Yukihiko Yamagata, Tomoaki Ikegami, Kenji Ebihara y Jagdish Narayan. "Superconducting YBa2Cu3O7-x—Ferroelectric PbZr0.52Ti0.48O3 Heterostructures for a Field Effect Transistor and a Nonvolatile Memory Device". En Advances in Superconductivity XI, 1305–8. Tokyo: Springer Japan, 1999. http://dx.doi.org/10.1007/978-4-431-66874-9_306.
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Rawat, Bhawna y Poornima Mittal. "Impact of High-Performance Transistor on Performance of Static Random Access Memory for Low-Voltage Applications". En Proceedings of Second International Conference on Computational Electronics for Wireless Communications, 369–77. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_33.
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Bhowmik, Sonali y Surajit Bari. "Design and Delay Analysis of Column Decoder Using NMOS Transistor at Nano Level for Semiconductor Memory Application". En Computational Advancement in Communication Circuits and Systems, 383–88. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_42.
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Agrawal, Reeya y Sangeeta Singh. "IoT-Based Designing of Single Bit Six-Transistor Static Random Access Memory Cell Architecture for Industrial Applications". En Internet of Things, 171–94. Boca Raton: Chapman and Hall/CRC, 2023. http://dx.doi.org/10.1201/9781003226888-13.
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Monazzah, Amir Mahdi Hosseini, Amir M. Rahmani, Antonio Miele y Nikil Dutt. "Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories". En Dependable Embedded Systems, 505–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_21.
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AbstractDue to the consistent pressing quest of larger on-chip memories and caches of multicore and manycore architectures, Spin Transfer Torque Magnetic RAM (STT-MRAM or STT-RAM) has been proposed as a promising technology to replace classical SRAMs in near-future devices. Main advantages of STT-RAMs are a considerably higher transistor density and a negligible leakage power compared with SRAM technology. However, the drawback of this technology is the high probability of errors occurring especially in write operations. Such errors are asymmetric and transition-dependent, where 0 → 1 is the most critical one, and is high subjected to the amount and current (voltage) supplied to the memory during the write operation. As a consequence, STT-RAMs present an intrinsic trade-off between energy consumption vs. reliability that needs to be properly tuned w.r.t. the currently running application and its reliability requirement. This chapter proposes FlexRel, an energy-aware reliability improvement architectural scheme for STT-RAM cache memories. FlexRel considers a memory architecture provided with Error Correction Codes (ECCs) and a custom current regulator for the various cache ways and conducts a trade-off between reliability and energy consumption. FlexRel cache controller dynamically profiles the number of 0 → 1 transitions of each individual bit write operation in a cache block and based on that selects the most-suitable cache way and current level to guarantee the necessary error rate threshold (in terms of occurred write errors) while minimizing the energy consumption. We experimentally evaluated the efficiency of FlexRel against the most efficient uniform protection scheme from reliability, energy, area, and performance perspectives. Experimental simulations performed by using gem5 has demonstrated that while FlexRel satisfies the given error rate threshold, it delivers up to 13.2% energy saving. From the area footprint perspective, FlexRel delivers up to 7.9% cache ways’ area saving. Furthermore, the performance overhead of the FlexRel algorithm which changes the traffic patterns of the cache ways during the executions is 1.7%, on average.
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Song, Young Suh, Youngjae Song, T. S. Arun Samuel, P. Vimala, Shubham Tayal, Ritam Dutta, Chandan Kumar Pandey, Abhishek Kumar Upadhyay, Ilho Myeong y Shiromani Balmukund Rahi. "TFET-based Memory Cell Design with Top-Down Approach". En Tunneling Field Effect Transistors, 223–34. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-12.
Texto completoActas de conferencias sobre el tema "Memory transistor"
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Jung, Ilwoo, Byoungdeok Choi, Bonggu Sung, Daejung Kim, Ilgweon Kim, Hyoungsub Kim y Gyoyoung Jin. "Body Effect Measurement in DRAM Cell Transistor Using Memory Test System". En ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0085.
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Abstract Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.
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Poghosyan, Armen R., Ruben K. Hovsepyan, Natella R. Aghamalyan, Yevgenia A. Kafadaryan, Hovhannes L. Ayvazyan y Hrachya G. Mnatsakanyan. "One-transistor memory element". En Photonic Fiber and Crystal Devices: Advances in Materials and Innovations in Device Applications XVI, editado por Shizhuo Yin y Ruyan Guo. SPIE, 2022. http://dx.doi.org/10.1117/12.2632105.
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Pal, Ashish, Krishna C. Saraswat, Aneesh Nainani, Zhiyuan Ye, Xinyu Bao y Errol Sanchez. "GaP source-drain vertical transistor on bulk silicon for 1-transistor DRAM application". En 2013 5th IEEE International Memory Workshop (IMW). IEEE, 2013. http://dx.doi.org/10.1109/imw.2013.6582132.
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Feng, Daohuan, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, Jaewoo Kim, Jian Chu et al. "Vertical Channel Transistor (VCT) as Access Transistor for Future 4F2 DRAM Architecture". En 2023 IEEE International Memory Workshop (IMW). IEEE, 2023. http://dx.doi.org/10.1109/imw56887.2023.10145977.
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Martins, R., L. Pereira, P. Barquinha, N. Correia, G. Gonçalves, I. Ferreira, C. Dias y E. Fortunato. "Floating gate memory paper transistor". En OPTO, editado por Ferechteh H. Teherani, David C. Look, Cole W. Litton y David J. Rogers. SPIE, 2010. http://dx.doi.org/10.1117/12.841036.
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Ruprecht, Michael W., Shengmin Wen y Rolf-P. Vollertsen. "Sample Preparation for Vertical Transistors in DRAM". En ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0307.
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Abstract This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) milling and selective wet chemical etching to expose both gates of the transistor simultaneously. Gate oxide pinholes are decorated by the wet etch to allow efficient inspection in a secondary electron microscope (SEM).
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Colvin, Jim B. y Anirban Roy. "Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor". En ISTFA 2000. ASM International, 2000. http://dx.doi.org/10.31399/asm.cp.istfa2000p0247.
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Abstract Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.
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Qian, Kun y Costas J. Spanos. "45nm transistor variability study for memory characterization". En SPIE Advanced Lithography, editado por Michael L. Rieger y Joerg Thiele. SPIE, 2010. http://dx.doi.org/10.1117/12.846704.
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Sharif, Kazi Fatima, Riazul Islam, Satyendra N. Biswas y Voicu Groza. "4 Transistor and 2 memristor based memory". En 2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE). IEEE, 2017. http://dx.doi.org/10.1109/iscaie.2017.8074946.
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Govli, Rishabh, Vivek Dixit y Bibhu Datta Sahoo. "1-Transistor-1-Memristor Multilevel Memory Cell". En 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018. http://dx.doi.org/10.1109/mwscas.2018.8624071.
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