Literatura académica sobre el tema "Low power high-speed links"
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Artículos de revistas sobre el tema "Low power high-speed links"
Statkus, Arūnas, Šarūnas Paulikas y Audrius Krukonis. "TCP Acknowledgment Optimization in Low Power and Embedded Devices". Electronics 10, n.º 6 (10 de marzo de 2021): 639. http://dx.doi.org/10.3390/electronics10060639.
Texto completoKhitrov, Andrei y Alexander Khitrov. "Electrical subsystem of the low-power cogeneration plant with low-speed vehicle". Environment. Technology. Resources. Proceedings of the International Scientific and Practical Conference 2 (8 de agosto de 2015): 119. http://dx.doi.org/10.17770/etr2013vol2.852.
Texto completoAli, Luqman Sufer y Asmaa Salim Mayoof. "Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed". Tikrit Journal of Engineering Sciences 23, n.º 2 (31 de mayo de 2016): 96–102. http://dx.doi.org/10.25130/tjes.23.2.11.
Texto completoLyashenko, Yu y A. Prudiy. "RESEARCH INTO THE IMPACT OF ROAD POWER ENERGY SYSTEM MECHANICAL CONVERTER LINKS MOTION ON GENERATOR OPERATION". Bulletin of the South Ural State University series "Power Engineering" 21, n.º 3 (2021): 41–48. http://dx.doi.org/10.14529/power210305.
Texto completoTraversi, G., S. Bonacini, F. De Canio, L. Gaioni, K. Kloukinas, M. Manghisoni, L. Ratti y V. Re. "Design of low-power, low-voltage, differential I/O links for High Energy Physics applications". Journal of Instrumentation 10, n.º 01 (29 de enero de 2015): C01055. http://dx.doi.org/10.1088/1748-0221/10/01/c01055.
Texto completoAyachi, Riadh, Ayoub Mhaouch y Abdessalem Ben Abdelali. "Lightweight Cryptography for Network-on-Chip Data Encryption". Security and Communication Networks 2021 (19 de mayo de 2021): 1–10. http://dx.doi.org/10.1155/2021/9943713.
Texto completoQu, Zhi Jian y Li Liu. "Real-Time Database System Implementation of Railway Signal Power Source Remote Monitoring". Applied Mechanics and Materials 128-129 (octubre de 2011): 961–64. http://dx.doi.org/10.4028/www.scientific.net/amm.128-129.961.
Texto completoChrisey, Douglas B. y Arun Inam. "Pulsed Laser Deposition of High Tc Superconducting Thin Films for Electronic Device Applications". MRS Bulletin 17, n.º 2 (febrero de 1992): 37–43. http://dx.doi.org/10.1557/s0883769400040604.
Texto completoUlusoy, Ahmet Çağrı, Gang Liu, Andreas Trasser y Hermann Schumacher. "Hardware efficient receiver for low-cost ultra-high rate 60 GHz wireless communications". International Journal of Microwave and Wireless Technologies 3, n.º 2 (3 de marzo de 2011): 121–29. http://dx.doi.org/10.1017/s1759078711000110.
Texto completoOphir, Noam, Christopher Mineo, David Mountain y Keren Bergman. "Silicon Photonic Microring Links for High-Bandwidth-Density, Low-Power Chip I/O". IEEE Micro 33, n.º 1 (enero de 2013): 54–67. http://dx.doi.org/10.1109/mm.2013.1.
Texto completoTesis sobre el tema "Low power high-speed links"
Fang, Yuan [Verfasser], Klaus [Akademischer Betreuer] Hofmann, Franko [Akademischer Betreuer] Küppers, Marius [Akademischer Betreuer] Pesavento, Christian [Akademischer Betreuer] Hochberger y Gersem Herbert [Akademischer Betreuer] De. "PHY Link Design and Optimization For High-Speed Low-Power Communication Systems / Yuan Fang. Betreuer: Klaus Hofmann ; Franko Küppers ; Marius Pesavento ; Christian Hochberger ; Herbert De Gersem". Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2015. http://d-nb.info/1111112444/34.
Texto completoSaadallah, Nisrine. "High-speed low-power asynchronous circuits". Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.
Texto completoIn Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.
Ibrahim, Sameh Ahmed Assem Mostafa. "High-speed low-power equalizers for high-loss channels". Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=2026920921&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
Texto completoJiang, Hao. "High-power, high-speed p-i-n- photodiodes for analog fiber optic links /". Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2000. http://wwwlib.umi.com/cr/ucsd/fullcit?p9970665.
Texto completoNho, Hyunwoo. "A high-speed, low-power 3D-SRAM architecture /". May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Texto completoZheng, Shijie M. Eng Massachusetts Institute of Technology. "A low cost asynchronous eye diagram reconstruction system for high speed links". Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85233.
Texto completoThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 97-98).
As link communication data rate increases, there is an increasing need for a more cost eective way to test and monitor signal integrity in link communication systems. Specifically, eye diagrams are valuable visual aids to analyze and quantify digital signal quality. This thesis presents a novel low cost eye diagram reconstruction system using asynchronous undersampling technique, which solves a key problem in performance monitoring in systems where synchronous sampling is not available, such as video switches. Existing works are studied and compared to this work in performance and cost. The proposed system is designed as a system-on-chip (SOC) and contains an undersampling ADC, aliased frequency estimator and a simple reconstruction algorithm. Major building blocks are implemented and simulated in 65nm CMOS process. Extensive system level analysis and simulations demonstrate functionality and performance of the system working at 10Gb/s maximum data rate.
by Shijie Zheng.
M. Eng.
Wolfe, Kurt A. "Radiation tolerant, high speed, low power gallium arsenide logic". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA277293.
Texto completoZargaran, Yazd Arash. "Design techniques for high-speed low-power wireline receivers". Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44660.
Texto completoSafi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters". Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.
Texto completoThe first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
Avadhanam, Karthik. "A new high speed low power Dynamic Programmable Logic Array /". Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1453188921&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Texto completoLibros sobre el tema "Low power high-speed links"
Cao, Zhiheng y Shouli Yan. Low-Power High-Speed ADCs for Nanometer CMOS Integration. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8450-8.
Texto completoCao, Zhiheng. Low-Power High-Speed ADCs for Nanometer CMOS Integration. Dordrecht: Springer Science + Business Media B.V, 2008.
Buscar texto completoLi, Weitao, Fule Li y Zhihua Wang. High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-62012-1.
Texto completoMargarit, Josep Maria. Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49962-8.
Texto completoArmin, Kemna y Hosticka Bedrich J, eds. Modular low-power, high-speed CMOS analog-to-digital converter of embedded systems. Boston: Kluwer Academic Publishers, 2003.
Buscar texto completoShehata, Khaled Ali. Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes. Monterey, Calif: Naval Postgraduate School, 1996.
Buscar texto completoRoermund, Arthur H. M. van., Casier Herman y Steyaert Michiel 1959-, eds. Analog circuit design: High-speed A-D converters, automotive electronics, and ultra-low power wireless. Dordrecht, Netherlands: Springer, 2006.
Buscar texto completoUnited States. Congress. Senate. Committee on Commerce, Science, and Transportation. Subcommittee on Communications. S. 2454, wireless high speed internet access for rural areas: Hearing before the Subcommittee on Communications of the Committee on Commerce, Science, and Technology, United States Senate, One Hundred Sixth Congress, second session, June 14, 2000. Washington: U.S. G.P.O., 2003.
Buscar texto completoRaabe, Oliver. Der öffentlich-rechtliche Primärrechtschutz gegen Höchstspannungsfreileitungen am Beispiel der Rechtslage in Schleswig-Holstein, Baden-Württemberg und Bayern. Kiel: [s.n.], 2000.
Buscar texto completoVirginia. Dept. of Transportation. Report of the Virginia Department of Transportation on a study of the Overhead High Voltage Line Safety Act to the Governor and the General Assembly of Virginia. Richmond: Commonwealth of Virginia, 1995.
Buscar texto completoCapítulos de libros sobre el tema "Low power high-speed links"
Fujishima, Minoru. "Ultimate High-Speed Wireless Link". En Low Power Circuit Design Using Advanced CMOS Technology, 363–444. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338772-5.
Texto completoKnudsen, Magne. "Changing Tides: Temporal Dimensions of Low-Cost, High-Skill Fisheries in the Central Visayas, Philippines". En Case Studies in Biocultural Diversity from Southeast Asia, 21–42. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6719-0_2.
Texto completoHatai, Indranil y Indrajit Chakrabarti. "A High-Speed Low-Power Low-Latency Pipelined ROM-Less DDFS". En Communications in Computer and Information Science, 108–19. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17881-8_11.
Texto completoBeerel, Peter A. "Asynchronous Design for High-Speed and Low-Power Circuits". En Lecture Notes in Computer Science, 669. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_66.
Texto completoTigelaar, Howard. "Engineering MOS Transistors for High Speed and Low Power". En How Transistor Area Shrank by 1 Million Fold, 51–66. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_4.
Texto completoKabra, Naveen Kumar y Zuber M. Patel. "Low-Power and High-Speed Configurable Arithmetic and Logic Unit". En Lecture Notes in Networks and Systems, 355–63. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3765-9_37.
Texto completoOudjida, Abdelkrim K., Nicolas Chaillet, Ahmed Liacha, Mustapha Hamerlain y Mohamed L. Berrandjia. "High-Speed and Low-Power PID Structures for Embedded Applications". En Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 257–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-24154-3_26.
Texto completoDimitrakopoulos, G., P. Kolovos, P. Kalogerakis y D. Nikolos. "Design of High-Speed Low-Power Parallel-Prefix VLSI Adders". En Lecture Notes in Computer Science, 248–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_27.
Texto completoKumar, K. J. y A. Raganna. "Implementation of Low-Power High-Speed Clock and Data Recovery". En Cognitive Informatics and Soft Computing, 333–46. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1056-1_27.
Texto completoGao, Yuan, Jin Yong Xu, Yan Ping Liu, Zhi Yong He y Zhong Xu. "A New Low Alloy High Speed Power Hack Saw Blades". En Materials Science Forum, 3939–42. Stafa: Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-960-1.3939.
Texto completoActas de conferencias sobre el tema "Low power high-speed links"
Thomson, David J., Kapil Debnath, Weiwei Zhang, Ke Li, Shenghao Liu, Fanfan Meng, Ali Z. Khokhar et al. "Towards High Speed and Low Power Silicon Photonic Data Links". En 2018 20th International Conference on Transparent Optical Networks (ICTON). IEEE, 2018. http://dx.doi.org/10.1109/icton.2018.8473598.
Texto completoZhang, Hao, Hiroki Matsutani, Michihiro Koibuchi y Hideharu Amano. "Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links". En IEEE Symposium on Low-Power and High-Speed Chips. 2013 COOL Chips XVI. IEEE, 2013. http://dx.doi.org/10.1109/coolchips.2013.6547924.
Texto completoMelikyan, Vazgen, Arthur Sahakyan, Arsen Hekimyan, Davit Trdatyan, Aram Shishmanyan y Tigran Khazhakyan. "Low power duty cycle adjustment simple method in high speed serial links". En 2015 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2015. http://dx.doi.org/10.1109/ewdts.2015.7493157.
Texto completoChangqing Xu, Yi Liu y Yintang Yang. "High-speed, low-power transmitter based on charge redistribution for NoC links". En 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2016. http://dx.doi.org/10.1109/icsict.2016.7998881.
Texto completoDuquennoy, Simon, Fredrik Österlind y Adam Dunkels. "Lossy links, low power, high throughput". En the 9th ACM Conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2070942.2070945.
Texto completoShekhar, S., J. E. Jaussi, F. O'Mahony, M. Mansuri y B. Casper. "Design considerations for low-power receiver front-end in high-speed data links". En 2013 IEEE Custom Integrated Circuits Conference - CICC 2013. IEEE, 2013. http://dx.doi.org/10.1109/cicc.2013.6658406.
Texto completoZamarreno-Ramos, Carlos, Teresa Serrano-Gotarredona, Bernabe Linares-Barranco, Raghavendra Kulkarni y Jose Silva-Martinez. "Voltage mode driver for low power transmission of high speed serial AER Links". En 2011 IEEE International Symposium on Circuits and Systems. IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5938095.
Texto completoAyesh, Mostafa M., Sameh A. Ibrahim, Hani F. Ragai y Mohamed M. Rizk. "A low-power high-speed charge-steering ADC-based equalizer for serial links". En 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2015. http://dx.doi.org/10.1109/icecs.2015.7440360.
Texto completoNagula, Suresh, Patri Sreehari Rao y Ekta Goel. "Adaptively Biased Low dropout regulator with High Power Supply Rejection for High speed serial Links". En 2022 IEEE International Symposium on Smart Electronic Systems (iSES). IEEE, 2022. http://dx.doi.org/10.1109/ises54909.2022.00070.
Texto completoHou, Zhongyuan, Fan Yang, Junhua Liu, Huailin Liao y Xing Zhang. "A low power and wide frequency range CMOS signal detector for high speed data links". En 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6466700.
Texto completoInformes sobre el tema "Low power high-speed links"
Lawrence, William R. Nanomechanical Devices for High Speed and Low-Power Electronics. Fort Belvoir, VA: Defense Technical Information Center, junio de 2001. http://dx.doi.org/10.21236/ada394851.
Texto completoParhi, Keshab K. High-Speed and Low-Power VLSI Error Control Coders. Fort Belvoir, VA: Defense Technical Information Center, septiembre de 2004. http://dx.doi.org/10.21236/ada426960.
Texto completoWaks, Edo, Sangbok Lee, Nader Engheta y Benjamin Shapiro. Metatronics for Ultra-High-Speed Low-Power Nano-Circuits. Fort Belvoir, VA: Defense Technical Information Center, diciembre de 2011. http://dx.doi.org/10.21236/ada585948.
Texto completoWang, Wen I. InAs HVT for Extremely Low Power and High Speed Applications. Fort Belvoir, VA: Defense Technical Information Center, julio de 2005. http://dx.doi.org/10.21236/ada438567.
Texto completoDagenais, M. High Speed, Low Power Non-Linear Optical Signal Processing in Semiconductors. Fort Belvoir, VA: Defense Technical Information Center, junio de 1985. http://dx.doi.org/10.21236/ada159054.
Texto completoCrosbie, R. E., J. J. Zenor, R. Bednar, D. Word y N. G. Hingorani. Low-Cost High-Speed Techniques for Real-Time Simulation of Power Electronic Systems. Fort Belvoir, VA: Defense Technical Information Center, junio de 2007. http://dx.doi.org/10.21236/ada485330.
Texto completoBrice, Jeremy. Investment, power and protein in sub-Saharan Africa. Editado por Tara Garnett. TABLE, octubre de 2022. http://dx.doi.org/10.56661/d8817170.
Texto completoAnalysis of Recompression-Regeneration sCO 2 Combined Cycle Utilizing Marine Gas Turbine Exhaust Heat: Effect of Operating Parameters. SAE International, julio de 2022. http://dx.doi.org/10.4271/2022-01-5059.
Texto completoL52074 Investigation of Mixing and Scavenging in Large Bore (Natural Gas) Engines using Laser Diagnostics. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), enero de 2003. http://dx.doi.org/10.55274/r0011345.
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