Tesis sobre el tema "Integrated mixers"

The growing demand for submillimetre wave (SMW ) circuits is spurred not only by the needs of traditional science applications such as radio astronomy and atmospheric remote sensing but also by military and commercial applications such as compact range radar. Several approaches to device and circuit fabrication have been developed and in the past 20 years, many successful SM W components have been built for operation up to THz frequencies. However, they all suffer one or more drawback, such as low reliability and repeatability, lengthy and difficult assembly and reliance on mechanical tuners. The first part of the work described here has been the development of high yield, high quality and high repeatability antiparallel Schottky diodes entirely fabricated at the University of Bath. After producing Schottky diodes having state of the art characteristics, the main focus of the research was the development of a process to monolithically integrate the anti-parallel Schottky diode in a 200 GHz RF mixer circuit. Throughout this research, advantage has been taken of the recent development of advanced computer aided design tools that are suitable for simulating both linear and nonlinear parts of the submillimetre mixer to design and fabricated a fixed-tuned integrated mixer at 183 GHz.

Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos.
This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz.

This thesis is based on a paper by V. Issakov, presented 2009, where a circuit of a merged power amplifier mixer solution was demonstrated. This work takes that solution and simplifies it for the use at a lower frequency. The implementation target is a Doppler radar application in CMOS that can detect humans in a range of 5 to 15 meters. This could be used as a burglar alarm or an automatic light switch. The report will present the background of Issakov’s work, basic theory used and the implementation of the final design. Simulations will show that the solution presented work, with a 15 dB conversion loss. This design performs well compared to reference mixers. With this report it will be shown that it is possible to make a simple and compact Doppler radar system in CMOS.
Denna avhandling bygger på en artikel av V. Issakov, presenterad 2009, där en lösning för att sammanslå en effektförstärkare med en mixer till en krets visades. Detta arbete tar denna lösning och förenklar det för användning vid en lägre frekvens. Målet är att implementera en dopplerradar i CMOS som kan detektera människor inom ett avstånd på 5 till 15 meter. Denna radar skulle kunna användas som ett inbrottslarm eller en automatisk strömbrytare. Rapporten kommer att presentera bakgrunden från Issakov’s arbete, grundläggande teori som används och genomförandet av det slutliga kretsschemat. Simuleringar visar att den presenterade lösningen fungerar, med en 15 dB konverteringsförlust. Denna konstruktion presterar väl jämfört med referens mixrar. Med denna rapport visas det att det är möjligt att göra ett enkelt och kompakt dopplerradarsystem i CMOS.

L’électrochimie directe des protéines (PFE) est une technique dans laquelle une enzyme est adsorbée à une électrode et son activité catalytique est mesurée sous forme d’un courant électrique, ce qui permet l’étude de la cinétique d’enzyme en fonction de différents paramètres expérimentaux. Cette technique nécessite un transport rapide du substrat vers l’électrode. Dans une étude précédente, notre équipe a proposé une nouvelle cellule électrochimique offrant un transport supérieur à l’électrode tournante, couramment utilisée dans les méthodes PFE. Dans cette thèse, nous avons exploré, à l’aide de CFD, l’effet des différents paramètres et proposé des formules semi-empiriques pour prédire les propriétés de transport dans la cellule. Puis, nous avons validé expérimentalement nos prédictions. En outre, nous avons construit un nouveau type de cellule avec des mélangeurs intégrés qui devraient permettre des changements rapides de concentrations
Protein Film Electrochemistry (PFE) is a technique in which an enzyme is adsorbed at an electrode and its catalytic turnover rate is measured as an electrical current which allows the investigation of enzyme’s kinetics as a function of different experimental parameters. However, this technique requires fast transport of the substrate towards the electrode. In a previous study, our team proposed a new design based on the wall-tube electrode that provides better transport than the rotating disc electrode, which is commonly used in PFE methods. In this thesis, we explored, using CFD, the effect of the various parameters of the design and proposed semi-empirical formulas to predict the mass transport coefficient and shear stress at the electrode. We used a 3D-printed cell to validate experimentally our predictions. Moreover, we designed and built a new type of wall-tube electrodes with integrated mixers that should allow faster changes of substrate and inhibitor’s concentrations

Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).

In this thesis, the principles of mixing ECL and CMOS technologies have been investigated with the intention of increasing the operating speed of synchronous systems. To achieve this, the design will be primarily CMOS based with the critical path implemented in ECL to reduce the delay and hence improve the execution time. Logic conversion circuitry between the two technologies has been designed, with the CMOS-ECL conversion circuit being a simple enhancement of the basic ECL current switch and ECL-CMOS translation being achieved with 0.5ns using a "double inverter circuit". To reduce the power dissipation of the ECL circuitry, a power control circuit has been incorporated which enables the ECL circuitry when the critical path is required and disables it, to save power, when the instructions to be evaluated are non critical. To further reduce the power consumption of the ECL circuitry and decrease the execution time, a BiCMOS active pull down circuit has been added. The active pull down circuit replaces the resistor in the traditional emitter follower configuration, reducing the power loss and matching the gate fall time to the rise time. A mixed ECL and CMOS technology ripple adder, utilising all of these features, has been designed and simulated using HSPIC. The inputs to be added are from CMOS registers and the output sum is returned to CMOS registers but within the circuit, the carry ripple is implemented in ECL. The performance is comparable with an ECL adder whilst using less than a third of the power and with larger, more complex systems, the mixed technology concept is estimated to actually be faster than ECL.

Récemment, les coûts faramineux d'une usine de fabrication de semi-conducteurs ont contraint de nombreuses entreprises à renoncer à avoir leur usine en propre. En externalisant la fabrication de CI/PI à des sociétés tierces, le procédé de fabrication a été confié à des sociétés potentiellement peu fiables. Il en résulte des menaces de sécurité pour l'industrie des semi-conducteurs, telles que la contrefaçon, la rétro-ingénierie et l'insertion de HT. Dans cette thèse, nous proposons une contre-mesure anti-piratage pour protéger les CI/PI AMS, une nouvelle attaque HT pour les CI/PI AMS et une nouvelle PUF. La technique anti-piratage que nous proposons est basée sur le verrouillage des circuits analogiques configurables. Notre technique exploite le mécanisme de configuration du circuit pour y introduire une fonction verrouillage. Nous présentons son implémentation et ses capacités de résilience contre les attaques. L'attaque HT proposée pour les circuits analogiques exploite l'infrastructure de test. Le HT est introduit dans le sous-système numérique du système AMS et transfère sa charge utile au circuit analogique via le bus de test. Le HT est invisible dans le domaine analogique. Le HT est montré sur deux études de cas. Cette thèse montre l'importance de nouvelles contre-mesures de sécurité et de confiance adaptées aux CI analogiques. La fonction PUF proposée utilise un neurone à impulsions comme source d'entropie. Sa caractéristique principale est de n'utiliser qu'une seule cellule PUF et une redondance temporelle pour générer une clé arbitrairement longue, ce qui réduit les coûts additionnels en surface et en énergie par rapport aux fonctions PUF traditionnelles
Recently, the enormous cost of owning and maintaining a modern semiconductor manufacturing plant has coerced many companies to go fabless. By outsourcing the manufacturing IC/IP to third-party and often off-shore companies, the process has been extended to potentially untrustworthy companies. This has resulted in several security threats to the semiconductor industry such as counterfeiting, reverse engineering, and HTs insertion. In this thesis, we propose an anti-piracy countermeasure to protect AMS ICs/IPs, a novel HT attack for AMS ICs/IPs, and a novel PUF. More specifically, we propose an anti-piracy technique based on locking for programmable analog circuits. The proposed technique leverages the programmability fabric to implement a natural lock-less locking. We discuss its implementation and its resilience capabilities against foreseen attacks. The proposed HT attack for analog circuits leverages the test infrastructure. The HT is hidden effectively in a digital core and transfers its payload to the analog circuit via the test bus and the interface of the analog circuit to the test bus. Its key characteristic is that it is invisible in the analog domain. The proposed HT is demonstrated on two case studies. This thesis sheds light on the importance of developing new security and trust countermeasures tailored for analog circuits. The proposed PUF, called "neuron-PUF", uses a single spiking neuron as the source of entropy. Its key characteristic is that it uses a single PUF cell and temporal redundancy to generate an arbitrarily long key, which results in significant low area and power overheads compared to mainstream PUFs, such as delay-based and memory-based PUFs

Thesis (M.S. in soil science)--Washington State University, December 2008.
Title from PDF title page (viewed on June 15, 2009). "Department of Crop and Soil Science." Includes bibliographical references.

In this modern age of information, the demands on data transmission networks for greater capacity, and mobile accessibility are increasing drastically. The increasing demand for mobile access is evidenced by the proliferation of wireless systems such as mobile phone networks and wireless local area networks (WLANs). The frequency range over which an oxygen resonance occurs in the atmosphere (~58-62 GHz) has received recent attention as a possible candidate for secure high-speed wireless data networks with a potentially high degree of frequency reuse. A significant challenge in implementing data networks at 60 GHz is the manufacture of low-cost RF transceivers capable of satisfying the system requirements. In order to produce transceivers that meet the additional demands of high-volume, mobility, and compactness, monolithic millimeter wave integrated circuits (MMICs) offer the most practical solution. In the design of radio tranceivers with a high degree of integration, the receiver front-end is typically the most critical component to overall system performance. High-performance low-noise amplifiers (LNAs) are now realizable at frequencies in excess of 100 GHz, and a wide variety of mixer topologies are available that are capable of downconversion from 60 GHz. However, local oscillators (LOs) capable of providing adequate output power at mm-wave frequencies remain bulky and expensive. There are several techniques that allow the use of a lower frequency microwave LO to achieve the same RF downconversion. One of these is to employ a subharmonic mixer. In this case, a lower frequency LO is applied and the RF mixes with a harmonic multiple of the LO signal to produce the desired intermediate frequency (IF). The work presented in this thesis will focus on the development of a GaAs MMIC 4-X subharmonic mixer in Finite Ground Coplanar (FGC) technology for operation at 60 GHz. The mixer topology is based on an antiparallel Schottky diode pair. A discussion of the mechanisms behind the operation of this circuit and the methods of practical implementation is presented. The FGC transmission lines and passive tuning structures used in mixer implementation are characterized with full-wave electromagnetic simulation software and 2-port vector network analyzer measurements. A characterization of mixer performance is obtained through simulations and measurement. The viability of this circuit as an alternative to other high-frequency downconversion schemes is discussed. The performance of the actual fabricated MMIC is presented and compared to currently available 60 GHz mixers. One particular MMIC design exhibits an 11.3 dB conversion loss at an RF of 58.5 GHz, an LO frequency of 14.0 GHz, and an IF of 2.5 GHz. This represents excellent performance for a 4X Schottky diode mixer at these frequencies. Finally, recommendations toward future research directions in this area are made.
Master of Science

Specialty chemicals industry relies on batch manufacturing, since it requires the frequent adaptation of production systems to market fluctuations. To be first in the market, batch industry requires decision-support systems for the rapid development and implementation of chemical processes. Moreover, the processes should be competitive to ensure their long-term viability. General-purpose and flexible plants and the consideration of physicochemical insights to define an efficient operation are also cornerstones for the success of specialty chemical industries. Precisely, this thesis tackles the systematic development of batch processes that are efficient, economically competitive, and environmentally friendly, to assist their agile introduction into production systems in grassroots and retrofit scenarios. Synthesis of conceptual processing schemes and plant allocation subproblems are solved simultaneously, taking into account the plant design. With this purpose, an optimization-based approach is proposed, where all structural alternatives are represented in a State-Equipment Network (SEN) superstructure, following formulated into a Mixed-Logic Dynamic Optimization (MLDO) problem which is later solved to minimize an objective function. Essentially, the strength of the proposed methodology lies in the modeling strategy which combines the different kinds of decisions of the integrated problem in a unique optimization model. Accordingly, it considers: (i) synthesis and allocation alternatives combination, (ii) dynamic process performance models and dynamic control variable profiles, (iii) discrete events associated to transitions of batch phases and operations, (iv) quantitative and qualitative information, (v) material transference synchronization to ensure batch integrity between unit procedures, and (vi) batch and semicontinuous processing elements. Different strategies can be used to solve the resulting MLDO problem. A deterministic direct-simultaneous approach is first proposed. The mixed-logic problem is reformulated into a mixed-integer one, which is fully-discretized to provide a Mixed-Integer Non-Linear Programming (MINLP) that is optimized using conventional solvers. Then, a Differential Genetic Algorithm (DGA) and a hybrid approach are presented. The purpose of these evolutionary strategies is to pose solution alternatives that keep solution goodness while seek for the improvement of computational efficiency to handle industrial-size problems. The optimization-based approach is applied in retrofit scenarios to solve the simultaneous process synthesis and plant allocation, taking into account the physical restrictions of existing plant elements. The production of specialty chemicals based on a competitive reactions system in an existing reactor network is first defined through process development and improvement according to different economic scenarios, decision criteria, and plant modifications. Additionally, a photo-Fenton process is optimized to eliminate an emergent wastewater pollutant in a given pilot plant, pursuing the minimization of processing time and cost. Batch process development in grassroots scenarios is also proven to be a problem of utmost importance to deal with uncertainty in future markets. Seeking for plant flexibility in several demand scenarios, the expected profit is maximized through a two-stage stochastic formulation that includes simultaneous plant design, process synthesis, and plant allocation decisions. A heuristic solution algorithm is used to handle the problem complexity. A grassroots plant design is defined to implement the previous competitive reaction system, where decisions like the feed-forward trajectories or operating modes allow the adaptation of master recipes to different demands. Finally, an acrylic fiber production example is presented to illustrate process development decisions like the selection of tasks, technological alternatives, chemicals, and solvent reuse.
La indústria de productes químics especials es basa en la fabricació discontinua, ja que permet adaptar de forma freqüent els sistemes de producció en funció de les fluctuacions de mercat. Per ser líder al sector, són necessàries eines de suport a la decisió que ajudin a l’àgil desenvolupament i implementació de nous processos. A més, aquests han de ser competitius per garantir la seva viabilitat a llarg termini. Altres peces clau per una operació eficient són l’ús de plantes flexibles així com l’estudi dels fenòmens fisicoquímics. Aquesta tesis aborda justament el desenvolupament sistemàtic de processos químics discontinus que siguin eficients, econòmicament competitius i ecològics, per contribuir a la seva ràpida introducció en els sistemes de producció, tant en escenaris de plantes existents com des de les bases. En concret, es planteja la resolució simultània de la síntesi conceptual d’esquemes de procés i l’assignació d’equips, tenint en compte el disseny de la planta. Amb aquest objectiu, es proposa una metodologia de solució basada en optimització, on les alternatives estructurals es representen en una Xarxa d’Estats i Equips (SEN per les sigles en anglès) que es formula mitjançant un problema d’Optimització Dinàmica Mixta-Lògica (MLDO per les sigles en anglès) que es resol minimitzant una funció objectiu. La solidesa de la metodologia proposada rau en la estratègia de modelat del problema MLDO, que integra els diferents tipus de decisions en un sol model d’optimització. En concret, es consideren: (i) la combinació d’alternatives de síntesi i assignació d’equips, (ii) models de procés i trajectòries de control dinàmics, (iii) esdeveniments discrets associats al canvi de fase i operació, (iv) informació quantitativa i qualitativa, (v) sincronització de transferències de material en tasques consecutives, i (vi) elements de processat discontinus i semi-continus. Existeixen diverses estratègies per resoldre el problema MLDO resultant. En aquesta tesi es proposa en primer lloc un mètode determinístic directe-simultani, on el model mixt-lògic es transforma en un mixt-enter. Aquest es discretitza al seu torn de forma completa per obtenir un problema de Programació No-Lineal Mixta-Entera (MINLP per les sigles en anglès) el qual es pot resoldre utilitzant algoritmes d’optimització convencionals. A més, es presenten un Algoritme Genètic Diferencial (DGA per les sigles en anglès) i un mètode híbrid. Totes dues estratègies esdevenen alternatives de cerca amb l’objectiu de mantenir la bondat de la solució i millorar l’eficàcia de computació per tractar problemes de dimensió industrial. La metodologia de solució proposada s’aplica al desenvolupament de processos discontinus en escenaris de plantes existents, tenint en compte les restriccions físiques dels equips. Un primer exemple aborda la manufactura de productes químics basada en un sistema de reaccions competitives. Concretament, es desenvolupa i millora el procés de producció implementat en una xarxa de reactors considerant diferents escenaris econòmics, criteris de decisió, i modificacions de planta. En un segon exemple, s’optimitza el procés foto-Fenton per ser executat en una planta pilot per eliminar contaminants emergents. Buscant integrar el desenvolupament de procés i el disseny de plantes flexibles en escenaris de base, es presenta una formulació estocàstica en dues etapes per a optimitzar el benefici esperat d’acord a diversos escenaris de demanda. Per gestionar la complexitat d’aquest problema es proposa la utilització d’una heurística. Com a exemple, es planteja el disseny d’una planta de base on implementar l’anterior sistema de reaccions competitives. Decisions com les trajectòries dinàmiques de control o la configuració d’equips permeten adaptar la recepta màster en funció de la demanda. Un darrer exemple defineix el procés de producció de fibra acrílica, il·lustrant decisions com la selecció de tasques, tecnologia, reactius o reutilització de dissolvents.
La industria productos químicos especiales se basa en la fabricación discontinua, la cual permite la adaptación frecuente de los sistemas de producción en función de las fluctuaciones de mercado. Para ser líder en el sector, son necesarias herramientas de soporte a la decisión que contribuyan al ágil desarrollo e implementación de nuevos procesos. Además, éstos deben ser competitivos para garantizar su viabilidad a largo plazo. Otras piezas clave para una operación eficiente son la utilización de plantas flexibles y el estudio de los fenómenos fisicoquímicos. Esta tesis aborda justamente el desarrollo sistemático de procesos químicos discontinuos que sean eficientes, económicamente competitivos y ecológicos, para contribuir a su rápida introducción en los sistemas de producción, ya sea en escenarios de plantas existentes o desde las bases. En particular, se plantea la resoluciónsimultánea de la síntesis conceptual de esquemas de proceso y la asignación de equipos, teniendo en cuenta además el diseño de planta.Con este fin, se propone una metodología de solución basada en optimización, donde todas las alternativas estructurales se representan en una Red de Estados y Equipos (SENpor sus siglas en inglés) que se formula mediante un problema de Optimización Dinámica Mixta-Lógica (MLDO por sus siglas en inglés) que se resuelve minimizando una función objetivo. La solidez de la metodología propuesta reside en la estrategia de modelado delproblema MLDO, que integra los diferentes tipos de decisiones en un solo modelo de optimización. En concreto, se consideran: (i) la combinación de alternativas de síntesis y asignación de equipos, (ii) modelos de proceso y trayectorias de control dinámicos, (iii)eventos discretos asociados al cambio de fase y operación, (iv) información cuantitativa y cualitativa, (v) sincronización de la transferencia de material en tareas consecutivas, y(vi) elementos de procesado discontinuos y semicontinuos.Existen diversas estrategias para resolver el problema MLDO resultante. En esta tesis se propone en primer lugar un método determinístico directo-simultáneo, donde el problema mixto-lógico se reformula en un mixto-entero. A su vez, éste se discretiza de formacompleta para obtener un problema de Programación No-Lineal Mixta-Entera (MINLP por sus siglas en inglés) el cual se puede resolver mediante algoritmos de optimización convencionales. Además, se presentan un Algoritmo Genético Diferencial (DGA por sussiglas en inglés) y un método híbrido. Ambas estrategias se plantean como alternativas de búsqueda con objeto de mantener la bondad de la solución y mejorar la eficacia de computación para tratar problemas de dimensión industrial.La metodología de solución propuesta se aplica al desarrollo de procesos discontinuos en escenarios con plantas existentes, teniendo en cuenta las restricciones físicas de los equipos. Un primer ejemplo aborda la fabricación de productos químicos basada en un sistema de reacciones competitivas. En concreto, se desarrolla y mejora el proceso de producción a implementar en una red de reactores considerando diferentes escenarios económicos, criterios de decisión, y modificaciones de planta. En un segundo ejemplo,se optimiza el proceso foto-Fenton a ser ejecutado en una planta piloto para eliminar contaminantes emergentes.Persiguiendo la integración del desarrollo de proceso con el diseño de plantas flexi-bles en escenarios base, se presenta asimismo una formulación estocástica en dos etapas para optimizar el beneficio esperado de acuerdo a varios escenarios de demanda. Paramanejar la complejidad de dicho problema se propone la utilización de una heurística.Como ejemplo, se plantea el diseño de una planta de base para implementar el anterior sistema de reacciones competitivas, donde decisiones como las trayectorias dinámicas de control o la configuración de equipos permiten adaptar la receta máster en función de lademandas. Por último, se presenta un ejemplo donde se define el proceso de producción de fibra acrílica, ilustrando decisiones como la selección de tareas, alternativas tecnológicas, reactivos químicos o la reutilización de disolventes.

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Bachelors
Engineering
Electrical Engineering

The objective of this research is to design and implement low-noise wideband RFIC components with CMOS technology for the direct-conversion architecture. This research proposes noise reduction techniques to improve the thermal noise and flicker noise contribution of a low noise amplifier (LNA) and a mixer. Of these techniques, the LNA is found to reduce noise, boost gain, and consume a relatively low amount of power without sacrificing the wideband and linearity advantages of a conventional common gate (CG) topology. The research concludes by investigating the proposed mixer topology, which senses and compensates local oscillator (LO) phase mismatches, the dominant cause of flicker noise.

Reliable high-temperature analog and mixed-signal CMOS circuits are required for several applications including aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In particular, in this work we focus on the design of key building blocks of a miniature sensor interface system that is intended to operate in a pulp and paper digester and collect and record sensory data such as pressure and temperature along its trajectory within the digester. The temperature inside the digester can be as high as 180℃. Design considerations and techniques for implementing these building blocks both at component- and circuit-levels are presented. At the component level, techniques for designing monolithic resistors with a desired temperature coefficient (TC) are proposed, and an analysis on the effects of design parameters such as resistor length, width and the number of fingers on the TC of such multi-finger resistor structures is presented. Furthermore, since the foundry-provided transistor models are typically valid up to 125℃, various NMOS and PMOS transistors with diff erent sizes are implemented to study their behaviour at high temperature. Based on our observations, a suitable sizing for transistors is suggested for circuits operating up to 200℃. At the circuit-level, several key building blocks such as bias circuits, voltage references and oscillators are designed and proof-of-concept prototypes are implemented in a standard 0.13 ㎛ CMOS process. The operation of the circuits is experimentally validated over the temperature range of interest, namely, 25 to 200℃. Also, a low-complexity resistive and capacitive temperature-compensation techniques for high-temperature relaxation oscillators is proposed. Although the temperature stability of the proposed oscillator (108 ppm/℃) compares favourably with that of state-of-the-art designs, it occupies 0.007 mm² which is 2.3 to 114 times smaller than other comparable designs. Also, the proposed circuit operates reliably up to 200℃ (as compared to 125℃ in other designs). Although the proposed techniques are only validated using proof-of-concept prototypes in a 0.13 ㎛ CMOS technology, they are general and our preliminary studies on several technologies indicate that the techniques can be implemented in other CMOS technologies as well.

Master of Science
Department of Electrical Engineering
William B. Kuhn
Designers of mixed-signal systems must understand coupling mechanisms at the system, PC board, package and integrated circuit levels to control crosstalk, and thereby minimize degradation of system performance. This research examines coupling mechanisms in a RF-targeted high-resistivity partially-depleted Silicon-on-Insulator (SOI) IC process and applying similar coupling mitigation strategies from higher levels of design, proposes techniques to reduce coupling between sub-circuits on-chip. A series of test structures was fabricated with the goal of understanding and reducing the electric and magnetic field coupling at frequencies up to C-Band. Electric field coupling through the active-layer and substrate of the SOI wafer is compared for a variety of isolation methods including use of deep-trench surrounds, blocking channel-stopper implant, blocking metal-fill layers and using substrate contact guard-rings. Magnetic coupling is examined for on-chip inductors utilizing counter-winding techniques, using metal shields above noisy circuits, and through the relationship between separation and the coupling coefficient. Finally, coupling between bond pads employing the most effective electric field isolation strategies is examined. Lumped element circuit models are developed to show how different coupling mitigation strategies perform. Major conclusions relative to substrate coupling are 1) substrates with resistivity 1 kΩ·cm or greater act largely as a high-K insulators at sufficiently high frequency, 2) compared to capacitive coupling paths through the substrate, coupling through metal-fill has little effect and 3) the use of substrate contact guard-rings in multi-ground domain designs can result in significant coupling between domains if proper isolation strategies such as the use of deep-trench surrounds are not employed. The electric field coupling, in general, is strongly dependent on the impedance of the active-layer and frequency, with isolation exceeding 80 dB below 100 MHz and relatively high coupling values of 40 dB or more at upper S-band frequencies, depending on the geometries and mitigation strategy used. Magnetic coupling was found to be a strong function of circuit separation and the height of metal shields above the circuits. Finally, bond pads utilizing substrate contact guard-rings resulted in the highest degree of isolation and the lowest pad load capacitance of the methods tested.

A passive mixer is designed in a silicon germine process for use in a 5GHz WLAN receiver. The design is implemented as a fully on-chip design and copackage design with passive components integrated on the substrate in the package. Also for each implementation the performance is evaluated with twelve different bonding inductances, from 50pH to 2nH. To estimate connection parasitic floorplans have been made for normal wirebonding and solderbumps for each of the implementation. The performance parameters compared are conversion gain, noise close to signal, noise with high frequency offset to the signal and IIP3. Some performance differences can be found between different implementations but neither of the implementations can be consider superior to the other.

In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components.

Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach.

The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.

L'acoblament de soroll a través del substrat en circuits integrats mixtos és un important problema que sovint limita les prestacions de la circuiteria analògica. Les característiques d'aquest tipus d'acoblament i els factors que en determinen la importància no són ben compresos, així que calen criteris per tal de triar les millor accions per a resoldre el problema. En els darrers anys s'han proposat algunes tècniques per reduir el soroll de substrat, tot i que no hi ha una idea clara de l'abast de la seva validesa, i de les condicions que calen per a la seva eficàcia. La majoria de l'esforç de recerca que s'ha dedicat a aquest tema s'ha centrat en el desenvolupament de models, que permetin la incorporació del substrat en les eines CAD que s'utilitzen en les fases de simulació dels dissenys. Per tant, aquests resultats de recerca no contribueixen a la comprensió dels aspectes rellevants de l'acoblament.

En aquesta tesi doctoral s'ha realitzat un estudi analític i experimental que ha permès determinar les característiques tecnolòiques i de disseny que faciliten l'acoblament vers la circuiteria analògica. S'ha partit d'una caracterització de l'acoblament mitjançant un simulador de dispositius, on s'ha pogut comprovar la importància d'aspectes com el tipus de substrat, la velocitat de commutació dels dispositius, les seves dimensions, o el punt de polarització. La caracterització s'ha realitzat tant per tecnologies CMOS com BiCMOS, i ha estat completada amb mesures sobre estructures de test. Posteriorment s'ha portat a terme un anàlisi de la propagació del soroll en el substrat, amb el que s'han esbrinat les característiques tecnològiques i de polartizació que determinen l'atenuació del soroll. L'anàlisis'ha realizat suposant condicions de polarització ideals, i ha permès determinar el potencial d'algunes mesures per a la minimització de l'acoblament. A continuació s'ha fet una revisió de les diverses tècniques de modelació del substrat, i utilitzant algun dels models s'han pogut realitzar simulacions circuitals per a estudiar l'acoblament en circuits de dimensions realistes, tenint en compte factors com els elements paràsits dels terminals de l'encapsulat, la influència dels pads, o l'estratègia de polarització. Aquest estudi s'ha complementat amb el disseny d'un circuit mixte de test sobre el que s'han fet mesures per a verificar els resultats obtinguts, i corroborar els mecanismes que determinen l'acoblament. La tesi s'ha completat amb una revisió de l'eficàcia d'algunes tècniques específiques per a la reducció del soroll, i amb un estudi de l'evolució en tecnologies futures tant del soroll de commutació a les línies d'alimentació, com del soroll acoblat a través del substrat.
El acoplo de perturbaciones a través del sustrato de silicio en circuitos integrados mixtos representa un importante problema que a menudo limita las prestaciones de la circuiteria analógica. Hay una cierta incomprensión de las características del acoplo i de los factotres que que determinan su importancia, de forma que faltan criterios para implementar técnicas que reduzcan el problema. En los últimos años se han propuesto diversas técnicas para la reducción del ruido de sustrato, aunque no estan claros su rango de validez y las condiciones que se deben cumplir para su eficacia. La mayor parte del esfuerzo investigador realizado en este campo se ha centrado en el desarrollo de modelos que faciliten la incorporación del sustrato a las herramientas CAD utilizadas en la fase de simulación de un circuito. Por tanto, esta investigación no ofrece aportaciones en la comprensión de los aspectos relevantes del fenómeno.

En esta tesis doctoral se ha realilzado un estudio analítico y experimental que ha permitido determinar las características tecnológicas y de diseño que facilitan el acoplo sobre la circuitería analógica. Se ha partido de una caracterización del acoplamiento mediante un simulador de dispositivos, donde se ha podido comprovar la importancia de aspectos como el tipo de sustrato, la velocidad de conmutación de los dispositivos, sus dimensiones, o el punto de polarización. La caracterización se ha realizado tanto para estructuras CMOS como BiCMOS, y ha sido completada con medidas sobre estructuras de test. Posteriomente se ha llevado a cabo un análisis de la propagación del ruido en el sustrato, con el que se han determinado las características tecnológicas y de polarización que determinan la atenuación del ruido. El análisis se ha realizado suponiendo condiciones de polarización ideales, y ha permitido determinar el potencial de algunas medidas para la minimización del acoplo. A continuación se ha realizado una revisión de las diversas técnicas de modelación del sustrato, y utilizando alguno de los modelos se han podido realizar simulaciones circuitales para estudiar el acoplo en circuitos de dimensiones realistas, teniendo en cuenta factores como los elementos parásitos de los terminales del encapsulado, la influencia de los pads, o la estrategia de polarización. Este estudio se ha complementado con el diseño de un circuito mixto de test sobre el que se han hecho medidas para verificar los resultados obtenidos, y corroborar los mecanismos que determinan el acoplo. La tesi se ha completado con una revisión de la eficacia de algunas técnicas específicas para la reducción del ruido, y con un estudio de la evolución en tecnologías futuras tanto del ruido de conmutación a través de las líneas de alimentación, como del ruido acoplado a través del sustrato.
Noise coupling through common silicon substrate in mixed-signal circuits is an important problem that often limits the performance of the analog circuitry. The characteristics of this type of coupling and the factors determining its importance are not well understood, so criteria to choose the best actions to solve the problem are needed. Several techniques to reduce substrate noise have been proposed in the last years, although there is no clear idea about their range of validity, and the conditions required for their efficacy. Most of the research effort done in this field has been centered on the development of models, in order to allow the incorporation of substrate in the CAD tools used in simulation design stages. Thus, these research results do not contribute to the understanding of the relevant aspects of coupling.

In this thesis an analytic and experimental study has been done, which has allowed determining the technological and design characteristics relevant in the coupling. The study has started with a characterisation of coupling using a device simulator, which has allowed determining the importance of aspects such as substrate type, device switching speed, device dimensions, or their biasing. Characterisation has been done both for CMOS and BiCMOS technologies, and it has been completed with measurements on test structures. Next an analysis of noise propagation through the substrate has been carried out, which has allowed to find out the biasing and technological characteristics that determine noise attenuation. The analysis has been done assuming ideal biasing conditions, and the potentiality of some noise minimisation measures could be determined. Next a review of the different substrate modelling techniques has been done, and some of the models have been used to perform circuit simulations to study coupling in circuits of some complexity, taking into account factors such as package pins parasitics, the influence of the ring of pads, or the biasing strategy. This study has been complemented with the design and measurements of a mixed-signal test circuit, which allowed verification of the results previously obtained, and the coupling mechanism. Finally the thesis is completed with a review of the efficacy of noise-reducing specific techniques, and with the study of the trends of switching noise on power supply lines and substrate for near future technologies.

Wireless sensor nodes are emerging in a wide range of critical applications such as environmental monitoring, health applications, home automation and military surveillance and reconnaissance. The addition of low power wireless capability to such sensor nodes allows communication between a node and a base station or between nodes, resulting in the formation of wireless sensor networks. Sensor networks can use the information available from the distributed sensor nodes to determine the location and nature of a stimulus or environmental condition. The information collected by the base station can be used to determine the appropriate course of action for dealing with the stimulus. In chemical/biological defense or safety monitoring scenarios, wireless sensor networks can be used to identify and track harmful chemical or biological agents which might be present in a particular area. Due to the potentially remote areas that wireless sensor networks aim to cover, it is essential to minimize the power consumption of a sensor node so that it can operate over a long period of time without a connection to the power grid. Sensor nodes can contain multiple blocks, such as the readout circuit which interfaces with the sensor, an embedded processor, and the wireless transceiver circuits, all of which need to operate on a low power budget. This thesis specifically focuses on design of low power mixed signal readout circuits which interface with chemoresistive chemical sensors, i.e. sensors that demonstrate a variation of resistance (or impedance) in the presence of chemical agents. For this thesis, the sensor can be either a chemoresistive bead or a nanowire. By integrating multiple non-specific chemoresistive sensors together in arrays, a cross-reactive array can be realized, where the combined response of the arrayed sensors can be used to determine analytes present in a mixture even if their concentrations are low. In this thesis, a CMOS resistive readout circuit based on a sigma-delta ADC is presented. The design is used to measure the resistance of chemoresistive beads and nanowires with respect to time. The frequency of the ADC output varies as the resistance of a sensor changes and, based on the magnitude and duration of the variation, the type of chemical agent and its concentration can potentially be estimated. For future cross-reactive sensor applications, an array of 16x16 sites is also included in the readout circuit design. Individual sites in the sensor array can be accessed using addressing blocks which designed to select a particular row and column using an 8-bit addressing system. This thesis also covers the techniques used for integration of chemoresistive beads and nanowires into the array locations provided on the prefabricated CMOS IC. Measurement results that demonstrate the operation of the resistive readout circuitry are presented. Finally, a second readout circuit is proposed to measure complex impedance variations of a sensor device. Measurement of magnitude and phase changes of a sensor device can provide another degree of freedom in the analysis of chemical mixture. Simulation results demonstrating the functionality of the proposed impedance measurement system are also presented.
Master of Science

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.

The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems. A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed. The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.

Among the existing corrosion control methods, surfactant inhibitors have widely been used for corrosion inhibition of pipelines in water-oil-steel pipe (WOS) environments. This dissertation includes a systemic review of the causes of pipeline corrosion in WOS environments containing carbon dioxide (CO2), general corrosion control using surfactant inhibitors and associated concerns, and commonly used classes of surfactants and their properties, various processes and phenomena that affect overall surfactant performance. This dissertation also provides a review of experimental evaluation techniques and various developed models (semi-empirical model, mechanistic model, and multiphysics model) in evaluation of surfactant inhibition efficiency. An integrated corrosion inhibition (ICI) model is proposed, developed, and validated based on the current understanding of the inhibition of CO2 corrosion in WOS environments using surfactants. The developed ICI model for the modeling and prediction of corrosion inhibition efficiency of mixed surfactant inhibitors is a multiphysics model, based on the fundamentals from many areas of corrosion science, electrochemistry, metallurgical engineering, and chemical and analytical engineering, etc., and the integration of several submodels, including a water-oil surfactant distribution submodel, the aqueous cmc prediction submodel, and the modified Langmuir adsorption (MLA)/ modified quantitative structure activity relation (MQSAR) submodel. Software is developed based on the ICI model and the use of computational and programming resources. The phenomena and processes integrated into the ICI model include surfactant partitioning between oil and water, micellization and precipitation, adsorption/desorption at surfaces and interfaces, surfactant-solvent interactions, surfactant-counterion pairing, lateral interactions between surfactant molecules, and fluid flow. These phenomena are incorporated into three main processes and associated modeling: partitioning between oil and water, micellization/precipitation, and effective adsorption on metal substrate and water/oil interface. The framework of multiphysics ICI model is intended to serve as a basic framework in the understanding of mixed surfactant inhibitor performance with a focus on the application in salt-containing WOS environments. Beyond this, other potential applications may be extended to the design of surfactants, selection of optimal surfactants for specific applications, experimental validation of developed models, simulation of conceivable processes and phenomena, and the integration into more comprehensive lifetime prediction models in which all the surfactant efficiency-affecting factors may be evaluated.

With the growing energy consumption in the world today, the decreasing amount of fossil fuels and their negative impact on the environment, developments and greater use of renewable energy resources is crucial. One of the promising environmentally friendly energy resources is solar power. The technology for producing electricity from the use of solar cells is continuously developing and is growing on the market. The objective of this master thesis is to illustrate how solar panels can be integrated into a building’s design, and what value this gives to the building. The purpose is also to give an indication of whether an integrated solar panel installation is profitable, and what is required for more building developers to invest in solar power. A study on solar cells was conducted to gain knowledge of the different types of solar cells and systems and their possible integration into buildings. The study also included research on why solar cell installations are not more common today. Case Studies were also conducted on projects with integrated solar cells. This was done to gain an understanding of how solar panels can be used as design elements. The study was done as a systematic literature study through a qualitative method. City and site analyses were carried out as a first step in the design process. The analyses focused on the movements, green spaces, climates, functions and architectural character of the city and site. The analyses were done to attain an impression of the environment the building would be placed in, and its requisites. These analyses were followed by volume and solar studies to come up with a building design that would fulfill the requirements of the client, while creating good areas for placement of the solar panels. The master thesis resulted in a design proposal for a mixed-use building with integrated solar cells. The resulting two buildings are located in the outskirts of the city center of Linköping. The buildings are designed to interact with the surrounding buildings and the remaining city, while at the same time bringing something new and exciting to the mix. The buildings’ placement and height were decided by the combination of the movement of the sun over the plot, so as to create good areas for the solar panels, and the requisites of the site. The integrated solar panels are placed on the roofs and facades of the buildings. The possibilities of semitransparent solar cells in windows and glass railings is also examined. The solar panels on the roof consist of solar roof tiles and are placed on the east side of the north building’s roof and the west side of the south building’s roof. These tiles have matching roof tiles without solar cells inside, on the other side of the roofs, meaning that no difference can be seen between the two sides. The façade panels are placed to cover the entire protruding stairwells of the buildings. Panels are also placed on remaining parts of the south-east and south-west facing facades but are here placed in a pattern as though they are trickling down the walls. The panels are placed to avoid shade as shading of the panels reduces their effect. The solar cells are smooth, black, thin-film solar cells and the panels have matching glass panes that are placed were the design opted for panels, but the placement was not good out of a solar irradiation perspective. The results of the rough calculations on the project’s solar panel installation’s profitability shows that the investment would have a payback time of approximately 15 years. This, when counting in a government support of 1.2 million kroners and the reduced cost for the building cover material that the solar panels replace. The solar panels in the design proposal are not in standard sizes. Would they have been so the investment cost would have been lower and the payback time, according to the rough calculations, would be around 10 years. The produced electricity constitutes around 60 percent of the operational electricity for the buildings. If semitransparent solar cells are included the value goes up to 80 percent. Although the produced electricity does not cover the complete electricity needs of the buildings, it still reduces the amount of bought electricity. Electricity that would most likely not come from a renewable source. The conclusion is, therefore, that an integrated solar cell installation is economically profitable. The solar panels contribute both the aesthetics of the building and building functions, as well as electricity from a renewable source. Investing in a solar cell installation also sets a good example and will lead to more investors taking a chance on solar power. Getting more building developers to invest in solar cells systems can be done by increasing the, today lacking, knowledge of solar energy and solar cells, the process for designing and installing a solar cell system, as well as the laws regarding solar power and solar power investments. Another obstacle for solar power is the high costs of the installations. The prices on solar cells are, however, continuously dropping, because of the development in technology and the manufacturing process, as well as the growing number of manufacturers. To increase the speed of this process more building developers should invest in solar cells, as a higher demand will lead to more manufacturers, which will then lead to reduced prices. The government can also help by offering research support and for example tax subventions to make an investment in solar power seem more worthwhile.