Artículos de revistas sobre el tema "Integrated circuits Very large scale integration"
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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M y Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits". ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
Texto completoPatel, Ambresh y Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits". SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, n.º 01 (30 de enero de 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
Texto completoIwai, Hiroshi, Kuniyuki Kakushima y Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING". International Journal of High Speed Electronics and Systems 16, n.º 01 (marzo de 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.
Texto completoMadhura, S. "A Review on Low Power VLSI Design Models in Various Circuits". Journal of Electronics and Informatics 4, n.º 2 (8 de julio de 2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
Texto completoIm, James S. y Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays". MRS Bulletin 21, n.º 3 (marzo de 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
Texto completoBeck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit y Andreas Richter. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration". Micromachines 11, n.º 5 (2 de mayo de 2020): 479. http://dx.doi.org/10.3390/mi11050479.
Texto completoLi, Jian, Robert Blewer y J. W. Mayer. "Copper-Based Metallization for ULSI Applications". MRS Bulletin 18, n.º 6 (junio de 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
Texto completoDove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS". Journal of Microelectronics and Electronic Packaging 6, n.º 1 (1 de enero de 2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
Texto completoWong, C. P. "An Overview of Integrated Circuit Device Encapsulants". Journal of Electronic Packaging 111, n.º 2 (1 de junio de 1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
Texto completoBoychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky y Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices". Facta universitatis - series: Electronics and Energetics 28, n.º 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
Texto completoIKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, HUADONG GAN, KATSUYA MIURA, KOTARO MIZUNUMA, SHUN KANAI et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI". SPIN 02, n.º 03 (septiembre de 2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
Texto completoSun, Chongjun y Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits". Journal of Physics: Conference Series 2029, n.º 1 (1 de septiembre de 2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.
Texto completoRajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics". Journal of Circuits, Systems and Computers 27, n.º 13 (3 de agosto de 2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
Texto completoMurarka, S. P., J. Steigerwald y R. J. Gutmann. "Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing". MRS Bulletin 18, n.º 6 (junio de 1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.
Texto completoChen, Xiangyu, Takeaki Yajima, Isao H. Inoue y Tetsuya Iizuka. "An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks". Japanese Journal of Applied Physics 61, SC (18 de febrero de 2022): SC1051. http://dx.doi.org/10.35848/1347-4065/ac43e4.
Texto completoChowdary, M. Kalpana, Rajasekhar Turaka, Bayan Alabduallah, Mudassir Khan, J. Chinna Babu y Ajmeera Kiran. "Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques". Processes 11, n.º 8 (8 de agosto de 2023): 2389. http://dx.doi.org/10.3390/pr11082389.
Texto completoZhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method". Advanced Materials Research 490-495 (marzo de 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
Texto completoLuo, Guozheng, Xiang Chen y Shanshan Nong. "Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning". Journal of Physics: Conference Series 2245, n.º 1 (1 de abril de 2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.
Texto completoJayakumar, Ganesh, Per-Erik Hellström y Mikael Östling. "Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application". Micromachines 9, n.º 11 (25 de octubre de 2018): 544. http://dx.doi.org/10.3390/mi9110544.
Texto completoLi, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng y Kai Huang. "Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology". Applied Sciences 13, n.º 6 (8 de marzo de 2023): 3471. http://dx.doi.org/10.3390/app13063471.
Texto completoNagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar y Swathi K. "Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module". International Journal of Electrical and Electronics Research 10, n.º 4 (30 de diciembre de 2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.
Texto completoZhu, Ziran, Zhipeng Huang, Jianli Chen y Longkun Guo. "Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles". Complexity 2021 (14 de abril de 2021): 1–12. http://dx.doi.org/10.1155/2021/8843271.
Texto completoMOHANA KANNAN, LOGANATHAN y DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION". DYNA 96, n.º 5 (1 de septiembre de 2021): 505–11. http://dx.doi.org/10.6036/10214.
Texto completoN., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors". Revista Gestão Inovação e Tecnologias 11, n.º 2 (5 de junio de 2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
Texto completoCheng, Yi Lung, Yi Shiung Lu y Tai Jung Chiu. "Comparative Study of Low Dielectric Constant Material Deposited Using Different Precursors". Advanced Materials Research 233-235 (mayo de 2011): 2480–85. http://dx.doi.org/10.4028/www.scientific.net/amr.233-235.2480.
Texto completoAhmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi y Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test". International Journal of Advanced Natural Sciences and Engineering Researches 7, n.º 6 (13 de julio de 2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
Texto completoRasheed, Israa Mohammed y Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms". Bulletin of Electrical Engineering and Informatics 12, n.º 1 (1 de febrero de 2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.
Texto completoNIRANJAN, VANDANA, ASHWANI KUMAR y SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS". Journal of Circuits, Systems and Computers 23, n.º 08 (18 de junio de 2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
Texto completoSun, Ben. "Interpretable machine learning in VLSI physical design". Applied and Computational Engineering 4, n.º 1 (14 de junio de 2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.
Texto completoEppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil y R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications". i-manager's Journal on Digital Signal Processing 11, n.º 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.
Texto completoSoref, Richard. "Applications of Silicon-Based Optoelectronics". MRS Bulletin 23, n.º 4 (abril de 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.
Texto completoNAKADA, KAZUKI, TETSUYA ASAI y HATSUO HAYASHI. "ANALOG VLSI IMPLEMENTATION OF RESONATE-AND-FIRE NEURON". International Journal of Neural Systems 16, n.º 06 (diciembre de 2006): 445–56. http://dx.doi.org/10.1142/s0129065706000846.
Texto completoShanavas, I. Hameem y R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm". Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.
Texto completoSanadhya, Minakshi, Devendra Kumar Sharma y Alfilh Raed Hameed Chyad. "Adiabatic technique based low power synchronous counter design". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 4 (1 de agosto de 2023): 3770. http://dx.doi.org/10.11591/ijece.v13i4.pp3770-3777.
Texto completoKumar, Umesh. "Vlsi Interconnection Modelling Using a Finite Element Approach". Active and Passive Electronic Components 18, n.º 3 (1995): 179–202. http://dx.doi.org/10.1155/1995/97362.
Texto completoBalodi, Deepak y Rahul Misra. "Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process". SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, n.º 01 (25 de julio de 2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.
Texto completoYeh, Chung-Huang y Jwu-E. Chen. "Unbalanced-Tests to the Improvement of Yield and Quality". Electronics 10, n.º 23 (4 de diciembre de 2021): 3032. http://dx.doi.org/10.3390/electronics10233032.
Texto completoLaudis, Lalin L. y N. Ramadass. "A Lion’s Pride Inspired Algorithm for VLSI Floorplanning". Journal of Circuits, Systems and Computers 29, n.º 01 (15 de marzo de 2019): 2050003. http://dx.doi.org/10.1142/s0218126620500036.
Texto completoSmy, T., S. K. Dew y M. J. Brett. "Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization". MRS Bulletin 20, n.º 11 (noviembre de 1995): 65–69. http://dx.doi.org/10.1557/s0883769400045619.
Texto completoKrishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi y V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm". International Journal of Innovative Research in Computer Science and Technology 10, n.º 2 (30 de marzo de 2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.
Texto completoQiao, Zhitong, Yan Han, Xiaoxia Han, Han Xu, Will X. Y. Li, Dong Song, Theodore W. Berger y Ray C. C. Cheung. "ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis". Neural Computation 30, n.º 9 (septiembre de 2018): 2472–99. http://dx.doi.org/10.1162/neco_a_01107.
Texto completoShacham-Diamand, Yosi. "The Reliability of Aluminum/Tungsten Technology for VLSI Applications". MRS Bulletin 20, n.º 11 (noviembre de 1995): 78–82. http://dx.doi.org/10.1557/s0883769400045644.
Texto completoSidorenko, V. P., V. D. Zhora, O. I. Radkevich, V. P. Grunyanska, Yu V. Prokofiev, Yu V. Tayakin y T. M. Virozub. "Assembly technology and design features of microelectronic coordinate-sensitive detectors". Технология и конструирование в электронной аппаратуре, n.º 1 (2018): 21–27. http://dx.doi.org/10.15222/tkea2018.1.21.
Texto completoSatria, Brama Yoga, Munawar Agus Riyadi y Muhammad Arfan. "PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC". TRANSIENT 6, n.º 3 (9 de noviembre de 2017): 476. http://dx.doi.org/10.14710/transient.6.3.476-482.
Texto completoDong, Chen, Jinghui Chen, Wenzhong Guo y Jian Zou. "A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things". International Journal of Distributed Sensor Networks 15, n.º 12 (diciembre de 2019): 155014771988809. http://dx.doi.org/10.1177/1550147719888098.
Texto completoManjunath, T. C., Deekshitha P., Pavithra G., Sindhu Sree M., Suhasini V.K. y K. N. Vijaykumar. "A Survey of the Different Intelligent Algorithms for the VLSI-Based Design Flows for Various Embedded Applications in Electronics Engineering". Journal of Embedded Systems and Processing 7, n.º 3 (3 de noviembre de 2022): 14–17. http://dx.doi.org/10.46610/joesp.2022.v07i03.003.
Texto completoMai, Christian, Steffen Marschmeyer, Anna Peczek, Aleksandra Kroh, Josmy Jose, Sebastian Reiter, Inga Fischer, Christian Wenger y Andreas Mai. "Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology". ECS Meeting Abstracts MA2022-02, n.º 32 (9 de octubre de 2022): 1174. http://dx.doi.org/10.1149/ma2022-02321174mtgabs.
Texto completoDeekshitha P, Pavithra G, Sindhu Sree M y T.C.Manjunath. "AI/ML/DL Algorithms and Applications in VLSI Design Technology Process Flow – A Brief Review". international journal of engineering technology and management sciences 6, n.º 6 (28 de noviembre de 2022): 329–32. http://dx.doi.org/10.46647/ijetms.2022.v06i06.057.
Texto completoFlemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth y Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (1 de enero de 2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.
Texto completoSharma, Himanshu y Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects". Journal of Circuits, Systems and Computers 29, n.º 12 (5 de febrero de 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
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