Tesis:

1

Sepúlveda, S. Diego. "ICS: — Industrias Creativas Santiago". Tesis, Universidad de Chile, 2012. http://repositorio.uchile.cl/handle/2250/100417.

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El presente proyecto de título nace como un cuestionamiento personal acerca del consumo cultural en nuestro país. Pretendo abordar con fascinación la producción cultural contemporánea, fuertemente infl uenciada por la tecnología y la electrónica de consumo, y que ha sufrido un acelerado desarrollo desde la inserción de la televisión en los hogares chilenos en la década del 60’. Propongo pensar en un espacio para la concepción, producción, post-producción y difusión de este tipo de bien cultural, en todos los niveles de profesionalismo, bajo el amparo del concepto de industria creativa, un aporte que puede aportar a la consolidación cultural y el acceso democrático a esta expresión. Finalmente el proyecto desarrolla paralelamente una memoria audiovisual complementaria a este documento, que puede ser visitada en la url http:// memoriaics.tumblr.com/ como una herramienta sugerente al proyecto de arquitectura y sus posibles situaciones y con eso una ayuda ante cualquier decisión del mismo y su comprensión.

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2

Kwon, Dongwon. "Piezoelectric kinetic energy-harvesting ics". Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47571.

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Wireless micro-sensors can enjoy popularity in biomedical drug-delivery treatments and tire-pressure monitoring systems because they offer in-situ, real-time, non-intrusive processing capabilities. However, miniaturized platforms severely limit the energy of onboard batteries and shorten the lifespan of electronic systems. Ambient energy is an attractive alternative because the energy from light, heat, radio-frequency (RF) radiation, and motion can potentially be used to continuously replenish an exhaustible reservoir. Of these sources, solar light produces the highest power density, except when supplied from indoor lighting, under which conditions the available power decreases drastically. Harnessing thermal energy is viable, but micro-scale dimensions severely limit temperature gradients, the fundamental mechanism from which thermo piles draw power. Mobile electronic devices today radiate plenty of RF energy, but still, the available power rapidly drops with distance. Harvesting kinetic energy may not compete with solar power, but in contrast to indoor lighting, thermal, and RF sources, moderate and consistent vibration power across a vast range of applications is typical. Although operating conditions ultimately determine which kinetic energy-harvesting method is optimal, piezoelectric transducers are relatively mature and produce comparatively more power than their counterparts such as electrostatic and electromagnetic kinetic energy transducers. The presented research objective is to develop, design, simulate, fabricate, prototype, test, and evaluate CMOS ICs that harvest ambient kinetic energy in periodic and non-periodic vibrations using a small piezoelectric transducer to continually replenish an energy-storage device like a capacitor or a rechargeable battery. Although vibrations in surrounding environment produce abundant energy over time, tiny transducers can harness only limited power from the energy sources, especially when mechanical stimulation is weak. To overcome this challenge, the presented piezoelectric harvesters eliminate the need for a rectifier which necessarily imposes threshold limits and additional losses in the system. More fundamentally, the presented harvesting circuits condition the transducer to convert more electrical energy for a given mechanical input by increasing the electromechanical damping force of the piezoelectric transducer. The overall aim is to acquire more power by widening the input range and improving the efficiency of the IC as well as the transducer. The presented technique in essence augments the energy density of micro-scale electronic systems by scavenging the ambient kinetic energy and extends their operational lifetime. This dissertation reports the findings acquired throughout the investigation. The first chapter introduces the applications and challenges of micro-scale energy harvesting and also reviews the fundamental mechanisms and recent developments of various energy-converting transducers that can harness ambient energy in light, heat, RF radiation, and vibrations. Chapter 2 examines various existing piezoelectric harvesting circuits, which mostly adopt bridge rectifiers as their core. Chapter 3 then introduces a bridge-free piezoelectric harvester circuit that employs a switched-inductor power stage to eliminate the need for a bridge rectifier and its drawbacks. More importantly, the harvester strengthens the electrical damping force of the piezoelectric device and increases the output power of the harvester. The chapter also presents the details of the integrated-circuit (IC) implementation and the experimental results of the prototyped harvester to corroborate and clarify the bridge-free harvester operation. One of the major discoveries from the first harvester prototype is the fact that the harvester circuit can condition the piezoelectric transducer to strengthen its electrical damping force and increase the output power of the harvester. As such, Chapter 4 discusses various energy-investment strategies that increase the electrical damping force of the transducer. The chapter presents, evaluates, and compares several switched-inductor harvester circuits against each other. Based on the investigation in Chapter 4, an energy-investing piezoelectric harvester was designed and experimentally evaluated to confirm the effectiveness of the investing scheme. Chapter 5 explains the details of the IC design and the measurement results of the prototyped energy-investing piezoelectric harvester. Finally, Chapter 6 concludes the dissertation by revisiting the challenges of miniaturized piezoelectric energy harvesters and by summarizing the fundamental contributions of the research. With the same importance as with the achievements of the investigation, the last chapter lists the technological limits that bound the performance of the proposed harvesters and briefly presents perspectives from the other side of the research boundary for future investigations of micro-scale piezoelectric energy harvesting.

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3

Волотка, В. С. "Analysis of reability of ics states". Thesis, ANALYSIS OF REABILITY OF ICS STATES, 2014. http://openarchive.nure.ua/handle/document/2082.

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A model of information and communication system is presented in the form of 4 main states: serviceable and unserviceable, each of them may be both in operative and standby modes. The main object of analysis is failure and appropriate parameters: mean time between fail-ures, availability coefficient, reliability probability, probability of survivability, an average total risk of failure probability.

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4

Monzer, Mohamad-Houssein. "Model-based IDS design pour ICS". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT056.

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Les systèmes industriels présentent des risques de sécurité liés à leurs vulnérabilités informatiques. Ces systèmes, répartis dans le monde, continuent d'être la cible d'attaques. Bien que les systèmes industriels partagent des vulnérabilités communes avec les systèmes informatiques, ils ont tendance à avoir plus de contraintes en raison de l'interaction entre les systèmes cyber et physiques.Les systèmes de détection d'intrusion donnent une visibilité au système et sont considérés comme l'une des solutions pour détecter les attaques ciblées. Il semble donc pertinent de s'appuyer sur un modèle physique du système cyber-physique pour obtenir un système de détection d'intrusion (IDS) pour les systèmes industriels. La plupart des IDS sont basés sur des règles qui définissent comment les attaques possibles sont détectées. Ces règles sont généralement utilisées pour décrire les scénarios d'attaque possibles sur les systèmes ou pour décrire le comportement normal du système. Cependant, la création et la maintenance manuels des règles pour un système complexe peuvent s'avérer être une tâche très difficile.Cette thèse propose une solution pour modéliser ICS et concevoir des IDS spécifiques pour les systèmes industriels. Un générateur de règles IDS basé sur un modèle est encore proposé, qui convertit un modèle de système en règles IDS basées sur des anomalies. Enfin, l'efficacité des règles générées est évaluée
Industrial systems present security risks related to their IT vulnerabilities. These systems, spread over the world, continue to be targets of attacks. While Industrial systems share common vulnerabilities with IT systems, they tend to have more constraints due to the interaction between cyber and physical systems.Intrusion detection systems give visibility to the system and are considered as one of the solutions to detect targeting attacks. Hence, it seems relevant to rely on a physical model of the cyber-physical system to obtain an intrusion detection system (IDS) for industrial systems. Most IDSs are based on rules that define how possible attacks are detected. These rules are generally used to either describe possible attack scenarios on the systems or used to describe the normal system behavior of the system. However, manually creating and maintaining rules for a complex system can prove to be a very tedious and difficult task.This thesis proposes a solution to model ICS and to design specific IDS for industrial systems. A model-based IDS rule generator is also proposed, which converts a system model into anomaly-based IDS rules. Finally, the effectiveness of the generated rules is evaluated

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5

Sidor, Peter. "Návrh infrastruktury ICS pro průmyslový podnik". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316693.

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This thesis deals with the issues of industrial communication, that is necessary to take account before making a final draft of industrial infrastructure and the overall design of a network infrastructure for a particular object. The first part of this thesis describes ICS system, parts of ICS and principle of operation. The thesis also focuses on the current trends in industrial networks, systems communication, security requirements of physical layer and the main differences from commercial infrastructures. The second part of the thesis describes the design of infrastructure for the foundry object. The final draft resolves the location of the switchboards, the specification of the used elements, the security, the cost of the solution and the final solution in practice.

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6

CEFFA, NICOLÒ GIOVANNI. "MICROFLUIDIC FLOW MAPPING WITH SPIM-ICS". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2018. http://hdl.handle.net/10281/198978.

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Il mio principale obiettivo è stato effettuare una mappatura spazio-temporale del flusso sanguigno in campioni biologici (embrioni Zebrafish), riuscendo a registrare immagini a campo largo (centinaia di micron), pur risolvendole a livello micrometrico; inoltre, essendo l’emodinamica un processo molto rapido, richiede alta frequenza di campionamento (da decine a centinaia di Hertz). La motivazione biologica consiste nel fatto che la progressione di un gran numero di malattie è legata direttamente alla circolazione sanguigna (un esempio importante è rappresentato dal cancro con le sue metastasi), sicché ho voluto elaborare un metodo per mappare quantitativamente il flusso in differenti condizioni, sia a scopo diagnostico, sia per studiare l’evoluzione di patologie (ad esempio la risposta infiammatoria). L’approccio seguito consiste nell’impiego della tecnica LSFM (Light Sheet Fluorescence Microscopy) accoppiata ad una telecamera ad alta efficienza e rapida frequenza di acquisizione, per raggiungere la risoluzione spazio-temporale prefissata (micron nello spazio, 4ms nel tempo). Agendo sul profilo di illuminazione è possibile manipolare un fascio laser per creare un sottile (spessore di pochi μm) foglietto di luce che selezioni otticamente il campione: il segnale di fluorescenza può essere quindi raccolto con una geometria a 90°. La camera utilizzata è una EMCCD, capace di una grande efficienza di raccolta (efficienza quantica del 95%), e che permette rapide acquisizioni. L’ultimo passo è stata la costruzione di campioni e strutture create appositamente per lavorare con la geometria propria del microscopio LSFM e per raggiungere la massima trasparenza. Molto lavoro è stato dedicato alla manipolazione di algoritmi di cross-correlazione, impiegati per studiare parametri di flusso: questi metodi sono in grado di raggiungere prestazioni eccellenti anche nella più intricata situazione incontrata nell’analisi di campioni biologici. La descrizione degli aspetti teorici e pratici del mio setup è al centro del Capitolo 2: qui descrivo la teoria della LSFM, concentrandomi su una descrizione dei profili di eccitazione e raccolta basata sul modello dell’Ottica Fisica. In seguito illustro l’implementazione pratica di due microscopi, uno per misure in vitro, l’altro per misure in-vivo, mostrando una calibrazione sperimentale dei parametri descritti. La seconda parte del capitolo è dedicata all’analisi dei metodi di cross-correlazione, fornendo una solida presentazione di tutte le tecniche usate per l’analisi di immagini. Infine descrivo concetti chiave di dinamica dei fluidi arrivando ad introdurre un modello circuitale e derivando l’equazione fondamentale (flusso di Poiseuille in canaletti a sezione rettangolare) impiegato per descrivere i sistemi in-vitro. Il capitolo 3 descrive materiali e metodi, concentrandosi sulle microstrutture in PDMS, sulla fabbricazione di liposomi, e sulla descrizione degli embrioni di zebrafish. Nel capitolo 4 riassumo i risultati di uno studio (sia in-vitro che in-vivo) sui flussi variabili nel tempo. Qui mostro una prima applicazione delle tecniche di cross-correlazione temporale, applicate allo studio di immagini a campo largo, che permette una mappatura dei flussi con alta risoluzione spazio-temporale. Nel capitolo 5 presento studi basati su correlazione spazio-temporali, applicati all’emodinamica in-vivo, in particolare riuscendo a caratterizzare il complesso flusso in regioni con ramificazioni di vasi. Il capitolo 6 si concentra sulla parte più recente del mio lavoro, cioè la ricerca di un modo per rompere la “restrizione planare” che sembra essere intrinsecamente presente quando si impiega un sistema LSFM. Mostro che metodi correlativi possono essere estesi permettendo di ricavare informazioni su regimi di flusso tridimensionali, senza alcuna modifica nel setup. Infine il capitolo 7 è dedicato alle conclusioni ed alle prospettive future.
My goal was to perform space and time mapping of blood flow in biological samples (Zebrafish embryos), being able to collect wide images (hundreds of microns), but still resolving them at a μm level; moreover hemodynamics is a fast process, that requires very high frequency sampling (tens to hundreds of Hz) in order to be resolved. The general biological motivation is that the progression of a wide number of diseases is affected directly by the blood circulation (an important example is cancer and its metastases), so that I want to devise an test methods to quantitatively map blood flow in different conditions, both for diagnosis and study of pathologies evolution . The approach I followed in my work is to employ Light Sheet Fluorescence Microscopy (LSFM) technique (also known as Selective-Plane Illumination Microscopy, SPIM) and a fast-acquisition, high efficiency camera, in order to achieve the minimum spatio-temporal resolution required (microns in space, 4ms in time). Acting on illumination profile, it is in fact possible to engineer a sheet of light to select just a thin (μm size) slice of the sample, so that fluorescence signals coming from just that plane can be measured in a 90° collection geometry. The CCD camera employed is an EMCCD, fabricated with a very advanced technology, capable of extremely high efficiency detection (quantum efficiency up to 95%), thus allowing very fast acquisition speeds. The last step was to fabricate samples and sample holder specifically designed to work with SPIM geometry, to achieve high transparency. Much work has been devoted to the study and manipulation of cross-correlation based algorithms, employed to retrieve flow parameters: being based on noise analysis, it is capable of excellent performances even in the most intricate biological situation I tried to investigate. The description of theoretical and practical aspects of my setup is the core of Chapter 2: I describe Single Plane Illumination Microscopy, focusing on a Physical Optics description of illumination and detection profiles. Then I will describe the practical implementation of two microscopes, one for in-vitro and one for in-vivo testing, showing an experimental evaluation of useful parameter derived in the previous section. The second part of the chapter is dedicated to the analysis of Cross-Correlation methods, providing both a solid presentation of all the techniques employed for image analysis, and also serving as an introduction for chapter 6, where an extension of these methods will be presented. Finally I will cover basic fluid dynamics to introduce a simple lumped circuit model, deriving the fundamental equation (Poiseuille flow in square channels) employed to describe in-vitro flows. Chapter 3 will describe material and methods, dealing with PDMS based microstructures, liposomes fabrication, and Zebrafish embryos description. In Chapter 4 I will summarize the results of the study of both in-vitro and in-vivo time-varying flows. Here I show a a first powerful application of temporal cross-correlation techniques coupled with large field of view images, which allows high resolution (both in time and space) mapping of flows. In Chapter 5 I will present related investigations, based on Image spatio-temporal correlations, in which I focused on in-vivo hemodynamics, in particular mapping blood flow in branched vessels in zebrafish embryos. Chapter 6 focuses on the most recent part of my work, that is to explore a way to break the "plane restriction" that seems to be intrinsically present when employing SPIM based microscopy. I will show that correlative methods can be extended allowing to retrieve 3D flow information, without any change in the hardware, as happens, for example, in optical tomography or micro-PIV. Finally Chapter 7 is dedicated to conclusions and future outlook.

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7

Grosch, Eva. "Funktionelle Magnetresonanztomographie (MRT) und klinischer ICS-Score". Diss., lmu, 2004. http://nbn-resolving.de/urn:nbn:de:bvb:19-31778.

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8

Panth, Shreepad Amar. "Physical design methodologies for monolithic 3D ICs". Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53542.

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The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.

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9

Váňa, Martin. "Kybernetické prostředí pro systémy typu ICS/SCADA". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400894.

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The thesis explores the problematics of cyber environment for the ICS/SCADA systems. First, shorter section is mainly focused on general introduction into the ICS/SCADA systems and their inner workings. Communication model of a general SCADA system and its foundational elements are explained. It is mainly theoretical passage and it serves as an introduction. It is necessary for understanding the second part which is mainly practical. The appropriate system is chosen as a first thing in the practical part of the thesis for the implementation of the whole project. There are defined criteria on which the system itself is implemented. Following that the system itself is implemented under a framework called openMUC and it is tested with help of the simulators according to the objective of the thesis.

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10

Schenkel, Michael. "Substrate current effects in smart power ICs". [S.l. : s.n.], 2003. http://e-collection.ethbib.ethz.ch/ecol-pool/diss/fulltext/eth14925.pdf.

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11

Ávila, Eliana de Souza. "A poet(h)ics of intercultural dissonance". Florianópolis, SC, 2002. http://repositorio.ufsc.br/xmlui/handle/123456789/82531.

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Tese (doutorado) - Universidade Federal de Santa Catarina, Centro de Comunicação e Expressão. Programa de Pós-Graduação em Letras/Inglês e Literatura Correspondente.
Made available in DSpace on 2012-10-19T15:54:42Z (GMT). No. of bitstreams: 1 197661.pdf: 24376555 bytes, checksum: d64a0778d8a12b5e9970b8d70188540b (MD5)
Análise da poética intercultural de Elizabeth Bishop, elaborando uma percepção expansiva de dissonância ou choque cultural, que problematiza os próprios termos através dos quais o pensamento antitético reduz a realidade experiencial. Demonstra inter-relações entre os textos teórico-críticos de Bishop, que engajam sua crise com a concepção linear do tempo narrativo, e a concepção de 'dissonância emancipatória' ou atonal elaborada por Arnold Schöenberg. Demonstra que os mapeamentos de dissonância cultural feitos por Bishop no Brasil desafiam seus próprios modelos esteticistas e solucionistas (lineares, teleológicas) de representação (especificamente, os modelos de transculturalismo e autenticismo), ao se recusarem a resolver a alteridade (do outro e do eu) na uniformidade (consonância), ou mesmo a dissolver seus conflitos, fixando a alteridade num 'passado atemporal' (sic), primitivizado. Examina a crise (a crítica) textual de consciência social e de gênero no corpus brasileiro de Bishop, argumentando que ele se torna valioso justamente porque a autora fracassa, e de modo perturbador, em realizar seu projeto de produzir resolução sobre suas percepções dissonantes da realidade. Engaja uma política irredutível ou ética de leitura que recusa reduzir o texto intercultural de Bishop a seus discursos solipsistas, pelos quais até mesmo atos aparentemente democráticos convergem dissimuladamente com dinâmicas totalitárias.

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12

Salah, Ben Romdhane Mohamed. "Design synthesis of application-specification ICs for DSP". Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15392.

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13

Davis, Robert Brent. "The law and econom(etr)ics of corruption". Thesis, The University of Sydney, 2014. http://hdl.handle.net/2123/13372.

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Corruption has become a deep-rooted feature of many economies and societies around the world. At the same time, there has been growing efforts both in international and municipal law to tackle, if not eliminate, the problem of corruption. This thesis looks at the effectiveness of such laws. In doing so, it draws on the toolkit of leximetrics (the application of econometrics to the law) to rigorously and transparently examine whether the creation of legal instruments lead to a behavioural change in impacted actors. The study also undertakes an expansive review of the theories of, and the literature on, law and economics, and develops new perspectives on the law and economics of corruption.

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14

Hehemann, Ingo. "Schnelle optoelektronische ICs für sichtbares Licht in CMOS-Technologie". [S.l. : s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=971485003.

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15

Moradi, Monfared Sahar. "Dynamical models for the Ion Channel Switch (ICS) biosensor". Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/27805.

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This thesis derives dynamical models that explain the operation of a solid phase immunoassay biosensor, the Ion Channel Switch (ICS) biosensor. The ICS biosensor unlike similar biosensors admits multiple surface chemical reactions which make the mathematical models significantly more complex than models used to describe alike biosensors. A two dimensional partial differential equation describes the distribution of the analyte through out the ﬂow chamber. The interaction of analyte and the immobilized species at the biosensor electrode is modeled through the boundary condition at the bottom of the ﬂow chamber. This boundary condition couples the partial differential equation to a set of nonlinear ordinary differential equations which are used to describe the surface chemical reactions. This model produces accurate results particularly when the rate of transport of analyte to the biosensor surface is comparable to the rate of reactions occurring at the biosensor surface. However, when the rate of mass transport is much faster than the reaction rates, the dynamics of the ICS biosensor can be accurately described by a system of nonlinear ordinary differential equations in which analyte concentration is assumed constant. Accuracy of the derived mathematical models are veriﬁed by comparing the simulated biosensor response to that obtained from an experimental run of the ICS biosensor.

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16

Lee, Young-Joon. "CAD methodologies for low power and reliable 3D ICs". Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47635.

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The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.

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17

Jung, Moongon. "Low power and reliable design methodologies for 3D ICs". Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51824.

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The main objective of this dissertation is to explore and develop computer-aided-design methodologies and optimization techniques for reliability, performance, and power of through-silicon-via-based 3D IC designs. Through-silicon-via (TSV), a vertical interconnect element between dies, is the key enabling technology in 3D ICs. This new design element provides unprecedented design freedom as well as challenges. To maximize benefits and overcome challenges in TSV-based 3D ICs, new analysis methodologies and optimization techniques should be developed. In this dissertation, first, the robustness of 3D power delivery network is assessed under different power/ground TSV placement schemes and TSV RC variations. Next, thermo-mechanical stress and reliability problems are examined in full-chip/stack scale using the principle of linear superposition of stress tensors. Finally, physical design methods for low power 3D designs are explored to enhance the 3D power benefit over the 2D counterpart.

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18

Gibson, David A., Newton B. Penrose y Ralph B. Jr Wade. "HSTSS-DAC CUSTOM ICS IMPACT ON 2.75" MISSILE TELEMETRY". International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608742.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada
We analyze several telemetry data acquisition systems to gage the system impact of denser custom ICs being developed under the HSTSS-DAC project. Our baseline is a telemetry system recently developed at Eglin AFB to support 16 analog input channels, signal conditioning and encoding for Pulse Code Modulation (PCM) using Commercial Off-the- Shelf (COTS) ICs. The data acquisition portion of the system occupies three double-sided, round circuit cards, each 2.3" in diameter. A comparable system using HSTSS-DAC custom Ics will occupy only one side of one card - a factor of six-volume reduction compared to the COTS approach.

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19

Aymerich, Gubern Joan. "Low-power read-out ICs for smart electrochemical sensors". Doctoral thesis, Universitat Politècnica de Catalunya, 2021. http://hdl.handle.net/10803/671918.

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Electrochemical sensors are expanding rapidly over other chemical sensoring technologies because of their potential to generate precise, selective, miniaturized and cost-effective analytical devices. These features satisfy the emerging global demand for disposable testing systems at the point-of-need, where usability, portability, and price counts most, enabling to detect critical analytical evidence by anyone, any-where and at any time, without concerning about recalibration and limited shelf life. In particular a disposable electrochemical device must include a paired smart electronic interface to specifically bias the electrochemical cell, acquire signals, per-form data conversion and communicate measurements through a standard digital interface, all under severe restrictions of size and power consumption. This thesis describes the development of a novel, cost-effective, disposable, high-performance and user-friendly electrochemical sensing platform that combines the smartness of CMOS integrated circuits (ICs) with the flexibility of printed electronics. Two practical µW-range readout integrated circuit (ROIC) realizations in 65-nm and0.18-µmCMOS technologies are presented and specifically optimized for the potentiostatic biasing and amperometric read-out of electrochemical sensors. The proposed frontend architectures yield very elegant and compact CMOS implementations by reusing the dynamic properties of the sensor itself to implement continuous-time mixed electrochemical delta-sigma modulators (¿SM). The topologies include differential potentiostats to extend its range. Furthermore, low limit of detection (LOD) values can be achieved by implementing a novel cancellation mechanism of the flicker noise coming from the feedback DAC of the electrochemical ¿SM. A standard interface based onI2Cis included on-chip not only to control the extensive system configuration but also to limit the number of IC pads towards a low-cost flip-chip assembly on flexible substrates. Experimental results from both electrical and electrochemical tests are presented and compared to other state-of-the-art electrochemical sensor frontends. A cost-effective hybrid electronics interfacing approach is proposed, where the electrochemical sensor is directly printed on a flexible PEN substrate that also hosts the CMOS readout integrated circuit (ROIC) as a bare die without wire bonding. Low-cost inkjet printing technology is employed for the development of a three-electrode sensor and all the required connectivity. Anisotropic conductive adhesives are investigated as an emerging approach for mechanical and electrical contact between the IC die and printed inks in order to obtain a disposable flexible smart electrochemical sensory device.
En els últims anys s’ha produït una ràpida expansió dels sensors electroquímics en comparació amb altres tecnologies químiques de sensat gràcies al seu potencial per generar dispositius analítics precisos, selectius, miniaturitzats i econòmics. Aquestes característiques satisfan l’actual creixent demanda de sistemes de sensat d’un sol ús, on la usabilitat, la portabilitat i el preu són els factors més importants, permetent detectar evidència analítica per qualsevol persona, en qualsevol lloc i en qualsevol moment, sense limitacions en termes de calibratge o de temps de vida útil. En particular, un dispositiu electroquímic ha d’incloure una interfície electrònica intel·ligent aparellada per estimular específicament la cèl·lula electroquímica, adquirir senyals, realitzar la conversió de dades i comunicar les mesures a través d’una interfície digital estàndard, tot sota restriccions severes de mida, cost i potencia consumida. Aquesta tesi descriu el desenvolupament d’una nova plataforma de detecció electroquímica, econòmica, d’un sol ús, d’alt rendiment i fàcil d’utilitzar, que combina la intel·ligència de circuits integrats CMOS amb la flexibilitat de l’electrònica impresa. Es presenten dues realitzacions de circuits integrats de lectura en tecnologies CMOS de65-nm i 0.18-µmamb un consum de l’ordre de µW, específicament optimitzades per ala polarització potenciostàtica i la lectura amperometria de sensors electroquímics. Les interfícies proposades ofereixen implementacions CMOS molt elegants i compactes, ja que reutilitzen les propietats dinàmiques del mateix sensor per implementar moduladors Delta-Sigma (ΔΣM) mixtes en temps continu. Les topologies inclouen potenciostats diferencials per ampliar el seu rang. A més, permeten aconseguir un límit baix de detecció mitjançant la implementació d’un nou mecanisme de cancel·lació del soroll de baixa freqüència pro-vinent de la retroalimentació digital-analògic del modulador ΔΣM electroquímic. El xip inclou una interfície digital estàndard basada en I2C per controlar l’extensa configuració del sistema i també per reduir el nombre de connexions externes de cara al seu muntatge de baix cost sobre substrats flexibles. Es presenten resultats experimentals de les proves tant elèctriques com electroquímiques i es comparen amb altres interfícies de sensors electroquímics d’última generació. Finalment, es proposa una interfície híbrida rendible, on s’imprimeix directament el sen-sor electroquímic sobre un substrat PEN flexible que també allotja la interfície CMOS integrada de lectura a nivell de dau de silici sense encapsular. Els tres elèctrodes del sensor i tota la connectivitat s’aconsegueixen gràcies a la tecnologia d’impressió d’injecció de tinta de baix cost. Així mateix, s’investiguen els adhesius conductors anisotròpics com un enfocament emergent per al contacte mecànic i elèctric entre la matriu del circuit integrat CMOS i les tintes conductores per tal d’obtenir un dispositiu sensorial electroquímic flexible d’un sol ús.

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20

AIELLO, ORAZIO. "Susceptibility to EMI of ICs for Power MOS Monitoring". Doctoral thesis, Politecnico di Torino, 2013. http://hdl.handle.net/11583/2506258.

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The widespread use of wired and wireless electronic systems has raised the level of electromagnetic pollution. For this reason, any electronic equipment and particularly those dealing with safety, should be conceived to work properly in harsh environments. In particular, power and analog front-end of a Smart Power integrated circuits (ICs) are directly exposed to the electromagnetic Interference (EMI) collected by cable harnesses, PCB traces, bonding wires and leadframes, which behaves like parasitic antennas. This PhD Thesis deals with the susceptibility of power and analog front-end circuits to EMI. Among the circuits for control and monitoring purpose, in this research work the current and temperature sensors are specifically addressed. An overview of the existing current sensor is provided. Two new methods for integrated current monitoring are presented in order to reduce the susceptibility to electromagnetic disturbances affecting the drain-source terminals of an integrated power MOS transistor. A new integrated solution for current monitoring based on Hall-effect is firstly proposed. This sensor exploits the magnetic sensitive properties of a split-drain transistor namely MagFET. The galvanic isolation between the sensor and the current to detect allows to increase the EMI immunity in current monitoring. Then, a further current sensor based on the mirror principle is described. Improved performance in terms of reactiveness and EMI immunity are shown. After that, the effect of EMI on integrated temperature sensors are investigated referring to a thermal shutdown circuit. The guidelines to improve to immunity to EMI of such circuits are given by means of simulations and experimental measurements that experienced the high reliability of the proposed temperature sensing in EMI polluted environment. The methods developed have been also used to design solutions to increase the immunity to EMI of readout front-end circuit for electronics employed in implanted circuit has been also presented. Bio-potential signals are usually monitored in current medical practice for diagnostics of several different disorders. Neural recording amplifiers that are usually employed to monitor such weak signals, can be can saturated by interference. Therefore, the effect of EMI received by the human body that behaves as an antenna, is a significant problem to specifically address.

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21

Piazza, Francesco. "Low power RF-receiver front-end ICs for mobile communications /". Zürich, 2000. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=13669.

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22

Kaya, Idris. "Ein kräftegesteuerter Platzierer für 3D-ICs mit Berücksichtigung vertikaler Durchkontaktierungen". [S.l. : s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=973168471.

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23

Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS". Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.

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For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.

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24

Zhang, Yue. "Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs". Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53539.

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A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack is needed. Second, in the heterogeneous integration, an effective thermal isolation solution is needed to ‘protect’ the low-power tier from the high-power tier. This research focuses to address these two thermal challenges through hybrid microfluidic cooling and thermal isolation technologies. Within-tier microfluidic cooling is proposed and demonstrated to cool a stack with multiple high-power tiers. Electrical thermal co-analysis is performed to understand the trade-offs between through silicon via (TSV) parasitics and heat sink performance. A TSV-compatible micropin-fin heat sink is designed, fabricated and thermally characterized in a single tier, and benchmarked with a conventional air-cooled heat sink. The designed heat sink has a thermal resistance of 0.269 K·cm2/W at a flow rate of 70 mL/min. High aspect ratios TSVs (18:1) are integrated in the micropin-fins. Within-tier microfluidic cooling is then implemented in 3D stacks to emulate different heating scenarios, such as memory-on-processor and processor-on-processor. Air gap and mechanically flexible interconnects (MFIs) are proposed for the first time to decrease the vertical thermal coupling between high-power (e.g. processor) and low-power tiers (e.g. memory or nanophotonics). A two-tier testbed with the proposed thermal isolation technology is designed, fabricated and tested. Compared with conventional 3D integration approach, thermal isolation technology helps reduce the temperature at a fixed location in the low-tier by 12.9 °C. The resistance of a single MFI is measured to be 46.49 mΩ.

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25

Chia, Mark P. C. "Efficient critical area extraction for photolithographically defined patterns on ICs". Thesis, University of Edinburgh, 2002. http://hdl.handle.net/1842/13371.

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The IC industry is developing at a phenomenal rate where smaller and denser chips are being manufactured. The yield of the fabrication process is one of the key factors that determine the cost of a chip. The pattern transfered onto silicon is not a perfect representation of the mask layout, and for an SRAM cell this results in a difference of 3 % between the average number of faults calculated from the mask layout and the aerial image. This thesis investigates methods that are capable of better estimating the yield of an IC during their design phase which can efficiently and accurately estimate the critical area (CA) without the need to directly calculate the aerial image. The initial attempt generates an equivalent set of parallel lines from the mask layout which is then used to estimate the CA after pattern transfer. To achieve this EYE, Depict and WorkBench were integrated with in-house software. Benchmarking on appropriate layouts resulted in estimates within 0.5 - 2.5 % of the aerial image compared with 1.5 -3.5 % for the mask layout. However, for layouts which did not lend themselves to representation by equivalent parallel lines, this method resulted in estimates that were not as accurate as those obtained using the mask layout. The second approach categorises CA curves into different groups based on physical characteristics of the layout. By identifying which group a curve belongs to, the appropriate mapping can be made to estimate the pattern transfer process. However, due to the large number of track combinations it proved too difficult to reliably classify layouts into an appropriate group. Another method proposed determines a track length and position using a combination of AND and OR operations with shifting algorithms. The limitation of this approach was that it was not robust and only proved to work with certain layout types. The fourth method used a one dimensional algorithm to categorise layouts. The estimated CA was within 0.2 % of the aerial image as compared to the mask layout CA of 2.2 %. The disadvantage of this method is that it can only classify parallel tracks. The next approach built upon the above method and can categorise a layout in two dimensions, not being limited to parallel tracks. A variety of designs were used as benchmarks, and for these layouts this method resulted in estimates that were within 0 - 10.7 % of the aerial image compared with 0.5 - 13.4 % for the mask layout.

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26

Fonseca, Luís Carlos Costa. "SISTEMA MULTIAGENTES PARA NEGOCIAÇÃO NO AMBIENTE ICS DE COMÉRCIO ELETRÔNICO". Universidade Federal do Maranhão, 2003. http://tedebc.ufma.br:8080/jspui/handle/tede/325.

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Made available in DSpace on 2016-08-17T14:52:46Z (GMT). No. of bitstreams: 1 Luis Carlos Costa.pdf: 746068 bytes, checksum: f166f2cc1f233fa3ddbeff894e618cf7 (MD5) Previous issue date: 2003-04-14
This work is part of a major project called ICS (Intelliget Commerce System) that has as it´s main goal to develop an Intelligent Negotiation System for Eletronic Business on the B2B category wich is being developed at UFMA (Maranhão s Federal University) under the Coordination of Prof. Dr. Sofiane Labidi. In this work we will specifically see the basic architecture proposed for the system, the technologies that bases it and in a more detailed way we will see the negotiation between sofware agents beyond its applications in the proposed system. In this context, we intend, to propose and develop a system that can automatize the negotiation mechanisms - purchase and sale of products and services - making the interactions between companies faster, more sophisticated and efficient, and thus increase even more the profits of this business. Being so, we present the ICS (Intelligent Commerce Sysrtem) as an Eletronic Business System based on Mobile Software Agent s technology that follows the OMG MASIF2 of OMG standard(OMG, 2000). Three important features of ICS are emphasized: the eletronic commerce lifecycle, the user modeling and the proposed ontologies on each of the lifecycle´s phase. Thus the ICS aims to get as end item of the negotiation, the best opportunities of purchase and sale of products and services, thus providing, a decision making support system.
Este trabalho faz parte de um projeto maior chamado ICS (Intelliget Commerce System) e que tem como objetivo desenvolver um Ambiente Inteligente de Negociação para Comércio Eletrônico na categoria B2B e que está sendo desenvolvido na UFMA (Universidade Federal do Maranhão) sob a Orientação do Prof. Dr. Sofiane Labidi. Neste trabalho trataremos especificamente da arquitetura básica proposta para o sistema, as tecnologias que o fundamentam e de forma mais detalhada trataremos da negociação entre agentes de software além das suas aplicações no sistema ora proposto. Neste contexto, pretendemos, propor e implementar um sistema que possa automatizar os mecanismos de negociação - compra e venda de produtos e serviços - tornando as interações entre empresas mais sofisticadas, rápidas e eficientes, e assim incrementar ainda mais os lucros deste ramo de negócio. Sendo assim, nós apresentamos o ICS (Intelligent Commerce Sysrtem) como um sistema de Comércio Eletrônico baseado na tecnologia de Agentes Móveis seguindo o padrão MASIF1 da OMG (OMG, 2000). Três importantes características do ICS são enfatizadas: ciclo de vida do comércio eletrônico, modelagem do usuário e as ontologias propostas para cada fase do ciclo de vida. Assim o ICS visa obter como produto final da negociação, as melhores oportunidades de compra e venda de produtos e serviços, provendo assim, um sistema de suporte à tomada de decisão.

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27

Bastos, Filho Othon de Carvalho. "MODELAGEM DO USUÁRIO PARA O SISTEMA ICS DE COMÉRCIO ELETRÔNICO". Universidade Federal do Maranhão, 2003. http://tedebc.ufma.br:8080/jspui/handle/tede/327.

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Made available in DSpace on 2016-08-17T14:52:47Z (GMT). No. of bitstreams: 1 Othon Bastos F.pdf: 1647627 bytes, checksum: 7dcef19065f85742782759bb7e6efe8a (MD5) Previous issue date: 2003-04-15
The Electronic Commerce (E-commerce) grew very in recent years. This type of Commerce, call also digital or virtual commerce, is characterized for the increasing capacity of supply, global competition, increasing, with this, the expectations of the consumers, thus causing, one high competition between the companies, who very change of fast form the businesses and the way to operate. Being that, it can be perceived that the companies who will not be ready for the changes, in a short period had been it stops backwards in the world of the businesses. The Electronic Commerce allows that such changes can be supported in one it scales global, making possible a bigger efficiency and flexibility, this occurs by means of the agility in taking care of to the necessities and expectations of the customers. For this new paradigm, it currently starts if to legalize the business-oriented call Intelligence (Business Intelligence), whose purpose is to manage the knowledge in the age of the global competition and the communications on-line.
O Comércio Eletrônico (E-commerce) cresceu muito nos últimos anos. Esse tipo de Comércio, chamado também comércio digital ou virtual, caracteriza-se pela crescente capacidade de fornecimento, competição global, aumentando, com isso, as expectativas dos consumidores, causando assim, uma alta concorrência entre as empresas, que mudam de forma muito rápida os negócios e o modo de operar. Sendo que, pode-se perceber que as empresas que não estiverem prontas para as mudanças, em um curto período ficaram para trás no mundo dos negócios. O Comércio Eletrônico permite que tais mudanças possam ser suportadas em uma escala global, possibilitando uma maior eficiência e flexibilidade, isto ocorre por meio da agilidade em atender às necessidades e expectativas dos clientes. Para este novo paradigma, começa atualmente a se formalizar a chamada Inteligência de Negócios (Business Intelligence), cuja finalidade é gerenciar os conhecimentos na era da competição global e das comunicações on-line.

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28

Faísca, Carlos Manuel dos Santos Alves Ferreira. "Uma política de desbaste para a biblioteca do ICS/UL". Master's thesis, Faculdade de Ciências Sociais e Humanas, Universidade Nova de Lisboa, 2010. http://hdl.handle.net/10362/9078.

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Relatório de Estágio apresentado para cumprimento dos requisitos necessários à obtenção do grau de Mestre em Ciências da Informação e da Documentação – Área de Especialização em Biblioteconomia
Este relatório de estágio estuda o desbaste com o objectivo final da definição de uma política de desbaste para a colecção de monografias da Biblioteca do ICS/UL. A primeira parte consiste na revisão da literatura sobre o desbaste; a segunda, tem um carácter empírico, através do estudo da ocupação actual do espaço na Biblioteca do ICS/UL e da avaliação das colecções de monografias. Como consequência natural, e de acordo com os estudos previamente realizados, surge então a definição de uma política de desbaste, onde se encontram definidos, entre outras questões, os critérios de desbaste. Dentro da mesma lógica de trabalho, são elaboradas sugestões sobre o destino dos itens alvo de desbaste. São também abordadas outras vertentes do âmbito da gestão de colecções e que podem influenciar decisivamente o desbaste, como a gestão de doações e a política de aquisições.

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29

Sundaresan, Vijay. "Architectural Synthesis Techniques for Design of Correct and Secure ICs". University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1217424117.

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30

Hanna, Drew E. "Developing RRAM-Based Approaches for Security and Provisioning of ICs". University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1617108121648124.

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31

Abdulrazzaq, Mohammed y Yuan Wei. "Industrial Control System (ICS) Network Asset Identiﬁcation and Risk Management". Thesis, Högskolan i Halmstad, Akademin för informationsteknologi, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-38198.

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Setting against the significant background of Industrial 4.0, the Industrial Control System (ICS) accelerates and enriches the upgrade the existing production infrastructure. To make the infrastructures “smart”, huge parts of manual operations have been automated in this upgrade and more importantly, the isolated controlled processes have been connected through ICS. This has also raised the issues in asset management and security concerns. Being the starting point of securing the ICS, the asset identification is, nevertheless, first dealt by exploring the definition of assets in the ICS domain due to insufficient documentation and followed by the introduction of ICS constituents and their statuses in the whole network. When the definition is clear, a well-received categorization of assets in the ICS domain is introduced, while mapping out their important attributes and their significance relating the core of service they perform. To effectively tackle the ever-increasing amount of assets, identification approaches are compared and a case study was performed to test the effectiveness of two open source software. Apart from the identification part, this thesis describes a framework for efficient asset management from CRR. The four cyclic modules proposed give an overview on how the asset management should be managed according the dynamics of the assets in the production environment.

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32

Sharmin, Afsana. "EMBEDDED COOLING OF HIGH PERFORMANCE ICS USING NOVEL NANOSTRUCTURED THERMOELECTRICS". OpenSIUC, 2013. https://opensiuc.lib.siu.edu/theses/1308.

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AN ABSTRACT OF THE THESIS OF AFSANA SHARMIN, for the Master of Science degree in Electrical and Computer Engineering, presented on November 1, 2013, at Southern Illinois University Carbondale. TITLE: EMBEDDED COOLING OF HIGH PERFORMANCE ICS USING NOVEL NANOSTRUCTURED THERMOELECTRICS MAJOR PROFESSOR: Dr. Shaikh S. Ahmed Site specific thermoelectric cooling in semiconductor materials is among the most promising approaches for the mitigation of on-chip hot spots resulting from the decreasing feature sizes and faster switching speeds of electronic components. The efficient usage of thermoelectric devices for hotspot cooling requires investigation and appropriate properties such as higher figure of merit, integration of these devices with electronic package, remedy of various obstacles such as parasitic contact resistances. A simulation model has been developed to investigate the effect of steady state operation of nanowire based thermoelectric cooler devices on hot-spot cooling considering the effect of crucial thermal and electrical contact resistances. The results suggest that active hotspot cooling of as much as 23ºC with a high (~1,300W/cm2) heat flux for nanowire based Bi2Te3 thermoelectric cooler. It has been observed from the results that thermal and electrical contact resistances play a very crucial role in the performance of nanowire based thermoelectric cooling devices as high values of these resistances can significantly degrade the effect of Peltier cooling.

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33

Sane, Hemant. "Power supply noise analysis for 3D ICs using through-silicon-vias". Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33875.

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3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.

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34

Su, Yinmei [Verfasser]. "Multi-functional Monolithic ICs for 94GHz Transmitters on Silicon / Yinmei Su". Ulm : Universität Ulm. Fakultät für Ingenieurwissenschaften und Informatik, 2015. http://d-nb.info/1065309724/34.

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35

Musabeyoglu, Ahmet Can. "A zero-voltage switching technique for high frequency buck converter ICs". Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/113122.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 59-60).
This thesis explores a zero-voltage switching (ZVS) method that can be used to decrease the frequency dependent losses in a buck converter. The specific application for this thesis was a buck converter IC with an input voltage of up to 42V. The method utilizes the addition of an auxiliary circuit composed of a helper inductor and two helper power MOSFETs that compliment the switching transition of a conventional synchronous buck converter topology. It is shown in this thesis that by using the described topology, the switching losses of the high-side power MOSFET in a synchronous buck converter can be reduced by up to 45%. Furthermore, it is shown that a similar helper circuit could be used to reduce the gate drive losses for both power MOSFETs in a synchronous buck converter by up to 60%. Since the method requires the use of an additional helper inductor with a small value (10-50 nH), various methods to integrate this inductor into an IC package are investigated. 0.35[mu]m BiCMOS technology was used to simulate and analyze the merits of the described topology and compare it to the LT8697, a hard-switched synchronous buck converter IC.
by Ahmet Can Musabeyoglu.
M. Eng.

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36

Almeida, Carlos Roberto Baluz. "COMPOSIÇÃO DE WEB SERVICES SEMÂNTICOS NO AMBIENTE ICS DE COMÉRCIO ELETRÔNICO". Universidade Federal do Maranhão, 2004. http://tedebc.ufma.br:8080/jspui/handle/tede/363.

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The ICS (Intelligent Commerce System), a developing project of the Intelligent Systems Lab (LSI) at Federal University of Maranhão (UFMA), under Prof. Dr. Sofiane Labidi´s supervision, is a project that has the objective of develop an Electronic Commerce System, in the B2B (Business to Business) category, effectively intelligent. It is based in the technology of intelligent mobile agents and has five phases in its life cycle: User Modeling, Matchmaking, Negotiation, Contract Formation and Contract Fulfillment. The Matchmaking is the process in which agents that represent traders (buyers and sellers), that are interested in the exchange of economic values, are put in touch with their potential business counterparts. The enrichment of the matchmaking process is the main focus of this work. Nowadays in the ICS, the matchmaking process only matches simple services. Our contribution is to enrich the actual matchmaking process allowing the composition of services, that is, simple services can add its capacities and form complex services with the goal to return a greater number of positive responses. To do this, we use ontologies allied to AI planning techniques to provide the discovery of complementary services and the posterior composition of them to elaborate more complex services.
O ICS (Intelligent Commerce System), projeto atualmente em desenvolvimento no Laboratório de Sistemas Inteligentes (LSI) na Universidade Federal do Maranhão (UFMA) sob a orientação do Prof. Dr. Sofiane Labidi, é um projeto que tem como objetivo desenvolver um Sistema de Comércio Eletrônico, na categoria B2B, efetivamente Inteligente. Ele é baseado na tecnologia de agentes móveis inteligentes e possui cinco fases no seu ciclo de vida: Modelagem do Usuário, Matchmaking, Negociação, Formação de Contrato e Cumprimento do Contrato. O Matchmaking é o processo no qual agentes representando negociantes (compradores e vendedores), que possuem interesse na troca de valores econômicos, são colocados em contato com seus potenciais parceiros de negócios. O enriquecimento do processo de matchmaking é o foco principal deste trabalho. Atualmente no ICS o processo de matchmaking somente emparceira serviços simples. Nossa contribuição é enriquecer o processo de matching atualmente em uso no ICS permitindo a composição de serviços, ou seja, serviços simples somam suas capacidades e formam serviços complexos com a finalidade de retornar maior número de respostas positivas. Para isso utilizamos ontologias aliadas às técnicas de planejamento automático para proporcionar a descoberta de serviços complementares e posterior composição dos mesmos para elaboração de serviços mais complexos.

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37

Gnawali, Krishna Prasad. "EMERGING MEMORY-BASED DESIGNS AND RESILIENCY TO RADIATION EFFECTS IN ICS". OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1863.

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The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..

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38

Vieira, Marco Manuel Santos. "PICSEL: Portable ICS Extensible Lab". Master's thesis, 2020. http://hdl.handle.net/10451/48330.

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Trabalho de projeto de mestrado, Segurança Informática, Universidade de Lisboa, Faculdade de Ciências, 2020
Critical infrastructures such as electric power grids, nuclear plants, oil and gas refineries, transportations systems or pharmaceutical industries, play an increasingly important role in our lives due to technological advancement and the precision industry. Traditionally, most of these infrastructures, also called industrial control systems (ICS), are large-scale cyber-physical systems (CPS) which all use supervisory control and data acquisition (SCADA). Over recent years, malicious actors have realized the importance and impact of these infrastructures. Combining this with the deprivation of security features in ICS resulted in a large quantity of high value targets just waiting to be exploited. Since these systems are based on equipment with a really long lifetime and, in most of the cases, have an extremely high availability requirement, its important to, somehow, gather information and perform security tests in order to protect these infrastructures, without compromising a live operation. Normally these infrastructures are very complex and often have a remarkable diversity of equipment, communication protocols and transmission technologies. This thesis presents a portable testbed, PICSEL, which was designed and developed to achieve the following goals: to be a portable testbed testing existing exploits and new security solutions whilst exploring new vulnerabilities within the equipment or the environment. Several requirements were considered in the design of the testbed: for instance, choosing the equipment that allowed for more environment configurations; choosing power supplies that support additional equipment; and designing a static electrical diagram based on each device’s requirements. With these requirements, the testbed must be able to support different types of equipment and architectures, allowing for applications in multiple industries, inside which it can be easily reconfigured. The thesis describes the testbed architecture and discusses the design decisions, presenting two test scenarios that were studied and implemented using PICSEL. In each of these test scenarios, different attacks were performed validating each of the PICSEL goals. Testing known vulnerabilities, testing exploits in the wild and exporting information from PICSEL equipment to an external tool were very important steps to validate the results. Therefore, this thesis provides proof of concept confirming the key value of a modular and reconfigurable testbed, PICSEL.

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39

Santos, Rodolfo Miguel Pinto Leite Brunner. "Desenho e implementação da plataforma ICS". Master's thesis, 2008. http://hdl.handle.net/10216/59610.

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Santos, Rodolfo Miguel Pinto Leite Brunner. "Desenho e implementação da plataforma ICS". Dissertação, 2008. http://hdl.handle.net/10216/59610.

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41

Nassif-Khalil, Sameh G. "Super junction LDMOSTs for smart power ICs". 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=94660&T=F.

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42

Küting, Jan Teichmann Peter. "Entwurf eines Demonstrator-ICs für HF-Baublöcke /". 2008. http://www.gbv.de/dms/ilmenau/abs/570375959kueti.txt.

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43

Ho, Cheng-Yeh y 何承曄. "A TSV Delay Meter for 3D ICs". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/82584110256095042380.

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碩士
國立交通大學
電子研究所
98
The manufacturing cost of the advanced process technology rises rapidly; on the other hand, the design complexity of modern designs also increases. To conquer the high cost of a large scale design, the stacked 3D IC is developed. Through-silicon-vias (TSVs) are widely used for vertical interconnection between layers in 3D ICs. Due to process variation, even when a signal passes through two different paths composed of the same series of TSVs, these two paths may incur a delay difference and affect the accuracy of a synchronous system. In this thesis, we present a TSV Delay Meter for calculating delay difference between two paths by HSpice with TSMC 90nm CMOS process. Our results show that the maximum resolution of the meter is about 0.74ps and the simulated delay errors are lower than 0.74ps as well. Hence, the TSV Delay Meter can precisely detect delay difference.

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44

Barreiros, Pedro Miguel França. "Exploring security controls for ICS/SCADA environments". Master's thesis, 2020. http://hdl.handle.net/10451/48398.

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Trabalho de projeto de mestrado, Segurança Informática, Universidade de Lisboa, Faculdade de Ciências, 2020
Os Sistemas de Controlo Industriais (ICS) estão a começar a fundir-se com as soluções de IT, por forma a promover a interconectividade. Embora isto traga inúmeros benefícios de uma perspetiva de controlo, os ICS apresentam uma falta de mecanismos de segurança que consigam evitar possíveis ameaças informáticas, quando comparados aos comuns sistemas de informação [29], [64]. Dada a natureza crítica destes sistemas, e a ocorrências recentes de ciberataques desastrosos, a segurança ´e um tópico que deve ser incentivado. À luz deste problema, na presente dissertação apresentamos uma avaliação de possíveis aplicações e controlos de segurança a serem implantados nestes ambientes críticos e a implementação de uma solução de segurança extensível que dá resposta a certos ataques focados em sistemas industriais, capaz de ser implantada em qualquer rede industrial que permita a sua ligação. Com o auxilio de uma framework extensivel e portátil para testes de ICS, e outros ambientes industriais de testes, foi possível analisar diferentes cenários de ameaças, implantar mecanismos de segurança para os detetar e avaliar os resultados, com o intuito de fornecer uma ideia de como empregar estes mecanismos da melhor maneira possível num ambiente real de controlo industrial.
Industrial Control Systems (ICS) are beginning to merge with IT solutions, in order to promote inter-connectivity. Although this brings countless benefits from a control perspective, ICS have been lacking in security mechanisms to ward off potential cyber threats, when compared to common information systems [29], [64]. Given the critical nature of these systems, and the recent occurrences of disastrous cyber-attacks, security is a topic that should be encouraged. In light of this problem, in this dissertation we present an assessment of possible security applications and controls that can be deployed in these critical environments and the implementation of an extensible security solution that responds to certain attacks focused on industrial systems, capable of being deployed in any industrial network that allows its connection. With the help of an extensible and portable framework for ICS testing, and other industrial testing environments, it was possible to analyze different threat scenarios, implement security mechanisms to detect them and evaluate the results in order to provide an idea on how to employ these mechanisms as best as possible in a real industrial control environment, without compromising it’s process.

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Correia, Ana Luísa Marques. "Adaptação portuguesa da ICS (Insomnia Catastrophizing Scale)". Master's thesis, 2019. http://hdl.handle.net/10773/29007.

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O objetivo da presente investigação foi realizar a primeira tradução e adaptação para o português europeu da ICS (Insomnia Catastrophizing Scale) de Jansson-Fröjmark, Harvey e Flink (2012, 2019), bem como a análise das suas propriedades psicométricas. A ICS avalia pensamentos catastróficos relacionados com sintomas de insónia na hora de dormir (ICS-N) e no funcionamento diurno (ICS-D). A ICS é composta por 17 itens avaliados numa escala de Likert de 0 a 5 pontos. No presente estudo recolheram-se dados de uma amostra comunitária de 802 participantes portugueses, com idades ≥ a 18 anos, sendo aproximadamente 80% do sexo feminino e 20% do sexo masculino. Os resultados demonstraram que a escala apresentou uma boa consistência interna tanto para a subescala ICS-N (α=0,93) como para a subescala ICS-D (α=0,95). A análise fatorial exploratória (Principal Axis Factoring) sugere a presença de um único fator para ambas as medidas. Verificou-se que as duas subescalas se correlacionam de forma elevada (r=0,79), sugerindo que medem construtos relacionados. Considerou-se que a variável sexo poderia moderar a relação entre a catastrofização e a gravidade da insónia. Neste estudo, encontrou-se correlações entre moderadas e fortes em ambos os sexos no que toca à associação quer da ICS-N, quer da ICS-D com a ISI (Insomnia Severity Index). Posteriormente, a amostra foi dividida em dois grupos, designados “insónia” (n=170) e “sem insónia” (n=632), através do ponto de corte da ISI proposto para a população portuguesa. Comparou-se os resultados médios totais entre os grupos e constatou-se que a ICS-N, comparativamente à ICS-D, apresentou uma magnitude de efeito ligeiramente mais elevada. Dentro de cada grupo (i.e., “insónia” versus “sem insónia”), nas respetivas subescalas, os valores médios foram mais elevados para o grupo “insónia”. Por último, calcularam-se curvas ROC (Receiver Operating Characteristics), tendo-se extraído pontos de corte com base na sensibilidade (ICS-N=75,9%; ICS-D=65,9%) e especificidade (ICS-N=75,6%; ICS-D=77,8%) ótimos. Em suma, os resultados obtidos apresentam semelhanças com os escassos estudos realizados até ao momento com a ICS, sendo que esta última parece constituir um instrumento de avaliação fiel e válido com potencialidade para uso no nosso país.
The aim of the current study was to develop the first translation and adaptation of the ICS (Insomnia Catastrophizing Scale) of Jansson-Fröjmark, Harvey and Flink (2012, 2019) into the European Portuguese, as well as to study its psychometric properties. The ICS evaluates the catastrophic thoughts related with insomnia symptoms during sleeping time (ICS-N) and during daytime functioning (ICS-D). Besides, the ICS comprises 17 items in a Likert scale ranging from 0 to 5 points. In this study, it was recruited a community-based sample of 802 Portuguese participants, aged ≥ 18 years, where approximately 80% of the sample were females and 20% males. The results showed that the scale has good internal consistency values for both the ICS-N (α=0,93) and ICS-D (α=0,95) subscales. The Principal Axis Factoring suggested the presence of a single factor in both measured scales. It was also observed a large correlation between the two subscales (r=0,79), suggesting that they measure related constructs. Additionally, it was considered that the gender variable could moderate the association between the catastrophization and insomnia severity. In this line, it was verified a moderate to large correlation coeficient among ICS-N and ICS-D and ISI (Insomnia Severity Index) for males and females. Posteriorly, the sample was divided in two groups labeled “Insomnia” (n=170) and “no Insomnia” (n=632). For that purpose, the cut-off point of 14 of the ISI - based on European Portuguese population - was used. For all the items of each one of the subscales, it was observed that “insomnia” individuals presented higher scores than “no insomnia” group. Finally, the ROC (Receiver Operating Characteristics) curves were computed for the subscales, extracting the cut-off points based on optimal sensitivity (ICS-N=75,9%; ICS-D=65,9%) and specificity ICS-N=75,6%; ICS-D=77,8%) values. Overall, these findings show similarities with the few published studies with ICS. The ICS seems to be a promising psychological assessment measure to be used in clinical and research settings.
Mestrado em Psicologia da Saúde e Reabilitação Neuropsicológica

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46

Cheng, Wen-Chieh y 鄭文傑. "PWM Controller ICs for DC-DC Converter". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/49547821618673899875.

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碩士
大葉大學
資訊工程學系碩士班
95
This thesis describes two complete PWM controller IC for switching power converters. One is analog PWM controller IC and another is digital PWM controller IC. Due to rapid development of CMOS technologies, more and more transistors can be fabricated on a single chip. Consumer electronic products also have been developed rapidly in these years. The power management ICs such as the highly efficient low-voltage switch-mode DC-DC converters are mandatory in these devices for maximizing the system run time. The analog-control scheme for the switching converters is developed for a long time, and it is a very mature technique. The digital-control scheme for the switching DC-DC converters also has been discussed in these years. The advantages and disadvantages between these two architectures are treated in this thesis. The key building blocks of analog PWM controller IC are two-stage operational amplifier, voltage-controlled oscillator and hysteretic comparator. The key building blocks of digital PWM controller IC are A/D converter, compensator and DPWM. These two controller ICs have been fabricated with TSMC 0.35um 2P4M 3.3V/5V Mixed Signal CMOS process through CIC. The chip size of APWM is about 0.35*0.37mm2. The chip size of A/D converter is about 0.555*0.555mm2. The chip size of DPWM is about 0.65*0.56mm2.

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47

Hsiao, Ching-Min y 蕭敬民. "Study of TFT-LCD Source Driver ICs". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/69684110095831438411.

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博士
國立暨南國際大學
電機工程學系
101
To improve the image quality of the display, high-resolution and high-color-depth source driver ICs are required. Achieving a higher resolution, more output channels of the source driver are needed. Extending color depth for the source driver requires high digital-to-analog converter’s (DAC’s) bit number, leading to an increase of DAC’s area. Since each output channel of the source driver needs one DAC, a source driver generally includes hundreds of DACs which occupy most silicon die size. Hence, there is a great demand for high-resolution, high-color-depth but low-cost source driver ICs. This study proposes three area-efficient DACs for LCD source driver ICs in different applications. For the small-size LCD panel, a quasi-pipeline DAC is proposed to implement a 9-bit source driver IC with high conversion rate. To minimize the charge injection error, we also utilize bootstrapped switches in the proposed DAC. Using 0.35-μm CMOS technology, a 30-channel source driver with quasi-pipeline DACs is implemented to validate the proposed DAC’s performance. The maximum DNL and INL are measured as 0.25 LSB and 0.33 LSB, respectively. The averaged data conversion time is 16 ns per channel. The Figure of Merit (FoM) of the proposed DAC is 0.2 pJ/bit-mm2, which is smaller (by a factor of 3-39) than that of prior arts. The measured results indicate that the proposed 9-bit quasi-pipeline DAC is highly suitable for small-format 16-million-color LCD source driver ICs. For the medium-size LCD application, we propose a 10-bit DAC with interpolation technique for compact LCD column driver ICs. The proposed DAC combines a 6-bit RDAC and a 4-bit DAC-embedded op with 1.6-bit current-mode interpolation cells. The 6-bit RDAC uses a one-voltage selector instead of a two-voltage selector; therefore, it requires a smaller silicon die area for the voltage selector than conventional ones. Fewer differential pairs are required for the voltage interpolation because the DAC-embedded op uses 1.6-bit interpolation cells with binary-weighted reference voltages. This reduces the silicon die area further. The 10-bit DAC prototype is realized in 0.35-μm CMOS technology with the worst DNL/INL of 0.45/0.93 LSB. The 10-bit DAC occupies only 64 % of the conventional 8-bit RDAC area. For the large-size LCD application, a 10-bit switched-capacitor voltage-summing DAC is introduced. This 10-bit DAC consists of a 3-bit RDAC and an 8-voltage switched-capacitor summer with high driving capability. The switched-capacitor summer adds up the output voltage of the 3-bit RDAC and the products of the input digital bit value and the corresponding binary-weighted voltage from bits 3 to 9. The 10-bit DAC prototype is realized using 0.35-μm/0.5-μm CMOS technology, with the worst-case DNL/INL at 0.76/1.56 LSB. The die area per channel is 35 μm × 410 μm, which is more compact than state-of-the-art circuits implemented with the same technology. The settling time to reach 0.2% tolerance of the final voltage is only 5 μs, smaller than that of previous switched-capacitor (cyclic) DACs.

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48

De, Paola Francesco Maria. "Silicon as Smart Package for Photonic ICs". Tesi di dottorato, 2003. http://www.fedoa.unina.it/123/1/De_Paola.pdf.

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In this thesis, the research is described for realizing hybrid modules where silicon can be used to effectively improve different functionalities of the photonic device. Several aspect are detailed, spanning from the techology to implement the hybrid modules to the description of some particular photonic devices that might improve their performance when mounted onto a silicon carrier. Also, some considerations about different amplifier architectures for optical communications are presented and completed with practical implementations in an advanced university bipolar process.

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49

Yao, Terry. "Transmitter front-end ICs for 60-GHz radio". 2006. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=442049&T=F.

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Ayazianmavi, Sahar. "Photovoltaic (PV) and fully-integrated implantable CMOS ICs". Thesis, 2012. http://hdl.handle.net/2152/ETD-UT-2012-05-5527.

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Today, there is an ever-growing demand for compact, and energy autonomous, implantable biomedical sensors. These devices, which continuously collect in vivo physiological data, are imperative in the next generation patient monitoring systems. One of the fundamental challenges in their implementation, besides the obvious size constraints and the tissue-to-electronics biocompatibility impediments, is the efficient means to wirelessly deliver power to them. This work addresses this challenge by demonstrating an energy-autonomous and fully-integrated implantable sensor chip which takes advantage of the existing on-chip photodiodes of a standard CMOS process as photovoltaic (PV) energy-harvesting cells. This 2.5 mm × 2.5 mm chip is capable of harvesting [mu]W’s of power from the ambient light passing through the tissue and performing real-time sensing. This system is also MRI compatible as it includes no magnetic material and requires no RF coil or antennae. In this dissertation, the optical properties of tissue and the capabilities of the CMOS integrated PV cells are studied first. Next, the implementation of an implantable sensor using such PV devices is discussed. The sensor characterizing and the in vitro measurement results using this system, demonstrate the feasibility of monolithically integrated CMOS PV-driven implantable sensors. In addition, they offer an alternative method to create low-cost and mass-deployable energy autonomous ICs in biomedical applications and beyond.
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