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Artículos de revistas sobre el tema "High level Synthesi"

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Publicado: 14 de marzo de 2023

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1

Rajan, S. P., M. Fujita, K. Yuan y M. T.-C. Lee. "ATM switch design by high-level modeling, formal verification and high-level synthesi". ACM Transactions on Design Automation of Electronic Systems 3, n.º 4 (octubre de 1998): 554–62. http://dx.doi.org/10.1145/296333.296342.

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2

Yang, Hae-Chan, Sang-Jun Park, Kwoan-Young Park, Jae-Hyun Sa y Tae-Hwan Kim. "High-level Synthesis Design and Implementation of an Efficient Capsule Network Inference System in an FPGA". Journal of the Institute of Electronics and Information Engineers 58, n.º 11 (30 de noviembre de 2021): 39–47. http://dx.doi.org/10.5573/ieie.2021.58.11.39.

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3

Bolton, Martin. "High-level synthesis". Microprocessors and Microsystems 18, n.º 8 (octubre de 1994): 489. http://dx.doi.org/10.1016/0141-9331(94)90097-3.

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4

Pawlak, Adam. "High-level synthesis". Microprocessing and Microprogramming 35, n.º 1-5 (septiembre de 1992): 261. http://dx.doi.org/10.1016/0165-6074(92)90325-2.

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5

YAMAMOTO, Takahiro. "Safety assessment of high-level nuclear waste disposal in Japan from the standpoint of geology". Synthesiology English edition 4, n.º 4 (2012): 202–11. http://dx.doi.org/10.5571/syntheng.4.202.

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6

Ravi, Selvaraj y M. Joseph. "High-Level Test Synthesis". ACM Transactions on Design Automation of Electronic Systems 19, n.º 4 (agosto de 2014): 1–27. http://dx.doi.org/10.1145/2627754.

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7

Ewering, Christian y Gunter Gerhardt. "PASS: High level synthesis". Microprocessing and Microprogramming 30, n.º 1-5 (agosto de 1990): 103–8. http://dx.doi.org/10.1016/0165-6074(90)90225-x.

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8

Xing, Xianwu y Ching Chuen Jong. "Floorplan-Driven Multivoltage High-Level Synthesis". VLSI Design 2009 (6 de septiembre de 2009): 1–10. http://dx.doi.org/10.1155/2009/156751.

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As the semiconductor technology advances, interconnect plays a more and more important role in power consumption in VLSI systems. This also imposes a challenge in high-level synthesis, in which physical information is limited and conventionally considered after high-level synthesis. To close the gap between high-level synthesis and physical implementation, integration of physical synthesis and high-level synthesis is essential. In this paper, a technique named FloM is proposed for integrating floorplanning into high-level synthesis of VLSI system with multivoltage datapath. Experimental results obtained show that the proposed technique is effective and the energy consumed by both the datapath and the wires can be reduced by more than 40%.
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9

Dossis, M. "High-level Synthesis Integrated Verification". Engineering, Technology & Applied Science Research 5, n.º 5 (4 de octubre de 2015): 864–70. http://dx.doi.org/10.48084/etasr.596.

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It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.
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10

Gajski, D. D. y L. Ramachandran. "Introduction to high-level synthesis". IEEE Design & Test of Computers 11, n.º 4 (1994): 44–54. http://dx.doi.org/10.1109/54.329454.

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11

Paulin, P. G. y J. P. Knight. "Algorithms for high-level synthesis". IEEE Design & Test of Computers 6, n.º 6 (diciembre de 1989): 18–31. http://dx.doi.org/10.1109/54.41671.

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12

Rosenstiel, Wolfgang. "Optimizations in high level synthesis". Microprocessing and Microprogramming 18, n.º 1-5 (diciembre de 1986): 347–52. http://dx.doi.org/10.1016/0165-6074(86)90063-3.

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13

Zhenyu Gu, Jia Wang, R. P. Dick y Hai Zhou. "Unified Incremental Physical-Level and High-Level Synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, n.º 9 (septiembre de 2007): 1576–88. http://dx.doi.org/10.1109/tcad.2007.895780.

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14

Van Meerbergen, J. L., P. E. R. Lippens, W. F. J. Verhaegh y A. Van Der Werf. "PHIDEO: High-level synthesis for high throughput applications". Journal of VLSI signal processing systems for signal, image and video technology 9, n.º 1-2 (enero de 1995): 89–104. http://dx.doi.org/10.1007/bf02406472.

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15

Nishikawa, Hiroki, Kenta Shirane, Ryohei Nozaki, Ittetsu Taniguchi y Hiroyuki Tomiyama. "Function‐level module sharing techniques in high‐level synthesis". ETRI Journal 42, n.º 4 (agosto de 2020): 527–33. http://dx.doi.org/10.4218/etrij.2020-0107.

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16

Zheng, Hongbin, Swathi T. Gurumani, Liwei Yang, Deming Chen y Kyle Rupnow. "High-Level Synthesis With Behavioral-Level Multicycle Path Analysis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, n.º 12 (diciembre de 2014): 1832–45. http://dx.doi.org/10.1109/tcad.2014.2361661.

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17

Herklotz, Yann, James D. Pollard, Nadesh Ramanathan y John Wickerson. "Formal verification of high-level synthesis". Proceedings of the ACM on Programming Languages 5, OOPSLA (20 de octubre de 2021): 1–30. http://dx.doi.org/10.1145/3485494.

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High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.
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18

Lyuh, C. G., T. Kim y K. W. Kim. "Coupling-Aware High-Level Interconnect Synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 1 (enero de 2004): 157–64. http://dx.doi.org/10.1109/tcad.2003.819892.

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19

Kundu, Sudipta, Sorin Lerner y Rajesh K. Gupta. "Translation Validation of High-Level Synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, n.º 4 (abril de 2010): 566–79. http://dx.doi.org/10.1109/tcad.2010.2042889.

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20

Coussy, Philippe y Andres Takach. "Special Issue on High-Level Synthesis". IEEE Design & Test of Computers 25, n.º 5 (septiembre de 2008): 393. http://dx.doi.org/10.1109/mdt.2008.147.

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21

Coussy, P., D. D. Gajski, M. Meredith y A. Takach. "An Introduction to High-Level Synthesis". IEEE Design & Test of Computers 26, n.º 4 (julio de 2009): 8–17. http://dx.doi.org/10.1109/mdt.2009.69.

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22

Coussy, Philippe, Ghizlane Lhairech-Lebreton y Dominique Heller. "Multiple Word-Length High-Level Synthesis". EURASIP Journal on Embedded Systems 2008, n.º 1 (2008): 916867. http://dx.doi.org/10.1155/2008/916867.

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23

Georgakakis, Spyridon y John Evans. "Overview of high level synthesis tools". Journal of Instrumentation 6, n.º 02 (18 de febrero de 2011): C02005. http://dx.doi.org/10.1088/1748-0221/6/02/c02005.

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24

Prihozhy, A. "Net scheduling in high-level synthesis". IEEE Design & Test of Computers 13, n.º 1 (1996): 26–35. http://dx.doi.org/10.1109/54.485780.

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25

Lin, Colin Yu, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So y Haigang Yang. "FPGA High-level Synthesis versus Overlay". ACM SIGARCH Computer Architecture News 44, n.º 4 (11 de enero de 2017): 92–97. http://dx.doi.org/10.1145/3039902.3039919.

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26

Ghosh, Indradeep y Niraj K. Jha. "High-level test synthesis: a survey". Integration 26, n.º 1-2 (diciembre de 1998): 79–99. http://dx.doi.org/10.1016/s0167-9260(98)00022-4.

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27

Ismaeel, A. A., R. Bhatnagar y R. Mathew. "Concurrent testing in high level synthesis". Microelectronics Reliability 40, n.º 12 (diciembre de 2000): 2095–106. http://dx.doi.org/10.1016/s0026-2714(00)00028-7.

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28

Lakshminarayana, G., A. Raghunathan, N. K. Jha y S. Dey. "Power management in high-level synthesis". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7, n.º 1 (marzo de 1999): 7–15. http://dx.doi.org/10.1109/92.748195.

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29

Winterstein, Felix J., Samuel R. Bayliss y George A. Constantinides. "Separation Logic for High-Level Synthesis". ACM Transactions on Reconfigurable Technology and Systems 9, n.º 2 (3 de febrero de 2016): 1–23. http://dx.doi.org/10.1145/2836169.

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30

Lin, Youn-Long. "Recent developments in high-level synthesis". ACM Transactions on Design Automation of Electronic Systems 2, n.º 1 (enero de 1997): 2–21. http://dx.doi.org/10.1145/250243.250245.

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31

Keinprasit, Rachaporn y Prabhas Chongstitvatana. "High-level synthesis by dynamic ant". International Journal of Intelligent Systems 19, n.º 1-2 (enero de 2004): 25–38. http://dx.doi.org/10.1002/int.10148.

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32

TATSUOKA, Masato y Mineo KANEKO. "High Level Congestion Detection from C/C++ Source Code for High Level Synthesis". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, n.º 12 (1 de diciembre de 2020): 1437–46. http://dx.doi.org/10.1587/transfun.2020vlp0012.

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33

Verdier, François S. y Bertrand Zavidovique. "A High Level Synthesis System for VLSI Image Processing Applications". VLSI Design 7, n.º 4 (1 de enero de 1998): 321–36. http://dx.doi.org/10.1155/1998/95421.

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We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a “front-end” data-flow emulator for validation of the algorithms and the RTL-synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the “restricted” domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data-path synthesis (scheduling and module selection) and then for control synthesis and data-path completion (binding). An interesting feature of the first optimization is the use of the data-flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.
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34

Aytekin, Metin, Suzy A. A. Comhair, Carol de la Motte, Sudip K. Bandyopadhyay, Carol F. Farver, Vincent C. Hascall, Serpil C. Erzurum y Raed A. Dweik. "High levels of hyaluronan in idiopathic pulmonary arterial hypertension". American Journal of Physiology-Lung Cellular and Molecular Physiology 295, n.º 5 (noviembre de 2008): L789—L799. http://dx.doi.org/10.1152/ajplung.90306.2008.

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Hyaluronan (HA), a large glycosaminoglycan found in the ECM, has major roles in lung and vascular biology and disease. However, its role in idiopathic pulmonary arterial hypertension (IPAH) is unknown. We hypothesized that HA metabolism is abnormal in IPAH. We measured the plasma levels of HA in IPAH and healthy individuals. We also evaluated HA synthesis and the expression of HA synthases and hyaluronidases in pulmonary artery smooth muscle cells (PASMCs) from explanted lungs. Plasma HA levels were markedly elevated in IPAH compared with controls [HA (ng/ml, mean ± SD): IPAH 325 ± 80, control 28 ± 9; P = 0.02]. In vitro, unstimulated IPAH PASMCs produced high levels of HA compared with control cells [HA in supernatant (μg/ml, mean ± SD): IPAH 12 ± 2, controls 6 ± 0.9; P = 0.04]. HA levels were also higher in IPAH PASMC lysates. The increased HA was biologically relevant as shown by tissue staining and increased HA-specific binding of mononuclear cells to IPAH compared with control PASMCs [number of bound cells × 104 (mean ± SD): IPAH 9.5 ± 3, control 3.0 ± 1; P = 0.01]. This binding was abrogated by the addition of hyaluronidase. HA synthase-2 and hyaluronidase-2 were predominant in control and IPAH PASMCs. Interestingly, the expressions of HA synthase-2 and hyaluronidase-2 were ∼2-fold lower in IPAH compared with controls [HA synthase-2 (relative expression mean ± SE): IPAH 4.3 ± 0.02, control 7.8 ± 0.1; P = 0.0004; hyaluronidase-2 (relative expression mean ± SE): IPAH 4.2 ± 0.06, control 7.6 ± 0.07; P = 0.008]. Thus patients with IPAH have higher circulating levels of HA, and PASMCs derived from IPAH lungs produce more HA compared with controls. This is associated with increased tissue levels and increased binding of inflammatory cells suggesting a role for HA in remodeling and inflammation in IPAH.
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35

Pilászy, György, György Rácz y Péter Arató. "Communication Time Estimation in High Level Synthesis". Periodica Polytechnica Electrical Engineering 57, n.º 4 (2013): 99. http://dx.doi.org/10.3311/ppee.7413.

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36

Zhang, Zhiru, Deming Chen, Steve Dai y Keith Campbell. "High-level Synthesis for Low-power Design". IPSJ Transactions on System LSI Design Methodology 8 (2015): 12–25. http://dx.doi.org/10.2197/ipsjtsldm.8.12.

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37

Su, Fei y Krishnendu Chakrabarty. "High-level synthesis of digital microfluidic biochips". ACM Journal on Emerging Technologies in Computing Systems 3, n.º 4 (enero de 2008): 1–32. http://dx.doi.org/10.1145/1324177.1324178.

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38

Wang, W., A. Raghunathan, N. K. Jha y S. Dey. "Resource Budgeting for Multiprocess High-Level Synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 7 (julio de 2004): 1010–19. http://dx.doi.org/10.1109/tcad.2004.829806.

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39

Lin Zhong y N. K. Jha. "Interconnect-aware low-power high-level synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, n.º 3 (marzo de 2005): 336–51. http://dx.doi.org/10.1109/tcad.2004.842820.

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40

Andriamisaina, Caaliph, Philippe Coussy, Emmanuel Casseau y Cyrille Chavet. "High-Level Synthesis for Designing Multimode Architectures". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, n.º 11 (noviembre de 2010): 1736–49. http://dx.doi.org/10.1109/tcad.2010.2062751.

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41

Ly, T. A. y J. T. Mowchenko. "Applying simulated evolution to high level synthesis". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, n.º 3 (marzo de 1993): 389–409. http://dx.doi.org/10.1109/43.215002.

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42

Martin, G. y G. Smith. "High-Level Synthesis: Past, Present, and Future". IEEE Design & Test of Computers 26, n.º 4 (julio de 2009): 18–25. http://dx.doi.org/10.1109/mdt.2009.83.

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43

Sarkar, S., S. Dabral, P. K. Tiwari y R. S. Mitra. "Lessons and Experiences with High-Level Synthesis". IEEE Design & Test of Computers 26, n.º 4 (julio de 2009): 34–45. http://dx.doi.org/10.1109/mdt.2009.84.

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44

Yuan Xie y Yibo Chen. "Statistical High-Level Synthesis under Process Variability". IEEE Design & Test of Computers 26, n.º 4 (julio de 2009): 78–87. http://dx.doi.org/10.1109/mdt.2009.85.

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45

Roy, J., N. Kumar, R. Dutta y R. Vemuri. "DSS: a distributed high-level synthesis system". IEEE Design & Test of Computers 9, n.º 2 (junio de 1992): 18–32. http://dx.doi.org/10.1109/54.143143.

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46

Camposano, R. "From behavior to structure: high-level synthesis". IEEE Design & Test of Computers 7, n.º 5 (octubre de 1990): 8–19. http://dx.doi.org/10.1109/54.60603.

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47

Ernst, R. y J. Bhasker. "Simulation-based verification for high-level synthesis". IEEE Design & Test of Computers 8, n.º 1 (marzo de 1991): 14–20. http://dx.doi.org/10.1109/54.75659.

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48

Camposano, R., L. F. Saunders y R. M. Tabet. "VHDL as input for high-level synthesis". IEEE Design & Test of Computers 8, n.º 1 (marzo de 1991): 43–49. http://dx.doi.org/10.1109/54.75662.

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49

Lavagno, Luciano. "What is ECO for high-level synthesis?" ACM SIGDA Newsletter 39, n.º 12 (diciembre de 2009): 1. http://dx.doi.org/10.1145/1862885.1862886.

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50

Bergamaschi, R. A., R. A. O'Connor, L. Stok, M. Z. Moricz, S. Prakash, A. Kuehlmann y D. S. Rao. "High-level synthesis in an industrial environment". IBM Journal of Research and Development 39, n.º 1.2 (enero de 1995): 131–48. http://dx.doi.org/10.1147/rd.391.0131.

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