Tesis sobre el tema "High level Synthesi"
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Amarasinghe, V. Kosala I. "Distributed high-level synthesis". Thesis, University of Southampton, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438696.
Texto completoLanger, Jan. "High-Level-Synthese von Operationseigenschaften". Doctoral thesis, Universitätsbibliothek Chemnitz, 2011. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-79059.
Texto completoThe complete verification approach using special operation properties is an accepted methodology for the formal verification of digital circuits. Operation properties describe the behavior of a circuit during a certain time interval. They can be sequentially concatenated in order to specify the overall behavior. Additionally, a formal completeness check proves that the sequence of properties consistently determines the exact value of the output signals for every valid sequence of input signal values. This work examines how a circuit description can be automatically derived from a set of operation properties whose completeness has been proven. In contrast to the traditional design flow at register-transfer level (RTL), this method offers two advantages. First, the prove of completeness helps to avoid many design errors. Second, the design of operation properties resembles the design of timing diagrams often used in textual specifications. Therefore, the design level is closer to the specification level and errors caused by refinement steps are avoided. The design tool vhisyn performs the high-level synthesis from a complete set of operation properties to a description at RTL. The results show that both the synthesis algorithms and the generated circuit descriptions are efficient and allow the design of larger applications. This is demonstrated by means of two case studies
Baidas, Zaher Abdulkarim. "High-level floating-point synthesis". Thesis, University of Southampton, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.325049.
Texto completoAbbas, Naeem. "Acceleration of a bioinformatics application using high-level synthesis". Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2012. http://tel.archives-ouvertes.fr/tel-00847076.
Texto completoLawrence, Bleddyn Idris. "High level synthesis with interconnect prediction". Thesis, University of Southampton, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.437114.
Texto completoYeung, Ping F. "High-level synthesis of VLSI circuits". Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/11647.
Texto completoFallside, Hamish. "High level synthesis of memory architectures". Thesis, University of Edinburgh, 1995. http://hdl.handle.net/1842/10882.
Texto completoFinlay, Iain William. "High-level synthesis using structural input". Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/14849.
Texto completoSchmidt, Marco, Ulrich Möhrke y Paul Herrmann. "Verhaltensbeschreibung in der High-Level Synthese". Universität Leipzig, 1996. https://ul.qucosa.de/id/qucosa%3A34506.
Texto completoUguen, Yohann. "High-level synthesis and arithmetic optimizations". Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI099.
Texto completoHigh-level synthesis (HLS) tools offer increased productivity regarding FPGA programming. However, due to their relatively young nature, they still lack many arithmetic optimizations. This thesis proposes safe arithmetic optimizations that should always be applied. These optimizations are simple operator specializations, following the C semantic. Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio. To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated. In some cases, there is not enough information about the input data to tailor the fixed-point accumulator. The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range. This thesis explores different strategies for implementing such a large accumulator, including new ones. The use of a 2's complement representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay. Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format. A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators. Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance. Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools. This library implements a strongly typed custom size integer type along side a set of optimized custom operators
Winterstein, Felix. "Separation logic for high-level synthesis". Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/33371.
Texto completoGremzow, Carsten. "High-Level-Synthese aus flachen Kontroll-/Datenflussgraphen". [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=970644744.
Texto completoTOMIYAMA, Hiroyuki, Hiroyuki KANBARA, Yoshiyuki ISHIMORI, Nagisa ISHIURA y Masanari NISHIMURA. "High-Level Synthesis of Software Function Calls". Institute of Electronics, Information and Communication Engineers, 2008. http://hdl.handle.net/2237/15044.
Texto completoWang, Xiaojun. "An interactive, high-level logic synthesis system". Thesis, Staffordshire University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387386.
Texto completoPatterson, Isaac. "Trustworthy system development through high-level synthesis". Thesis, Monterey, California: Naval Postgraduate School, 2014. http://hdl.handle.net/10945/43974.
Texto completoMajor processor manufacturers have embraced the high-level synthesis (HLS) design philosophy. HLS offers the potential to explore the design space of electronic circuits and systems more efficiently than traditional methods. In this thesis, we investigate the ap-plication of HLS to hardware-oriented security and trust by developing a model of a simple 16-bit Central Processing Unit in the SystemC modeling language. We enhanced our processor with a simple security mechanism that enforces a memory integrity policy. The integrity policy allows a region of the program labeled as trustworthy to modify any address in data memory, but another region of the program labeled as untrustworthy is restricted to only being able to modify a specific region of data memory. Our timing results show that adding the integrity policy enforcement mechanism has a negligible effect on overall system performance.
Collis, G. V. "A prototype high level hardware synthesis system". Thesis, University of Manchester, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234891.
Texto completoOikonomakos, Petros. "High-level synthesis for on-line testability". Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.414359.
Texto completoLiu, Junyi. "Parametric polyhedral optimisation for high-level synthesis". Thesis, Imperial College London, 2017. http://hdl.handle.net/10044/1/64814.
Texto completoMahmood, Hassan. "Crest Factor Reduction using High Level Synthesis". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229437.
Texto completoAnvändning av högnivåsyntes för reduktion av toppfaktor Det har gjorts noterbara framsteg inom modern trådlös kommunikationsteknik för mobiltelefoni, men tekniken plågas fortfarande av dålig energieffektivitet hos förstärkarna i dagens basstationer. En faktor som påverkar energieffektiviteten negativt är om signaler har en stor skillnad mellan maximal effekt och medeleffekt. Kvoten mellan maximal effekt och medeleffekt kallas för toppfaktor, och en egenskap hos moderna moduleringstekniker, såsom ortogonal frekvensdelningsmodulering, är att de har en hög toppfaktor. Algoritmer för reducering av toppfaktor kan lösa det problemet. Den dominerande metoden för design av hårdvara är att skriva kod i ett hårdvarubeskrivande språk med abstraktionsnivån Register Transfer Level och sedan använda verktyg för att syntetisera hårdvara från koden. Resultatet är en specifik implementation som inte nödvändigtvis är den optimala lösningen. Det här examensarbetet är inriktat på att utveckla ett system för reducering av toppfaktor, baserat på algoritmen Peak Cancellation, genom att skriva kod i ett högnivåspråk och använda verktyg för högnivåsyntes för att syntetisera designen. Syftet är att ta reda på om högnivåsyntes som designmetod kan ge ökad produktivitet och ökad kvalitet, för den här typen av design, jämfört med den klassiska designmetoden med abstraktionsnivån Register Transfer Level. Verktyget för högnivåsyntes användes för att på ett effektivt sätt undersöka olika designalternativ för att optimera kretsytan. I rapporten presenteras ett antal parametrar för att mäta prestandan hos systemet, vilket ger information som kan användas för finjustering. Resultatet av undersökningen av designalternativ gjorde det möjligt att välja den bästa implementationen bland fyra olika konfigurationer. Den slutgiltiga implementationen hade en kretsyta som är jämförbar med en tidigare design som implementerats med hårdvarubeskrivande språk med abstraktionsnivån Register Transfer Level. En annan slutsats är att, för den här designen, så gav designmetoden med högnivåsyntes ökad produktivitet och minskad designtid.
Xiao, Chenglong. "Custom operator identification for high-level synthesis". Rennes 1, 2012. http://www.theses.fr/2012REN1E005.
Texto completoIt is increasingly common to see custom operators appear in various fields of circuit design. Custom operators that can be implemented in special hardware units make it possible to reduce code size, improve performance and reduce area. In this thesis, we propose a design flow based on custom operator identification for high-level synthesis. The key issues involved in the design flow are: automatic enumeration and selection of custom operators from a given high-level application code and re-generation of the source code incorporating the selected custom operators. Unlike the previously proposed approaches, our design flow is quite adaptable and is independent of high-level synthesis tools (i. E. , without modifying the scheduling and binding algorithms in high-level synthesis tools). Experimental results show that our approach achieves on average 19%, and up to 37% area reduction, compared to a traditional high-level synthesis. Meanwhile, the latency is reduced on average by 22%, and up to 59%. Furthermore, on average 74% and up to 81% code size reduction can be achieved
Hänninen, T. (Tony). "Intelin High Level Synthesis Compiler -ohjelman ominaisuudet". Bachelor's thesis, University of Oulu, 2019. http://jultika.oulu.fi/Record/nbnfioulu-201905141748.
Texto completoJoshi, Manasi. "On Reverse Engineering of Encrypted High Level Synthesis Designs". University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049.
Texto completoHUANG, RENQIU. "PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs". University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.
Texto completoNourani-Dargiri, Mehrdad. "Area and delay estimation for constraint-driven high-level synthesis". Case Western Reserve University School of Graduate Studies / OhioLINK, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=case1057603424.
Texto completoTran, Mai-Thanh. "Towards hardware synthesis of a flexible radio from a high-level language". Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S072/document.
Texto completoSoftware defined radio (SDR) is a promising technology to tackle flexibility requirements of new generations of communication standards. It can be easily reprogrammed at a software level to implement different waveforms. When relying on a software-based technology such as microprocessors, this approach is clearly flexible and quite easy to design. However, it usually provides low computing capability and therefore low throughput performance. To tackle this issue, FPGA technology turns out to be a good alternative for implementing SDRs. Indeed, FPGAs have both high computing power and reconfiguration capacity. Thus, including FPGAs into the SDR concept may allow to support more waveforms with more strict requirements than a processor-based approach. However, main drawbacks of FPGA design are the level of the input description language that basically needs to be the hardware level, and, the reconfiguration time that may exceed run-time requirements if the complete FPGA is reconfigured. To overcome these issues, this PhD thesis proposes a design methodology that leverages both high-level synthesis tools and dynamic reconfiguration. The proposed methodology is a guideline to completely build a flexible radio for FPGA-based SDR, which can be reconfigured at run-time
Namvar, Gharehshiran Amir. "High Level Synthesis Evaluation of Tools and Methodology". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177362.
Texto completoGhatraju, Lakshmikanth. "Frontiers for high-level synthesis of digital circuits". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq24073.pdf.
Texto completoHettiaratchi, Sambuddhi Sinha Bandara. "Power optimized memory access in high-level synthesis". Thesis, Imperial College London, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.407906.
Texto completoBaguma, Gerald. "High Level Synthesis of FPGA-Based Digital Filters". Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-232414.
Texto completoZiyuan, Jiang. "Synthesis of GPU Programs from High-Level Models". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230163.
Texto completoModerna grafikbehandlingsenheter (GPU) tillhandahåller högpresterande generella syftes-beräkningsförmågor. De har massiva parallella arkitekturer som är lämpliga för att utföra parallella algoritmer och operationer. De är också streaminriktade enheter som är optimerade för att uppnå hög streaming för streamingbehandling. Att utforma effektiva GPU-program är en notoriskt svårt uppgift. ForSyDe-metoden är lämplig för att underlätta svårigheterna med GPU-programmering. Metodiken uppmuntrar mjukvaruutveckling från en hög nivå av abstraktion för att sedan omvandla den abstrakta modellen till en implementering genom en rad formella metoder. De befintliga ForSyDe-modellerna stöder synkron dataflöde (SDF) modell av beräkning (MoC) som är lämplig för modellering av streaming-beräkningar och är bra för att syntetisera effektiv streaming-bearbetningsprogram. Det finns också högkvalitativa designmodeller som kallas parallella mönster vilka är lämpliga för att representera parallella algoritmer och operationer. Avhandlingen analyserar metoden för modellering av parallella algoritmer med parallella mönster, och utforskar sättet att syntetisera effektiv OpenCL-implementering för GPU för parallella mönster. Avhandlingen försöker även att möjliggöra integration av parallella mönster i ForSyDe SDF-modellen för att modellera streaming parallella operationer. Ett automationsbibliotek som hjälper till att designa stream-program för parallella algoritmer som riktar sig mot GPU:er är avsedda för avhandlingsprojektet. Flera experiment utförs för att utvärdera effektiviteten hos det föreslagna biblioteket avseende implementering av högnivåmodellen.
Lim, Stephen E. L. "A high-level methodology for VHDL-based synthesis". Thesis, University of Aberdeen, 1992. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU047338.
Texto completoOUAISS, IYAD. "HIERARCHICAL MEMORY SYNTHESIS IN RECONFIGURABLE COMPUTERS". University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1033498452.
Texto completoHemmert, Karl S. "Source Level Debugging of Circuits Synthesized from High Level Language Descriptions". Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd405.pdf.
Texto completoAsthana, Rohit Mohan. "High-Level CSP Model Compiler for FPGAs". Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36428.
Texto completoMaster of Science
Ellervee, Peeter. "High-level synthesis of control and memory intensive applications". Doctoral thesis, KTH, Electronic Systems Design, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2929.
Texto completoBeikzadeh, Mohammad Reza. "Automatic high-level synthesis based upon artificial intelligence techniques". Thesis, University of Essex, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315691.
Texto completoNijhar, Tajinder Pal Kaur. "Source code optimisation in a high level synthesis system". Thesis, University of Southampton, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242110.
Texto completoAhmadi, Arash. "An investigation of high level synthesis for computational hardware". Thesis, University of Southampton, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.443050.
Texto completoGao, Xitong. "Structural optimization of numerical programs for high-level synthesis". Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/42498.
Texto completoDuncan, Andrew A. "High level synthesis for an area efficient datapath architecture". Thesis, University of Aberdeen, 1994. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU069038.
Texto completoJelodari, Mamaghani Mahdi. "High-level synthesis of elasticity : from models to circuits". Thesis, University of Manchester, 2016. https://www.research.manchester.ac.uk/portal/en/theses/highlevel-synthesis-of-elasticity-from-models-to-circuits(7d881d3e-b90a-4ec3-9caa-67524d3bd34b).html.
Texto completoSIVA, SUBRAMANYAN D. "APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS". University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893.
Texto completoAli, Baraa Saeed. "HIGH LEVEL SYNTHSIS FOR A NETWORK ON CHIP TOPOLOGY". OpenSIUC, 2013. https://opensiuc.lib.siu.edu/theses/1079.
Texto completoKrishnan, Vyas. "Temperature and interconnect aware unified physical and high level synthesis". [Tampa, Fla] : University of South Florida, 2008. http://purl.fcla.edu/usf/dc/et/SFE0002785.
Texto completoPinilla, Jose Pablo. "Source-level instrumentation for in-system debug of high-level synthesis designs for FPGA". Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59380.
Texto completoApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
MANSOURI, NAZANIN. "AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS". University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.
Texto completoFarahini, Nasim. "SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms : Toward Next Generation Hardware Synthesis Methodologies". Doctoral thesis, KTH, Elektronik och Inbyggda System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-185787.
Texto completoAraujo, Barrientos Antonio. "Implementation of a High Performance Embedded MPC on FPGA using High-Level Synthesis". Master's thesis, Pontificia Universidad Católica del Perú, 2017. http://tesis.pucp.edu.pe/repositorio/handle/123456789/8899.
Texto completoTesis
Isaksson, Johan. "FPGA-Accelerated Image Processing Using High Level Synthesis with OpenCL". Thesis, Linköpings universitet, Datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143213.
Texto completoMansour, Omar. "High level synthesis for non-manifest digital signal processing applications". Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/51107.
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