Bibliografías temáticas / Hardware Model Checking / Artículos de revistas

Artículos de revistas sobre el tema "Hardware Model Checking"

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Publicado: 14 de marzo de 2023

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1

Pixley, Carl y Vigyan Singhal. "Model checking: a hardware design perspective". International Journal on Software Tools for Technology Transfer (STTT) 2, n.º 3 (1 de noviembre de 1999): 288–306. http://dx.doi.org/10.1007/s100090050036.

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2

Gong, Wei y Jun Wei Jia. "Comparison of Model Checking Tools". Advanced Materials Research 659 (enero de 2013): 181–85. http://dx.doi.org/10.4028/www.scientific.net/amr.659.181.

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Model Checking is a method for verification. The model will be checked until the specification of it is proved or disproved. With the rising complexity of big models, there are non-checkable cases, in which cases the problem can be analyzed by some models, for example, bounded Model Checking means to analyze the model until a defined time or depth. The verification happens automatically. The programs for doing this are called Model Checking Tools or Model Checker. Model Checking are used in both software and hardware verification. It is an inherent part of hardware verification, whereas it is less used in the software verification.
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3

Vasudevan, Shobha, E. Allen Emerson y Jacob A. Abraham. "Efficient Model Checking of Hardware Using Conditioned Slicing". Electronic Notes in Theoretical Computer Science 128, n.º 6 (mayo de 2005): 279–94. http://dx.doi.org/10.1016/j.entcs.2005.04.017.

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4

Moiseenko, Evgenii, Michalis Kokologiannakis y Viktor Vafeiadis. "Model checking for a multi-execution memory model". Proceedings of the ACM on Programming Languages 6, OOPSLA2 (31 de octubre de 2022): 758–85. http://dx.doi.org/10.1145/3563315.

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Multi-execution memory models, such as Promising and Weakestmo, are an advanced class of weak memory consistency models that justify certain outcomes of a concurrent program by considering multiple candidate executions collectively. While this key characteristic allows them to support effective compilation to hardware models and a wide range of compiler optimizations, it makes reasoning about them substantially more difficult. In particular, we observe that Promising and Weakestmo inhibit effective model checking because they allow some suprisingly weak behaviors that cannot be generated by examining one execution at a time. We therefore introduce Weakestmo2, a strengthening of Weakestmo by constraining its multi-execution nature, while preserving the important properties of Weakestmo: DRF theorems, compilation to hardware models, and correctness of local program transformations. Our strengthening rules out a class of surprisingly weak program behaviors, which we attempt to characterize with the help of two novel properties: load buffering race freedom and certification locality. In addition, we develop WMC, a model checker for Weakestmo2 with performance close to that of the best tools for per-execution models.
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5

Li, Dejian, Qizhi Zhang, Dongyan Zhao, Lei Li, Jiaji He, Yidong Yuan y Yiqiang Zhao. "Hardware Trojan Detection Using Effective Property-Checking Method". Electronics 11, n.º 17 (24 de agosto de 2022): 2649. http://dx.doi.org/10.3390/electronics11172649.

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Hardware Trojans refer to additional logic maliciously implanted by attackers in integrated circuits (ICs). Because of the potential security threat of hardware Trojans, they have attracted extensive attention to security issues. As a formal verification method, property checking has been proved to be a powerful solution for hardware Trojan detection. However, existing property-checking methods are limited by the unity of security properties and the model explosion problem of formal models. The limitations above hinder the practical applications of these methods. To alleviate these challenges, we propose an effective property-checking method for hardware Trojan detection. Specifically, we establish the formal model based on the principle of finite state machine (FSM), and the method can alleviate the model explosion problem. For property writing, we extract the core behavior characteristics of hardware Trojans and then generate properties for the verification of certain types of hardware Trojans. Experimental results demonstrate that our approach is applicable to detect information leakage and denial of service (DoS) hardware Trojans by verifying security properties.
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6

McMillan, K. L. "A methodology for hardware verification using compositional model checking". Science of Computer Programming 37, n.º 1-3 (mayo de 2000): 279–309. http://dx.doi.org/10.1016/s0167-6423(99)00030-1.

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7

Bjesse, Per. "Word level bitwidth reduction for unbounded hardware model checking". Formal Methods in System Design 35, n.º 1 (7 de julio de 2009): 56–72. http://dx.doi.org/10.1007/s10703-009-0080-2.

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8

Zhang, Jie, Jian Qi y Yong Guan. "Research on Hardware Design Verification Methods". Advanced Materials Research 588-589 (noviembre de 2012): 1208–13. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.1208.

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This paper first summarizes the existing basic theories and methods of hardware design verification. Then it analyzes and compares the simulation-based verification and formal methods-based verification, and discusses Equivalence Checking, Model Checking and Theorem Proving in detail. Finally, it points out the existing problems and the future directions in the field.
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9

Cooke, John. "Symbolic Model Checking". Microprocessors and Microsystems 18, n.º 5 (junio de 1994): 297. http://dx.doi.org/10.1016/0141-9331(94)90007-8.

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10

Ben-David, Shoham, Cindy Eisner, Daniel Geist y Yaron Wolfsthal. "Model Checking at IBM". Formal Methods in System Design 22, n.º 2 (marzo de 2003): 101–8. http://dx.doi.org/10.1023/a:1022905120346.

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11

Emerson, E. Allen y A. Prasad Sistla. "Symmetry and model checking". Formal Methods in System Design 9, n.º 1-2 (agosto de 1996): 105–31. http://dx.doi.org/10.1007/bf00625970.

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12

Zakharov, V. "Review: Model Checking". Journal of Logic and Computation 11, n.º 6 (1 de diciembre de 2001): 962–64. http://dx.doi.org/10.1093/logcom/11.6.962.

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13

Lukács, Dániel, Gergely Pongrácz y Máté Tejfel. "Model Checking-Based Performance Prediction for P4". Electronics 11, n.º 14 (6 de julio de 2022): 2117. http://dx.doi.org/10.3390/electronics11142117.

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Next-generation networks focus on scale and scope at the price of increasing complexity, leading to difficulties in network design and planning. As a result, anticipating all hardware- and software-related factors of network performance requires time-consuming and expensive benchmarking. This work presents a framework and software tool for automatically inferring the performance of P4 programmable network switches based on the P4 source code and probabilistic models of the execution environment with the hope of eliminating the requirement of the costly set-up of networked hardware and conducting benchmarks. We designed the framework using a top-down approach. First, we transform high-level P4 programs into a representation that can be refined incrementally by adding probabilistic environment models of increasing levels of complexity in order to improve the estimation precision. Then, we use the PRISM probabilistic model checker to perform the heavy weight calculations involved in static performance prediction. We present a formalization of the performance estimation problem, detail our solution, and illustrate its usage and validation through a case study conducted using a small P4 program and the P4C-BM reference switch. We show that the framework is already capable of performing estimation, and it can be extended with more concrete information to yield better estimates.
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14

Cho, Shenghsun, Mrunal Patel, Michael Ferdman y Peter Milder. "Practical Model Checking on FPGAs". ACM Transactions on Reconfigurable Technology and Systems 14, n.º 2 (8 de julio de 2021): 1–18. http://dx.doi.org/10.1145/3448272.

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Software verification is an important stage of the software development process, particularly for mission-critical systems. As the traditional methodology of using unit tests falls short of verifying complex software, developers are increasingly relying on formal verification methods, such as explicit state model checking, to automatically verify that the software functions properly. However, due to the ever-increasing complexity of software designs, model checking cannot be performed in a reasonable amount of time when running on general-purpose cores, leading to the exploration of hardware-accelerated model checking. FPGAs have been demonstrated to be promising verification accelerators, exhibiting nearly three orders of magnitude speedup over software. Unfortunately, the “FPGA programmability wall,” particularly the long synthesis and place-and-route times, block the general adoption of FPGAs for model checking. To address this problem, we designed a runtime-programmable pipeline specifically for model checkers on FPGAs to minimize the “preparation time” before a model can be checked. Our design of the successor state generator and the state validator modules enables FPGA-acceleration of model checking without incurring the time-consuming FPGA implementation stages, reducing the preparation time before checking a model from hours to less than a minute, while incurring only a 26% execution time overhead compared to model-specific implementations.
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15

Ziller, Roberto y Klaus Schneider. "Combining supervisor synthesis and model checking". ACM Transactions on Embedded Computing Systems 4, n.º 2 (1 de mayo de 2005): 331–62. http://dx.doi.org/10.1145/1067915.1067920.

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16

Schlich, Bastian. "Model checking of software for microcontrollers". ACM Transactions on Embedded Computing Systems 9, n.º 4 (marzo de 2010): 1–27. http://dx.doi.org/10.1145/1721695.1721702.

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17

Kumar, Sanjeev y Kai Li. "Using model checking to debug device firmware". ACM SIGOPS Operating Systems Review 36, SI (31 de diciembre de 2002): 61–74. http://dx.doi.org/10.1145/844128.844135.

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18

Kesten, Yonit, Amir Pnueli, Li-On Raviv y Elad Shahar. "Model Checking with Strong Fairness". Formal Methods in System Design 28, n.º 1 (enero de 2006): 57–84. http://dx.doi.org/10.1007/s10703-006-4342-y.

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19

Sebastiani, Roberto, Eli Singerman, Stefano Tonetta y Moshe Y. Vardi. "GSTE is partitioned model checking". Formal Methods in System Design 31, n.º 2 (26 de mayo de 2007): 177–96. http://dx.doi.org/10.1007/s10703-007-0036-3.

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20

Benerecetti, M. "Model checking multiagent systems". Journal of Logic and Computation 8, n.º 3 (1 de junio de 1998): 401–23. http://dx.doi.org/10.1093/logcom/8.3.401.

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21

Baier, Christel, Boudewijn R. Haverkort, Holger Hermanns y Joost-Pieter Katoen. "Model checking meets performance evaluation". ACM SIGMETRICS Performance Evaluation Review 32, n.º 4 (marzo de 2005): 10–15. http://dx.doi.org/10.1145/1059816.1059819.

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22

Kwiatkowska, Marta, Gethin Norman y David Parker. "Probabilistic model checking in practice". ACM SIGMETRICS Performance Evaluation Review 32, n.º 4 (marzo de 2005): 16–21. http://dx.doi.org/10.1145/1059816.1059820.

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23

Kumar, Jayanand Asok, Seyed Nematollah Ahmadyan y Shobha Vasudevan. "Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, n.º 6 (junio de 2014): 945–58. http://dx.doi.org/10.1109/tcad.2014.2299957.

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24

Griggio, Alberto y Marco Roveri. "Comparing Different Variants of the ic3 Algorithm for Hardware Model Checking". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, n.º 6 (junio de 2016): 1026–39. http://dx.doi.org/10.1109/tcad.2015.2481869.

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25

Malik, Avinash y David Gregg. "Orchestrating stream graphs using model checking". ACM Transactions on Architecture and Code Optimization 10, n.º 3 (16 de septiembre de 2013): 1–25. http://dx.doi.org/10.1145/2512435.

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26

Henderson, Peter B. "Abstraction, model checking and software correctness". ACM SIGCSE Bulletin 40, n.º 2 (junio de 2008): 23–24. http://dx.doi.org/10.1145/1383602.1383624.

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27

Leuschel, Michael, Andreas Podelski, C. R. Ramakrishnan y Ulrich Ultes-Nitsche. "Call for Papers Verification and Computational Logic Special Issue of Theory and Practice of Logic Programming". Theory and Practice of Logic Programming 1, n.º 5 (septiembre de 2001): 631–32. http://dx.doi.org/10.1017/s1471068401001089.

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Submission deadline: January 10, 2002The past decade has seen dramatic growth in the application of model checking techniques to the validation and verification of correctness properties of hardware, and more recently software systems. One of the methods is to model a hardware or software system as a finite, labelled transition system which is then exhaustively explored to decide whether a given temporal specification holds. Recently, there has been increasing interest in applying logic programming techniques to model checking in particular and verification in general. For example, table-based logic programming can be used as an efficient means of performing explicit model checking. Other research has successfully exploited set-based logic program analysis, constraint logic programming, and logic program transformation techniques.The aim of this special issue is to attract high-quality research papers on the interplay between verification techniques (e.g. model checking, reduction and abstraction) and logic programming techniques (e.g. constraints, abstract interpretation, program transformation).
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28

Fantechi, Alessandro, Stefania Gnesi y Gioia Ristori. "Model checking for action-based logics". Formal Methods in System Design 4, n.º 2 (febrero de 1994): 187–203. http://dx.doi.org/10.1007/bf01384084.

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29

Naik, Kshirasagar y Behcet Sarikaya. "Test case verification by model checking". Formal Methods in System Design 2, n.º 3 (junio de 1993): 277–321. http://dx.doi.org/10.1007/bf01384135.

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30

Godefroid, Patrice. "Software Model Checking: The VeriSoft Approach". Formal Methods in System Design 26, n.º 2 (marzo de 2005): 77–101. http://dx.doi.org/10.1007/s10703-005-1489-x.

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31

Norman, Gethin, David Parker y Jeremy Sproston. "Model checking for probabilistic timed automata". Formal Methods in System Design 43, n.º 2 (12 de octubre de 2012): 164–90. http://dx.doi.org/10.1007/s10703-012-0177-x.

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32

Li, Yi, Jin Song Dong, Jing Sun, Yang Liu y Jun Sun. "Model checking approach to automated planning". Formal Methods in System Design 44, n.º 2 (26 de octubre de 2013): 176–202. http://dx.doi.org/10.1007/s10703-013-0197-1.

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33

Abdulla, Parosh Aziz, Mohamed Faouzi Atig, Othmane Rezine y Jari Stenman. "Budget-bounded model-checking pushdown systems". Formal Methods in System Design 45, n.º 2 (25 de abril de 2014): 273–301. http://dx.doi.org/10.1007/s10703-014-0207-y.

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34

Cabodi, Gianpiero, Carmelo Loiacono, Marco Palena, Paolo Pasini, Denis Patti, Stefano Quer, Danilo Vendraminetto, Armin Biere y Keijo Heljanko. "Hardware Model Checking Competition 2014: An Analysis and Comparison of Model Checkers and Benchmarks". Journal on Satisfiability, Boolean Modeling and Computation 9, n.º 1 (1 de enero de 2016): 135–72. http://dx.doi.org/10.3233/sat190106.

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35

Baier, Christel, Lucia Cloth, Boudewijn R. Haverkort, Holger Hermanns y Joost-Pieter Katoen. "Performability assessment by model checking of Markov reward models". Formal Methods in System Design 36, n.º 1 (febrero de 2010): 1–36. http://dx.doi.org/10.1007/s10703-009-0088-7.

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36

Lin, Shang-Wei y Pao-Ann Hsiung. "Model Checking Prioritized Timed Systems". IEEE Transactions on Computers 61, n.º 6 (junio de 2012): 843–56. http://dx.doi.org/10.1109/tc.2011.99.

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37

Trindade, Alessandro Bezerra, Renato De Faria Degelo, Edilson Galvao Dos Santos Junior, Hussama Ibrahim Ismail, Helder Cruz Da Silva y Lucas Carvalho Cordeiro. "Multi-core model checking and maximum satisfiability applied to hardware-software partitioning". International Journal of Embedded Systems 9, n.º 6 (2017): 570. http://dx.doi.org/10.1504/ijes.2017.088044.

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38

Cordeiro, Lucas Carvalho, Helder Cruz Da Silva, Hussama Ibrahim Ismail, Renato De Faria Degelo, Edilson Galvao Dos Santos Junior y Alessandro Bezerra Trindade. "Multi-core model checking and maximum satisfiability applied to hardware-software partitioning". International Journal of Embedded Systems 9, n.º 6 (2017): 570. http://dx.doi.org/10.1504/ijes.2017.10008947.

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39

XU, X., S. KIMURA, K. HORIKAWA y T. TSUCHIYA. "Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A, n.º 12 (1 de diciembre de 2006): 3451–57. http://dx.doi.org/10.1093/ietfec/e89-a.12.3451.

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40

Kobayashi, Naoki. "Model Checking Higher-Order Programs". Journal of the ACM 60, n.º 3 (junio de 2013): 1–62. http://dx.doi.org/10.1145/2487241.2487246.

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41

Ben-David, S., R. Trefler y G. Weddell. "Model Checking Using Description Logic". Journal of Logic and Computation 20, n.º 1 (13 de noviembre de 2008): 111–31. http://dx.doi.org/10.1093/logcom/exn062.

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42

BOZZANO, MARCO, GIORGIO DELZANNO y MAURIZIO MARTELLI. "Model checking linear logic specifications". Theory and Practice of Logic Programming 4, n.º 5-6 (12 de agosto de 2004): 573–619. http://dx.doi.org/10.1017/s1471068404002066.

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43

Jiang, Jiulei, Panqing Zhang y Zhanyou Ma. "The μ-Calculus Model-Checking Algorithm for Generalized Possibilistic Decision Process". Applied Sciences 10, n.º 7 (9 de abril de 2020): 2594. http://dx.doi.org/10.3390/app10072594.

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Model checking is a formal automatic verification technology for complex concurrent systems. It is used widely in the verification and analysis of computer software and hardware systems, communication protocols, security protocols, etc. The generalized possibilistic μ-calculus model-checking algorithm for decision processes is studied to solve the formal verification problem of concurrent systems with nondeterministic information and incomplete information on the basis of possibility theory. Firstly, the generalized possibilistic decision process is introduced as the system model. Then, the classical proposition μ-calculus is improved and extended, and the concept of generalized possibilistic μ-calculus (GPoμ) is given to describe the attribute characteristics of nondeterministic systems. Then, the GPoμ model-checking algorithm is proposed, and the model-checking problem is simplified to fuzzy matrix operations. Finally, a specific example and a case study are analyzed and verified. Compared with the classical μ-calculus, the generalized possibilistic μ-calculus has a stronger expressive power and can better characterize the attributes of nondeterministic systems. The model-checking algorithm can give the possibility that the system satisfies the attributes. The research work provides a new idea and method for model checking nondeterministic systems.
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44

Tao, Zhi-Hong, Hans Kleine Büning y Li-Fu Wang. "Direct Model Checking Matrix Algorithm". Journal of Computer Science and Technology 21, n.º 6 (noviembre de 2006): 944–49. http://dx.doi.org/10.1007/s11390-006-0944-5.

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45

Tao, Zhi-Hong, Cong-Hua Zhou, Zhong Chen y Li-Fu Wang. "Bounded Model Checking of CTL". Journal of Computer Science and Technology 22, n.º 1 (enero de 2007): 39–43. http://dx.doi.org/10.1007/s11390-007-9004-z.

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46

Rus, Teodor y Eric van Wyk. "Using Model Checking in a Parallelizing Compiler". Parallel Processing Letters 08, n.º 04 (diciembre de 1998): 459–71. http://dx.doi.org/10.1142/s0129626498000468.

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In this paper we describe the usage of temporal logic model checking in a parallelizing compiler to analyze the structure of a source program and locate opportunities for optimization and parallelization. The source program is represented as a process graph in which the nodes are sequential processes and the edges are control and data dependence relationships between the computations at the nodes. By labeling the nodes and edges with descriptive atomic propositions and by specifying the conditions necessary for optimizations and parallelizations as temporal logic formulas, we can use a model checker to locate nodes of the process graph where particular optimizations can be made. To discover opportunities for new optimizations or modify existing ones in this parallelizing compiler, we need only specify their conditions as temporal logic formulas; we do not need to add to or modify the code of the compiler. This greatly simplifies the process of locating optimization and parallelization opportunities in the source program and makes it easier to experiment with complex optimizations. Hence, this methodology provides a convenient, concise, and formal framework in which to carry out program optimizations by compilers.
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47

Strichman, Ofer. "Accelerating Bounded Model Checking of Safety Properties". Formal Methods in System Design 24, n.º 1 (enero de 2004): 5–24. http://dx.doi.org/10.1023/b:form.0000004785.67232.f8.

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48

Grumberg, Orna, Tamir Heyman y Assaf Schuster. "Distributed Symbolic Model Checking for μ-Calculus". Formal Methods in System Design 26, n.º 2 (marzo de 2005): 197–219. http://dx.doi.org/10.1007/s10703-005-1493-1.

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49

Barnat, Jiří y Ivana Černá. "Distributed breadth-first search LTL model checking". Formal Methods in System Design 29, n.º 2 (8 de julio de 2006): 117–34. http://dx.doi.org/10.1007/s10703-006-0009-y.

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50

Schuele, Tobias y Klaus Schneider. "Bounded model checking of infinite state systems". Formal Methods in System Design 30, n.º 1 (31 de agosto de 2006): 51–81. http://dx.doi.org/10.1007/s10703-006-0019-9.

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