Tesis sobre el tema "Hardware Model Checking"
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Ford, Gregory Fick. "Hardware Emulation of Sequential ATPG-Based Bounded Model Checking". Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.
Texto completoRaju, Akhilesh. "Trojan Detection in Hardware Designs". University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1504781162418081.
Texto completoVENDRAMINETTO, DANILO. "Advanced Techniques for Bit-Level Model Checking". Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643478.
Texto completoMarques, Luis Gustavo Perpetuo Costa. "Metodologia de desenvolvimento de VHDL sintetizável com uso de model checking". reponame:Repositório Institucional da UFSC, 2016. https://repositorio.ufsc.br/xmlui/handle/123456789/168246.
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Essa dissertação foi elaborada em uma companhia que desenvolve equipamentos para proteção e automação de subestações, sendo que a maior parte deles possui um FPGA programado em VHDL como unidade principal de processamento. O código VHDL sintetizável e validado através de simulação e testes em equipamento, método bastante comum mas que não e suficiente para garantir a satisfação de propriedades tanto gerais quanto orientadas a aplicação, devido ao fato de não ser exaustivo. Na direção de aumentar a confiabilidade do circuito projetado para o FPGA, o objetivo principal da dissertação e apresentar uma metodologia de desenvolvimento de codigo VHDL sintetizável que aprimore as atuais técnicas utilizadas, ao incorporar métodos formais para verificação de propriedades, sendo que o método formal utilizado e o model checking. A metodologia e construída de um modo que o uso do model checking seja transparente ao desenvolvedor VHDL, mantendo a interface com o processo de verificação formal em linguagem de usuário,evitando a necessidade de aprendizado de novas linguagens. Para atingir esse objetivo específico, e proposto que as propriedades sejam representadas através de padrões orientados a VHDL que são baseados na biblioteca OVL. Alem disso, os contraexemplos gerados no processo de model checking retornam como test bench VHDL, permitindo ao usuário identificar o comportamento indesejado através de simulação. O ambiente de verificação adotado utiliza modelos em linguagem intermediaria FIACRE como front-end e por isso são propostas regras de tradução VHDL-FIACRE para que a transformação possa ocorrer no contexto de engenharia dirigida a modelos e assim evitar erros no processo de tradução. O uso da linguagem intermediaria e vantajoso, pois permite a utilização das ferramentas de verificação, as quais são de código aberto,sem que seja necessária a tradução direta do VHDL para os formalismos matemáticos em que essas ferramentas se baseiam. A metodologia e validada com a aplicação em quatro exemplos de código VHDL, sendo dois deles utilizados em projetos desenvolvidos na empresa: uma função de proteção e um controlador de acesso a um barramento de transferência de dados. Os resultados da aplicação indicam que a proposta e viável,pois foi possível fazer a verificação dos exemplos, sendo que em um deles foi identificado um erro que havia passado despercebido por simulação, sinalizando que a proposta contribui no aumento da confiabilidade do código desenvolvido.
Abstract: This dissertation was elaborated in a company that develops equipment for substation protection and automation, most of them having an FPGA programmed in VHDL as the main processing unit. The synthesizable VHDL code is validated through simulation and tests on equipment, a fairly common method that is not enough to ensure the satisfaction of both general and application-oriented properties, due tothe fact of being non exhaustive. In the direction of increasing the reliability of the designed FPGA circuit, the main objective of thiswork is to present a synthesizable VHDL code development methodology that enhances the current techniques by incorporating formal methods for verication of properties, with model checking being theselected method. The methodology is constructed in such a way thatthe use of model checking procedure should be transparent to VHDL designers, keeping the interface with the formal verication process inuser language, avoiding the need to learn new languages. To achievethis specic objective, it is proposed that the properties are represented by VHDL oriented patterns based on OVL library. In addition, the counter examples generated in the model checking process for properties that failed, return as VHDL test bench, allowing the user to identify theundesired behavior through simulation. The verication environment used in the methodology requires models described with the intermediatelanguage FIACRE as front-end and so VHDL-FIACRE translation rules are proposed to allow the transformation to occur in the context of model driven engineering, and thus prevent errors in the translation process. The use of an intermediate language is advantageous because it allows the use of the verication tools, which are open source, withoutthe need of translating VHDL directly to the mathematical formalismin which these tools are based. The methodology is validated by the application in four examples of VHDL code, two of them are used in designs developed by the company: a protection function and a controller to access a data transfer bus. The application results indicate that the proposal is viable because it was possible to verify the examples,and for one of them was identied an error that had passed unnoticed by simulation, showing that the proposal contributes to increase the reliability of the created code.
Dharmadhikari, Pranav Hemant. "Hardware Trojan Detection in Sequential Logic Designs". University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1543919236213844.
Texto completoBingham, Brad. "Leveraging distributed explicit-state model checking for practical verification of liveness in hardware protocols". Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/52670.
Texto completoScience, Faculty of
Computer Science, Department of
Graduate
Ou, Jen-Chieh. "HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD". Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.
Texto completoAdams, Sara Elisabeth. "Abstraction discovery and refinement for model checking by symbolic trajectory evaluation". Thesis, University of Oxford, 2014. http://ora.ox.ac.uk/objects/uuid:27276f9c-eba5-42a9-985d-1812097773f8.
Texto completoJafri, Nisrine. "Formal fault injection vulnerability detection in binaries : a software process and hardware validation". Thesis, Rennes 1, 2019. http://www.theses.fr/2019REN1S014/document.
Texto completoFault injection is a well known method to test the robustness and security vulnerabilities of systems. Detecting fault injection vulnerabilities has been approached with a variety of different but limited methods. Software-based and hardware-based approaches have both been used to detect fault injection vulnerabilities. Software-based approaches can provide broad and rapid coverage, but may not correlate with genuine hardware vulnerabilities. Hardware-based approaches are indisputable in their results, but rely upon expensive expert knowledge, manual testing, and can not confirm what fault model represent the created effect. First, this thesis focuses on the software-based approach and proposes a general process that uses model checking to detect fault injection vulnerabilities in binaries. The efficacy and scalability of this process is demonstrated by detecting vulnerabilities in different cryptographic real-world implementations. Then, this thesis bridges software-based and hardware-based fault injection vulnerability detection by contrasting results of the two approaches. This demonstrates that: not all software-based vulnerabilities can be reproduced in hardware; prior conjectures on the fault model for electromagnetic pulse attacks may not be accurate; and that there is a relationship between software-based and hardware-based approaches. Further, combining both software-based and hardware-based approaches can yield a vastly more accurate and efficient approach to detect genuine fault injection vulnerabilities
PASINI, PAOLO. "Improving bit-level model checking algorithms for scalability through circuit-based reasoning". Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2680998.
Texto completoPALENA, MARCO. "Exploiting Boolean Satisfiability Solvers for High Performance Bit-Level Model Checking". Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2680997.
Texto completoYao, Håkansson Jonathan y Niklas Rosencrantz. "Formal Verification of Hardware Peripheral with Security Property". Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-209807.
Texto completoMålet med vårt projekt är att verifiera olika specifikationer av externa enheter som ansluts till datorn. Vi utför formell verifikation av sådan datorutrustning och virtuellt minne. Verifikation med temporal logik, LTL, utförs. Specifikt verifierar vi 4 olika use-case och 9 formler för seriell datakommunikation, DMA och virtuellt minne. Slutsatsen är att anslutning av extern hårdvara är säker om den är ordentligt konfigurerad.Vi gör jämförelser mellan olika minnesstorlekar och mätte tidsåtgången för att verifiera olika system. Vi ser att tidsåtgången för verifikation är långsammare än linjärt beroende och att relativt små system tar relativt lång tid att verifiera.
Pockrandt, Marcel [Verfasser], Sabine [Akademischer Betreuer] Glesner, Ben [Akademischer Betreuer] Juurlink y Rolf [Akademischer Betreuer] Drechsler. "Model checking memory-related properties of hardware/software codesigns / Marcel Pockrandt. Gutachter: Sabine Glesner ; Ben Juurlink ; Rolf Drechsler. Betreuer: Sabine Glesner". Berlin : Technische Universität Berlin, 2014. http://d-nb.info/1067388087/34.
Texto completoAhuja, Sumit. "High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design". Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/27802.
Texto completoPh. D.
Trindade, Alessandro Bezerra. "Aplicando verificação de modelos baseada nas teorias do módulo da satisfabilidade para o particionamento de hardware/software em sistemas embarcados". Universidade Federal do Amazonas, 2015. http://tede.ufam.edu.br/handle/tede/4091.
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When performing hardware/software co-design for embedded systems, does emerge the problem of allocating properly which functions of the system should be implemented in hardware (HW) or in software (SW). This problem is known as HW/SW partitioning and in the last ten years, a significant research effort has been carried out in this area. In this proposed project, we present two new approaches to solve the HW/SW partitioning problem by using SMT-based verification techniques, and comparing the results using the traditional technique of Integer Linear Programming (ILP) and a modern method of optimization by Genetic Algorithm (GA). The goal is to show with experimental results that model checking techniques can be effective, in particular cases, to find the optimal solution of the HW/SW partitioning problem using a state-of-the-art model checker based on Satisfiability Modulo Theories (SMT) solvers, when compared to the traditional techniques.
Quando se realiza um coprojeto de hardware/software para sistemas embarcados, emerge o problema de se decidir qual função do sistema deve ser implementada em hardware (HW) ou em software (SW). Este tipo de problema recebe o nome de particionamento de HW/SW. Na última década, um esforço significante de pesquisa tem sido empregado nesta área. Neste trabalho, são apresentadas duas novas abordagens para resolver o problema de particionamento de HW/SW usando técnicas de verificação formal baseadas nas teorias do módulo da satisfabilidade (SMT). São comparados os resultados obtidos com a tradicional técnica de programação linear inteira (ILP) e com o método moderno de otimização por algoritmo genético (GA). O objetivo é demonstrar, com os resultados empíricos, que as técnicas de verificação de modelos podem ser efetivas, em casos particulares, para encontrar a solução ótima do problema de particionamento de HW/SW usando um verificador de modelos baseado no solucionador SMT, quando comparado com técnicas tradicionais.
Harrath, Nesrine. "A stepwise compositional approach to model and analyze system C designs at the transactional level and the delta cycle level". Thesis, Paris, CNAM, 2014. http://www.theses.fr/2014CNAM0957/document.
Texto completoEmbedded systems are increasingly integrated into existing real-time applications. They are usually composed of deeply integrated but heterogeneous hardware and software components. These components are developed under strict constraints. Accordingly, the work of design engineers became more tricky and challenging. To meet the high quality standards in nowadays embedded systems and to satisfy the rising industrial demands, the automatization of the developing process of those systems is gaining more and more importance. A major challenge is to develop an automated approach that can be used for the integrated verification and validation of complex and heterogeneous HW/SW systems.In this thesis, we propose a new compositional approach to model and verify hardware and software written in SystemC language. This approach is based on the SystemC Waiting State Automata (WSA). The SystemC Waiting State Automata are used to model the abstract behavior of hardware or software systems described in SystemC. They preserve the semantics of the SystemC scheduler at the temporal and the delta-cycle level. This model allows to reduce the complexity of the modeling process of complex systems due to the problem of state explosion during modeling while remaining faithful to the original system. The SystemC waiting state automaton is also compositional and supports refinement. In addition, this model is extended with parameters such as time and counters in order to take into account further aspects like temporality and other extra-functional properties such as QoS.In this thesis, we propose a stepwise approach on how to automatically extract the SystemC WSAs from SystemC descriptions. This construction is based on symbolic execution together with predicate abstraction. We propose a set of algorithms to symbolically compose and reduce the SystemC WSAs in order to study, analyze and verify concurrent behavior of systems as well as the data exchange between various components. We then propose to use the SystemC WSA to model and simulate hardware and software systems, and to compute the worst cas execution time (WCET) using the Timed SystemC WSA. Finally, we define how to apply model checking techniques to prove the correctness of the abstract analysis
Plassan, Guillaume. "Conclusive formal verification of clock domain crossing properties". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT021/document.
Texto completoModern hardware designs typically comprise tens of clocks to optimize consumption and performance to the ongoing tasks. With the increasing number of clock-domain crossings as well as the huge complexity of modern SoCs, formally proving the functional integrity of data propagation became a major challenge. Several issues arise: setting up the design in a realistic mode, writing protocol assumptions modeling the environment, facing state-space explosion, analyzing counter-examples, ...The first contribution of this thesis aims at reaching a complete and realistic design setup. We use parametric liveness verification and a structural analysis of the design in order to identify behaviors of the clock and reset trees. The second contribution aims at avoiding state-space explosion, by combining localization abstractions of the design, and counter-example analysis. The key idea is to use counterexample-guided abstraction refinement as the algorithmic back-end, where the user influence the course of the algorithm based on relevant information extracted from intermediate abstract counterexamples. The third contribution aims at creating protocol assumptions for under-specified environments. First, multiple counter-examples are generated for an assertion, with different causes of failure. Then, information is mined from them and transformed into realistic protocol assumptions.Overall, this thesis shows that a conclusive formal verification can be obtained by combining inexpensive structural analysis along with exhaustive model checking
Stamenkovich, Joseph Allan. "Enhancing Trust in Autonomous Systems without Verifying Software". Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/89950.
Texto completoMaster of Science
Autonomous systems are surprisingly vulnerable, not just from malicious hackers, but from design errors and oversights. The lines of code required can quickly climb into the millions, and the artificial decision algorithms can be inscrutable and fully dependent upon the information they are trained on. These factors cause the verification of the core software running our autonomous cars, drones, and everything else to be prohibitively difficult by traditional means. Independent safety monitors are implemented to provide internal oversight for these autonomous systems. A semi-automatic design process efficiently creates error-free monitors from safety rules drones need to follow. These monitors remain separate and isolated from the software typically controlling the system, but use the same sensor information. They are embedded in the circuitry and act as their own small, task-specific processors watching to make sure a particular rule is not violated; otherwise, they take control of the system and force corrective behavior. The monitors are added to a consumer off-the-shelf (COTS) drone to demonstrate their effectiveness. For every rule monitored, an override is triggered when they are violated. Their effectiveness depends on reliable sensor information as with any electronic component, and the completeness of the rules detailing these monitors.
Wu, Cheng-Yin y 吳政穎. "Model Checking RT-Level Hardware Systems". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/76601859990180165600.
Texto completo國立臺灣大學
電子工程學研究所
102
Model checking, or property checking, is a classic methodology for formally verifying a hardware system. More specifically, given a system and a set of properties, model checkers judge whether the system satisfies a property or not. However, due to the high complexity of model checking, as the design complexity and the number of property to be verified grows rapidly, the capability of model checking decreases. In this thesis, we present a complete framework for model checking of RT-level hardware systems. The framework consists of three major building blocks: FORMAL MODELING, PREPROCESSING, and MODEL CHECKING. Starting from FORMAL MODELING, a complicated RT-level design is parsed, synthesized, and then modeled as a word-level network. Next in the PREPROCESSING stage, rewriting and resynthesis techniques are applied to optimize the network, and moreover, property-directed constraints and invariants are extracted from design abstraction for improving model checking. After properties are elaborated at the end of PREPROCESSING, a portfolio-based model checker starts to verify all the properties in the MODEL CHECKING stage, and in particular, different model checking algorithms share information (e.g. deep bounds and reachabilities) on-the-fly to complement each other. Our experimental evaluation shows that our framework, equipped with abovementioned techniques, is capable of model checking RT-level benchmarks with thousands of properties efficiently.
Bobaru, Mihaela. "Approximation and Refinement Techniques for Hard Model-checking Problems". Thesis, 2009. http://hdl.handle.net/1807/17453.
Texto completoMärcker, Steffen. "Model Checking Techniques for Design and Analysis of Future Hardware and Software Systems". 2020. https://tud.qucosa.de/id/qucosa%3A74374.
Texto completoHarrath, Nesrine. "Une approche compositionnelle pour la modélisation et l'analyse des composants systemC au niveau TLM et au niveau des Delta Cycles". Thesis, 2014. http://www.theses.fr/2015CNAM0957/document.
Texto completoEmbedded systems are increasingly integrated into existing real-time applications. They are usually composed of deeply integrated but heterogeneous hardware and software components. These components are developed under strict constraints. Accordingly, the work of design engineers became more tricky and challenging. To meet the high quality standards in nowadays embedded systems and to satisfy the rising industrial demands, the automatization of the developing process of those systems is gaining more and more importance. A major challenge is to develop an automated approach that can be used for the integrated verification and validation of complex and heterogeneous HW/SW systems.In this thesis, we propose a new compositional approach to model and verify hardware and software written in SystemC language. This approach is based on the SystemC Waiting State Automata (WSA). The SystemC Waiting State Automata are used to model the abstract behavior of hardware or software systems described in SystemC. They preserve the semantics of the SystemC scheduler at the temporal and the delta-cycle level. This model allows to reduce the complexity of the modeling process of complex systems due to the problem of state explosion during modeling while remaining faithful to the original system. The SystemC waiting state automaton is also compositional and supports refinement. In addition, this model is extended with parameters such as time and counters in order to take into account further aspects like temporality and other extra-functional properties such as QoS.In this thesis, we propose a stepwise approach on how to automatically extract the SystemC WSAs from SystemC descriptions. This construction is based on symbolic execution together with predicate abstraction. We propose a set of algorithms to symbolically compose and reduce the SystemC WSAs in order to study, analyze and verify concurrent behavior of systems as well as the data exchange between various components. We then propose to use the SystemC WSA to model and simulate hardware and software systems, and to compute the worst cas execution time (WCET) using the Timed SystemC WSA. Finally, we define how to apply model checking techniques to prove the correctness of the abstract analysis