Tesis sobre el tema "Hardware circuits"
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Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication". Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.
Texto completoVita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).
Kalganova, Tatiana. "Evolvable hardware design of combinational logic circuits". Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4341.
Texto completoSingh, Satnam. "Analysis of hardware descriptions". Thesis, University of Glasgow, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.390451.
Texto completoSandiford, Richard. "Hardware compilation based on communicating processes". Thesis, Imperial College London, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246769.
Texto completoThompson, Adrian. "Hardware evolution : automatic design of electronic circuits in reconfigurable hardware by artificial evolution". Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360588.
Texto completoDesai, Avinash R. "Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation". Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23756.
Texto completoMaster of Science
Basak, Abhishek. "INFRASTRUCTURE AND PRIMITIVES FOR HARDWARE SECURITY IN INTEGRATED CIRCUITS". Case Western Reserve University School of Graduate Studies / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=case1458787036.
Texto completoBlum, Thomas. "Modular exponentiation on reconfigurable hardware". Digital WPI, 1999. http://www.wpi.edu/Pubs/ETD/Available/etd-090399-090413/unrestricted/thesis.pdf.
Texto completoWang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE". Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.
Texto completoStaunstrup, Jørgen. "A formal approach to hardware design /". Boston [u.a.] : Kluwer Acad. Publ, 1994. http://www.loc.gov/catdir/enhancements/fy0820/93043582-d.html.
Texto completoHe, Ji. "Formal specification and analysis of digital hardware circuits in LOTOS". Thesis, University of Stirling, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.322097.
Texto completoLayzell, Paul. "Hardware evolution : on the nature of artificially evolved electronic circuits". Thesis, University of Sussex, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.393208.
Texto completoDutta, Sumit Ph D. Massachusetts Institute of Technology. "Magnetic logic circuits with high bit resolution for hardware acceleration". Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111997.
Texto completoThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 109-120).
The ever-increasing demand for high-performance and low-power computing warrants an investigation of technologies beyond conventional digital transistor circuits. We explore a logic device based on magnetic domain walls, which are electrically movable boundaries between oppositely magnetized domains of a wire, for applications to hardware acceleration. A domain wall logic device takes current on the input, which moves a magnetic domain wall to a position in a ferromagnetic wire, and this position is the nonvolatile data token read as an output current through a magnetic tunnel junction. The spatial resolution of discrete magnetic domain wall positions in domain wall logic devices is studied to guide memory and logic applications. Theory, numerical modeling, and experiments on in-plane and perpendicularly magnetized materials demonstrate that the bit resolution, or analog information capacity, of a magnetic nanowire with a single domain wall is limited by the self-affine statistics of the wire edge roughness. The domain wall logic device is extended further into functional design implementations, including a logic-in-memory architecture to perform deep convolutional neural network operations in a hybrid process with magnetic devices and 45 nm CMOS. A 3-terminal magnetic logic device is designed to have a 3-bit resolution, and is used in conjunction with transistors in circuit designs for an ecient logic-in-memory system that can process convolutional neural networks 10 faster than conventional digital CMOS implementations.
by Sumit Dutta.
Ph. D.
Gohil, Nikhil N. "Design of DPA-Resistant Integrated Circuits". University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.
Texto completoPietkiewicz-Koutny, Marta. "Relating formal models of concurrency for the modelling of asynchronous digital hardware". Thesis, University of Newcastle Upon Tyne, 2000. http://hdl.handle.net/10443/1817.
Texto completoHu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY". Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.
Texto completoPatel, Mayank Raman. "HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES". Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275246.
Texto completoStamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic". Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
Texto completoRyan, Christopher A. "Parallel hardware accelerated switch level fault simulation". Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-10022007-145318/.
Texto completoKuyucu, Tuze. "Evolution of circuits in hardware and the evolvability of artificial development". Thesis, University of York, 2010. http://etheses.whiterose.ac.uk/1020/.
Texto completoMeana, Richard William Piper. "Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware". Scholar Commons, 2013. http://scholarcommons.usf.edu/etd/4728.
Texto completoKim, Kwanghyun. "An expert system for self-testable hardware design". Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.
Texto completoPh. D.
Goulart, Sobrinho Edilton Furquim [UNESP]. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo". Universidade Estadual Paulista (UNESP), 2007. http://hdl.handle.net/11449/87253.
Texto completoCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).
In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).
Tobar, Edgar Leonardo Romero. "Contribuições à verificação funcional ajustada por cobertura para núcleos de hardware de comunicação e multimídia". Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-20082010-160736/.
Texto completoMaking functional verification more efficient in terms of computational and time resources is mandatory in order to maintain the evolution of digital systems. Coverage driven verification is one of the recently used alternatives for speeding up the execution of testbenches. Many approaches have been successfully applied to the functional verification of cores in the application domain of general purpose processors, however, being influenced by the specific coverage and testcase dimensionality characteristics of this domain. Furthermore, little attention has been given to the use of coverage driven verification in other domains, such as communication systems and multimedia systems. These domains have been considered in the present study, together with the specific factors that have influenced the coverage driven testbench results. Among these factors, one has identified the size of the testcase space and the distribution of the coverage events; making it necessary to the development of this work, several changes regarding the construction of the coverage driven testbenches. Coverage driven testecase generation is performed by feedbacking the coverage status information and selecting those testcases that lead to the improvement of the coverage progression rate. This feedback depends on the construction of a model, by automatic learning, which relates testcases and the observations of coverage events. During this work, realistic large IP cores were verified with the following coverage driven techniques: Bayesian networks and classification tree data mining. These techniques, previously used in specific research works, adopt local optimization in their processing. In the present work, coverage driven verification with support vector machine learning, is tested due to the fact that this technique is based in a global optimization process. Results of this work have shown the need of adaptation of the coverage driven verification to the application domain characteristics, in order to obtain meaningful acceleration in testbench execution.
Cozzi, Maxime. "Infrared Imaging for Integrated Circuit Trust and Hardware Security". Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS046.
Texto completoThe generalization of integrated circuits and more generally electronics to everyday life systems (military, finance, health, etc) rises the question about their security. Today, the integrity of such circuits relies on a large panel of known attacks for which countermeasures have been developed. Hence, the search of new vulnerabilities represents one of the largest contribution to hardware security. The always rising complexity of dies leads to larger silicon surfaces.Circuit imaging is therefore a popular step among the hardware security community in order to identify regions of interest within the die. In this objective, the work presented here proposes new methodologies for infrared circuit imaging. In particular, it is demonstrated that statistical measurement analysis can be performed for automated localization of active areas in an integrated circuit.Also, a new methodology allowing efficient statistical infrared image comparison is proposed. Finally, all results are acquired using a cost efficient infrared measurement platform that allows the investigation of weak electrical source, detecting power consumption as low as 200 µW
Taesopapong, Somboon. "A VLSI-nMOS hardware implementation of a high speed parallel adder". Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183379787.
Texto completoLáník, Jan. "La réduction de consommation dans les circuits digitaux". Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM016/document.
Texto completoThe topic of this thesis are methods for power reduction in digital circuits by reducing average switching on the transistor level. These methods are structural in the sense that they are not related to tuning physical properties of the circuitry but to the internal structure of the implemented logic an d therefore independent on the particular technology. We developed two novel methods. One is based on optimizing the structure of the combinatorial part of a circuit during synthesis. The second method is focused on sequential part of the circuit. It looks for clock gating conditions that can be used to disable idle parts of a circuit and uses formal methods to prove that the function of the circuit will not be altered
Chenard, Jean-Samuel. "Hardware-based temporal logic checkers for the debugging of digital integrated circuits". Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106282.
Texto completoLa complexité des circuits intégrés augmente sans cesse et à un tel point que le procéssus de déboggage pose de nombreux problèmes techniques et engendre des retards dans la production. Une approche d'ensemble de conception pour le déboggage (Design-for-Debug) devient donc rapidement une nécessité. Cette thèse propose une approche détaillée de niveau système, intégrant des circuits de surveillance sur puce. L'approche proposée s'appuie sur la réutilisation de déclarations écrites en language de logique temporelle afin de les transformer en circuits digitaux efficaces. Ces derniers seront intégrés à la puce à travers son interface d'image mémoire afin qu'ils puissent servir au processus de déboggage ainsi qu'à une utilisation dans le système lorsque la puce est intégrée dans son environement. Cette thèse présente une série d'ajout au procéssus de transformation d'instructions de logique temporelle de manière à faciliter le procéssus de déboggage. Une méthode qui automatise l'intégration des sorties et du contrôle des circuits de surveillance est présentée ainsi que la manière dont une utilisation de ces circuits peut être accomplie dans le contexte d'un système d'exploitation moderne (Linux). Finalement, une méthode globale d'intégration des circuits de vérification dans le contexte de systèmes basés sur les réseaux-sur-puce est présentée, accompagnée de la chaine d'outils requise pour supporter ce nouveau processus de conception. Cette méthode propose l'utilisation de facteurs de qualité de test, de surveillance et de déboggage (Test, Monitoring and Debug) permettant une meilleure sélection des circuits ainsi qu'une intégration plus efficace au niveau des resources matérielles.
Batts, William Merle. "Modeling of a hardware VLSI placement system : accelerating the simulated annealing algorithm /". Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/1015.
Texto completoKhairullah, Shawkat Sabah. "Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices". VCU Scholars Compass, 2018. https://scholarscompass.vcu.edu/etd/5671.
Texto completoBodnar, Michael Richard. "The implementation of a hardware accelerator for the full-wave analysis of electronic circuits". Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 63 p, 2007. http://proquest.umi.com/pqdweb?did=1338919461&sid=3&Fmt=2&clientId=8331&RQT=309&VName=PQD.
Texto completoKoelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits". Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.
Texto completoAhmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits". PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.
Texto completoChu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays". Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.
Texto completoAndrade, Junior Antonio de Quadros. "Planejamento de teste de sistemas baseados em núcleos de hardware de sinal misto usando bist". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/8296.
Texto completoCurrently, integrated electronic systems follow the core-based design paradigm. Such systems include not only digital circuits as internal blocks, but also analog circuits, which dominate test resources, such as testing time, extra pins and overhead area, thus increasing the total manufacture cost of these devices. The present work proposes the application of analog Built-in Self Test (BIST) techniques based on the reuse of available digital cores within the same integrated system, aiming to reduce the test costs of the analog cores. Moreover, a satisfactory strategy requires an adequate test planning, so that the design space is better explored. By adapting a software tool, which was originally designed for test planning of exclusively digital SOC, to consider analog cores, as well as the possibility of BIST, one can evaluate the impact of the proposed strategy in terms of test application time, area overhead due to test structures added and extra pins. Power dissipation restrictions may also be taken into account. In order to validate the hypotheses considered, mixed-signal systems are described from digital industrial and academic benchmarks, just adding analog cores. Through simulation with the adapted tool, the obtained results point to a decrease in the system test time, as well as a reduction in the cost of Automatic Test Equipment (ATE), in case of a production test. Thus, a reduction in the overall cost of the test procedure for such devices can be achieved.
Thulasi, Raman Sudheer Ram. "Logic Encryption of Sequential Circuits". University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.
Texto completoBa, Papa-Sidy. "Détection et prévention de Cheval de Troie Matériel (CTM) par des méthodes Orientées Test Logique". Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT271/document.
Texto completoIn order to reduce the production costs of integrated circuits (ICs), outsourcing the fabrication process has become a major trend in the Integrated Circuits (ICs) industry. As an inevitable unwanted side effect, this outsourcing business model increases threats to hardware products. This process raises the issue of un-trusted foundries in which, circuit descriptions can be manipulated with the aim to possibly insert malicious circuitry or alterations, referred to as Hardware Trojan Horses (HTHs). This motivates semiconductor industries and researchers to study and investigate solutions for detecting during testing and prevent during fabrication, HTH insertion.However, considering the stealthy nature of HTs, it is quite impossible to detect them with conventional testing or even with random patterns. This motivates us to make some contributions in this thesis by proposing solutions to detect and prevent HTH after fabrication (during testing).The proposed methods help to detect HTH as well during testing as during normal mode(run-time), and they are logic testing based.Furthermore, we propose prevention methods, which are also logic testing based, in order tomake harder or quasi impossible the insertion of HTH both in netlist and layout levels
Taber, Caleb N. "Conversion of Digital Circuits Labs". Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.
Texto completoZaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology". DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.
Texto completoMoseley, Ralph. "Transcending static deployment of circuits : dynamic run-time systems and mobile hardware processes for FPGAs". Thesis, University of Kent, 2002. https://kar.kent.ac.uk/13733/.
Texto completoSchaeffer, Ben. "Synthesis of Linear Reversible Circuits and EXOR-AND-based Circuits for Incompletely Specified Multi-Output Functions". PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3783.
Texto completoImvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit". Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.
Texto completoThesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.
Norrod, Forrest Eugene. "The E-algorithm: an automatic test generation algorithm for hardware description languages". Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43260.
Texto completoMaster of Science
Lynch, Elizabeth Whitaker. "Hardware acceleration for conservative parallel discrete event simulation on multi-core systems". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39506.
Texto completoVamja, Harsh. "Reverse Engineering of Finite State Machines from Sequential Circuits". University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191.
Texto completoBrown, Michelle M. "Hardware study on the H.264/AVC video stream parser /". Online version of thesis, 2008. http://hdl.handle.net/1850/7766.
Texto completoAhderom, Selam T. "Opto-VLSI based WDM multifunction device". Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/772.
Texto completoArdeishar, Raghu. "Automatic verification of VHDL models". Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.
Texto completoSelvakumaran, Dinesh Kumar. "ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES". UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/132.
Texto completoBalog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /". Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.
Texto completo