Artículos de revistas sobre el tema "GATE LEVEL SIMULATION"
Crea una cita precisa en los estilos APA, MLA, Chicago, Harvard y otros
Consulte los 50 mejores artículos de revistas para su investigación sobre el tema "GATE LEVEL SIMULATION".
Junto a cada fuente en la lista de referencias hay un botón "Agregar a la bibliografía". Pulsa este botón, y generaremos automáticamente la referencia bibliográfica para la obra elegida en el estilo de cita que necesites: APA, MLA, Harvard, Vancouver, Chicago, etc.
También puede descargar el texto completo de la publicación académica en formato pdf y leer en línea su resumen siempre que esté disponible en los metadatos.
Explore artículos de revistas sobre una amplia variedad de disciplinas y organice su bibliografía correctamente.
Chatterjee, Debapriya, Andrew Deorio y Valeria Bertacco. "Gate-Level Simulation with GPU Computing". ACM Transactions on Design Automation of Electronic Systems 16, n.º 3 (junio de 2011): 1–26. http://dx.doi.org/10.1145/1970353.1970363.
Texto completoViamontes, George F., Igor L. Markov y John P. Hayes. "Improving Gate-Level Simulation of Quantum Circuits". Quantum Information Processing 2, n.º 5 (octubre de 2003): 347–80. http://dx.doi.org/10.1023/b:qinp.0000022725.70000.4a.
Texto completoUbar, Raimund, Jaan Raik, Eero Ivask y Marina Brik. "Defect-oriented mixed-level fault simulation in digital systems". Facta universitatis - series: Electronics and Energetics 15, n.º 1 (2002): 123–36. http://dx.doi.org/10.2298/fuee0201123u.
Texto completoChih-Shun Ding, Chi-Ying Tsui y M. Pedram. "Gate-level power estimation using tagged probabilistic simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, n.º 11 (1998): 1099–107. http://dx.doi.org/10.1109/43.736184.
Texto completoSvensson, C. M. y R. Tjarnstrom. "Switch-level simulation and the pass transistor EXOR gate". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, n.º 9 (1988): 994–97. http://dx.doi.org/10.1109/43.7797.
Texto completoBagrodia, Rajive, Yu-an Chen, Vikas Jha y Nicki Sonpar. "Parallel gate-level circuit simulation on shared memory architectures". ACM SIGSIM Simulation Digest 25, n.º 1 (julio de 1995): 170–74. http://dx.doi.org/10.1145/214283.214336.
Texto completoVandris, Evstratios y Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits". VLSI Design 4, n.º 3 (1 de enero de 1996): 217–29. http://dx.doi.org/10.1155/1996/34084.
Texto completoCORNO, FULVIO, MATTEO SONZA REORDA y GIOVANNI SQUILLERO. "EVOLUTIONARY SIMULATION-BASED VALIDATION". International Journal on Artificial Intelligence Tools 13, n.º 04 (diciembre de 2004): 897–916. http://dx.doi.org/10.1142/s0218213004001880.
Texto completoHigami, Yoshinobu, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi y Yuzo Takamatsu. "An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation". IPSJ Transactions on System LSI Design Methodology 2 (2009): 250–62. http://dx.doi.org/10.2197/ipsjtsldm.2.250.
Texto completoBoliolo, A., L. Benini, G. de Micheli y B. Ricco. "Gate-level power and current simulation of CMOS integrated circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, n.º 4 (diciembre de 1997): 473–88. http://dx.doi.org/10.1109/92.645074.
Texto completoWood, Kenneth R. "Distributing gate-level digital timing simulation over arrays of transputers". Concurrency: Practice and Experience 3, n.º 4 (agosto de 1991): 367–79. http://dx.doi.org/10.1002/cpe.4330030413.
Texto completoCheng, Rui, Lin-Zi Yin, Zhao-Hui Jiang y Xue-Mei Xu. "Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm". Entropy 25, n.º 4 (31 de marzo de 2023): 597. http://dx.doi.org/10.3390/e25040597.
Texto completoHungse Cha, E. M. Rudnick, J. H. Patel, R. K. Iyer y G. S. Choi. "A gate-level simulation environment for alpha-particle-induced transient faults". IEEE Transactions on Computers 45, n.º 11 (1996): 1248–56. http://dx.doi.org/10.1109/12.544481.
Texto completoFahmi, M. I., M. F. Mukmin, H. F. Liew, C. L. Wai, M. A. Aazmi y S. N. M. Arshad. "Design new voltage balancing control series connected for HV-IGBT`s". International Journal of Electrical and Computer Engineering (IJECE) 11, n.º 4 (1 de agosto de 2021): 2899. http://dx.doi.org/10.11591/ijece.v11i4.pp2899-2906.
Texto completoAlamin, Mochammad Machlul, Hendrawan Armanto y Indra Maryati. "Penerapan Teknologi Augmented Reality Untuk Pembelajaran Gerbang Logika Pada Mata Pelajaran Sistem Komputer". JURNAL MEDIA INFORMATIKA BUDIDARMA 4, n.º 3 (20 de julio de 2020): 503. http://dx.doi.org/10.30865/mib.v4i3.2128.
Texto completoMeraji, Sina, Wei Zhang y Carl Tropper. "On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, n.º 9 (septiembre de 2010): 1368–80. http://dx.doi.org/10.1109/tcad.2010.2049044.
Texto completoBatagin Armelin, Fábio, Lírida Alves de Barros Naviner y Roberto d’Amore. "Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate". Electronics 8, n.º 7 (2 de julio de 2019): 749. http://dx.doi.org/10.3390/electronics8070749.
Texto completoZhao, Weiguo, Shuo Li, Honggang Fan y Liying Wang. "Fluctuation in the Water Level of the Air Hole of the Gate Shaft in the Pumped Storage Power Station". Processes 11, n.º 3 (16 de marzo de 2023): 905. http://dx.doi.org/10.3390/pr11030905.
Texto completoFehr, E. Scott, Stephen A. Szygenda y Granville E. Ott. "An Integrated Hardware Array for Very High Speed Logic Simulation". VLSI Design 4, n.º 2 (1 de enero de 1996): 107–18. http://dx.doi.org/10.1155/1996/13931.
Texto completoKim, Hong K. y Jack Jean. "Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation". VLSI Design 9, n.º 3 (1 de enero de 1999): 253–70. http://dx.doi.org/10.1155/1999/18373.
Texto completoPrasad, G. Durga y V. Jegathesan. "FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits". International Journal of Reconfigurable and Embedded Systems (IJRES) 6, n.º 1 (28 de mayo de 2018): 53. http://dx.doi.org/10.11591/ijres.v6.i1.pp53-68.
Texto completoZamri, Muhammad Harith Bin, Yoshihiro Ujihara, Masanori Nakamura, Mohammad R. K. Mofrad y Shukei Sugita. "Decoding the Effect of Hydrostatic Pressure on TRPV1 Lower-Gate Conformation by Molecular-Dynamics Simulation". International Journal of Molecular Sciences 23, n.º 13 (1 de julio de 2022): 7366. http://dx.doi.org/10.3390/ijms23137366.
Texto completoRAGUL, DURAISAMY y VENKATRAMAN THIYAGARAJAN. "A NOVEL FAULT TOLERANT ASYMMETRICAL 21-LEVEL INVERTER TOPOLOGY WITH REDUCED COMPONENTS". REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE 68, n.º 2 (3 de julio de 2023): 200–205. http://dx.doi.org/10.59277/rrst-ee.2023.68.2.14.
Texto completoSarhan, Sarhan Abdulsatar y Shaker Abdulatif Jalil. "Analysis of Simulation Outputs for the Mutual Effect of Flow in Weir and Gate System". Journal of University of Babylon for Engineering Sciences 26, n.º 6 (10 de abril de 2018): 48–59. http://dx.doi.org/10.29196/jubes.v26i6.1050.
Texto completoAamali, Kaoutar, Abdelhakim Alali, Mohamed Sadik y Zineb El Hariti. "A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)". E3S Web of Conferences 229 (2021): 01025. http://dx.doi.org/10.1051/e3sconf/202122901025.
Texto completoFang, Tianyu, Yu Gu, Xiangli He, Xiaodong Liu, Yu Han y Jian Chen. "Numerical Simulation of Gate Control for Unsteady Irrigation Flow to Improve Water Use Efficiency in Farming". Water 10, n.º 9 (5 de septiembre de 2018): 1196. http://dx.doi.org/10.3390/w10091196.
Texto completoMuroi, Hiromichi, Kensuke Mine y Yoshiki Eguchi. "Scenario Analysis of Sluice Gate Operations for Evaluating Inland Flood Damage". Journal of Disaster Research 16, n.º 3 (1 de abril de 2021): 429–36. http://dx.doi.org/10.20965/jdr.2021.p0429.
Texto completoZhang, Meng, Baikui Li y Jin Wei. "Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs". Crystals 10, n.º 5 (23 de mayo de 2020): 417. http://dx.doi.org/10.3390/cryst10050417.
Texto completoQiu, Chun y Cheng Lan Liu. "3D Dynamic Numerical Simulation of Water Flow in Stilling Basin with Flaring Gate Pier". Applied Mechanics and Materials 580-583 (julio de 2014): 1971–74. http://dx.doi.org/10.4028/www.scientific.net/amm.580-583.1971.
Texto completoBertrand-Krajewski, J. L., J. P. Bardin, C. Gibello y D. Laplace. "Hydraulics of a sewer flushing gate". Water Science and Technology 47, n.º 4 (1 de febrero de 2003): 129–36. http://dx.doi.org/10.2166/wst.2003.0237.
Texto completoLi, Ran, Jie Zhang y Jianbo Xiao. "Operation State Evaluation of Miter Gate Based on On-Line Monitoring and Finite Element Analysis". Applied Sciences 13, n.º 1 (28 de diciembre de 2022): 381. http://dx.doi.org/10.3390/app13010381.
Texto completoAshenden, Peter J., Henry Detmold y Wayne S. McKeen. "Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms". VLSI Design 2, n.º 1 (1 de enero de 1994): 1–16. http://dx.doi.org/10.1155/1994/86178.
Texto completoJmai, Bassem, Vitor Silva y Paulo M. Mendes. "2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation". Micromachines 12, n.º 8 (18 de agosto de 2021): 979. http://dx.doi.org/10.3390/mi12080979.
Texto completoVanijjirattikhan, Rangsarit, Chinoros Thongthamchart, Patsorn Rakcheep, Unpong Supakchukul y Jittiwut Suwatthikul. "Reservoir Flood Routing Simulation for Dam Safety Management in Thailand". Journal of Disaster Research 16, n.º 4 (1 de junio de 2021): 596–606. http://dx.doi.org/10.20965/jdr.2021.p0596.
Texto completoChen, Haotian, Hongjun Lv, Zhang Zhang, Xin Cheng y Guangjun Xie. "Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata". Journal of Circuits, Systems and Computers 28, n.º 08 (julio de 2019): 1950141. http://dx.doi.org/10.1142/s021812661950141x.
Texto completoChen, Jie Ren y Shi Feng Xu. "The Numerical Simulation of Hydrodynamics in the Sancha River Mouth". Advanced Materials Research 1065-1069 (diciembre de 2014): 2978–82. http://dx.doi.org/10.4028/www.scientific.net/amr.1065-1069.2978.
Texto completoChen, Shi Gui y Xi Zhang. "Optimized Simulation of Automatic Gate System of Beijing Tianjin Intercity Line on Beijing South Railway Station". Applied Mechanics and Materials 602-605 (agosto de 2014): 1391–94. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.1391.
Texto completoSu, Ching-Lung, Tse-Min Chen y Kuo-Hsuan Wu. "A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation". VLSI Design 2013 (16 de mayo de 2013): 1–10. http://dx.doi.org/10.1155/2013/529150.
Texto completoJohannesson, Daniel y Muhammad Nawaz. "Development of a PSpice Model for SiC MOSFET Power Modules". Materials Science Forum 858 (mayo de 2016): 1074–77. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1074.
Texto completoAl jewari, Maher Abd Ibrahim, Auzani Jidin, Siti Azura Ahmad Tarusan y Mohammed Rasheed. "Implementation of SVM for five-level cascaded H-Bridge multilevel inverters utilizing FPGA". International Journal of Power Electronics and Drive Systems (IJPEDS) 11, n.º 3 (1 de septiembre de 2020): 1132. http://dx.doi.org/10.11591/ijpeds.v11.i3.pp1132-1144.
Texto completoShah, M. J., K. S. Pandya y P. Chauhan. "Direct ADC Controlled Asymmetric Cascaded Multilevel Inverter". Engineering, Technology & Applied Science Research 12, n.º 4 (1 de agosto de 2022): 9071–77. http://dx.doi.org/10.48084/etasr.5164.
Texto completoIvancova, Olga, Vladimir Korenkov, Olga Tyatyushkina, Sergey Ulyanov y Toshio Fukuda. "Quantum supremacy in end-to-end intelligent IT. Pt. I:Quantum software engineering–quantum gate level applied models simulators". System Analysis in Science and Education, n.º 1 (2020) (2020): 52–84. http://dx.doi.org/10.37005/2071-9612-2020-1-52-84.
Texto completoGuo, Huaixin, Tangsheng Chen y Shang Shi. "Transient Simulation for the Thermal Design Optimization of Pulse Operated AlGaN/GaN HEMTs". Micromachines 11, n.º 1 (9 de enero de 2020): 76. http://dx.doi.org/10.3390/mi11010076.
Texto completoYang, Seiyang. "Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy". KIPS Transactions on Computer and Communication Systems 5, n.º 12 (31 de diciembre de 2016): 439–46. http://dx.doi.org/10.3745/ktccs.2016.5.12.439.
Texto completoJiang, Yu, Linyan Zeng y Yuxiao Luo. "Multiobjective Gate Assignment Based on Passenger Walking Distance and Fairness". Mathematical Problems in Engineering 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/361031.
Texto completoChampac, Victor H. y Joan Figueras. "Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects". VLSI Design 5, n.º 3 (1 de enero de 1997): 273–84. http://dx.doi.org/10.1155/1997/97381.
Texto completoRaj, Sumit, Rajib Kumar Mandal, Mala De y Ashutosh Kumar Singh. "Nine-level inverter with lesser number of power semiconductor switches using dSPACE". International Journal of Power Electronics and Drive Systems (IJPEDS) 13, n.º 1 (1 de marzo de 2022): 39. http://dx.doi.org/10.11591/ijpeds.v13.i1.pp39-46.
Texto completoDeng, Chengfa y Jincheng Du. "Numerical Simulation of Hydraulic Characteristics of Spillway Tunnel with Gradually Expanding Outlet and Lower outlet height". Journal of Physics: Conference Series 2271, n.º 1 (1 de mayo de 2022): 012031. http://dx.doi.org/10.1088/1742-6596/2271/1/012031.
Texto completoKim, Dong-Wook y Tae-Yong Choi. "Delay Time Estimation Model for Large Digital CMOS Circuits". VLSI Design 11, n.º 2 (1 de enero de 2000): 161–73. http://dx.doi.org/10.1155/2000/18189.
Texto completoSihombing, Fiktor y Nova Juwita Siburian. "Perancangan Gerbang Otomatis Menggunakan Frekuensi Berbasis Arduino". Jurnal ELPOTECS 4, n.º 2 (30 de septiembre de 2021): 10–21. http://dx.doi.org/10.51622/elpotecs.v4i2.430.
Texto completo