Artículos de revistas sobre el tema "Gate array circuits"
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Abraitis, Vidas y Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA". Solid State Phenomena 144 (septiembre de 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.
Texto completoMowafy, Aya Nabeel. "Asynchronous Circuits Design Using a Field Programmable Gate Array". International Journal for Research in Applied Science and Engineering Technology 6, n.º 4 (30 de abril de 2018): 2423–32. http://dx.doi.org/10.22214/ijraset.2018.4412.
Texto completoMohammadi, Hossein y Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate". Journal of Circuits, Systems and Computers 27, n.º 14 (23 de agosto de 2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.
Texto completoSato, Ryoichi, Yuta Kodera, Md Arshad Ali, Takuya Kusaka, Yasuyuki Nogami y Robert H. Morelos-Zaragoza. "Consideration for Affects of an XOR in a Random Number Generator Using Ring Oscillators". Entropy 23, n.º 9 (5 de septiembre de 2021): 1168. http://dx.doi.org/10.3390/e23091168.
Texto completoKuboki, S., I. Masuda, T. Hayashi y S. Torii. "A 4K CMOS gate array with automatically generated test circuits". IEEE Journal of Solid-State Circuits 20, n.º 5 (octubre de 1985): 1018–24. http://dx.doi.org/10.1109/jssc.1985.1052430.
Texto completoAKELLA, KAPILAN MAHESWARAN VENKATESH. "PGA-STC: programmable gate array for implementing self-timed circuits". International Journal of Electronics 84, n.º 3 (marzo de 1998): 255–67. http://dx.doi.org/10.1080/002072198134823.
Texto completoMurtaza, Ali Faisal y Hadeed Ahmed Sher. "A Reconfiguration Circuit to Boost the Output Power of a Partially Shaded PV String". Energies 16, n.º 2 (4 de enero de 2023): 622. http://dx.doi.org/10.3390/en16020622.
Texto completoJaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim y Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance". Applied Sciences 11, n.º 14 (12 de julio de 2021): 6417. http://dx.doi.org/10.3390/app11146417.
Texto completoCherepacha, Don y David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths". VLSI Design 4, n.º 4 (1 de enero de 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.
Texto completoReaungepattanawiwat, Chalermpol y Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter". Applied Mechanics and Materials 781 (agosto de 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.
Texto completoHarrison, R. R., J. A. Bragg, P. Hasler, B. A. Minch y S. P. Deweerth. "A CMOS programmable analog memory-cell array using floating-gate circuits". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, n.º 1 (2001): 4–11. http://dx.doi.org/10.1109/82.913181.
Texto completoTANAKA, YU. "EXACT NON-IDENTITY CHECK IS NQP-COMPLETE". International Journal of Quantum Information 08, n.º 05 (agosto de 2010): 807–19. http://dx.doi.org/10.1142/s0219749910006599.
Texto completoChin, Scott Y. L., Clarence S. P. Lee y Steven J. E. Wilton. "On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays". International Journal of Reconfigurable Computing 2008 (2008): 1–13. http://dx.doi.org/10.1155/2008/751863.
Texto completoLin, Y., Fei Li y Lei He. "Circuits and architectures for field programmable gate array with configurable supply voltage". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, n.º 9 (septiembre de 2005): 1035–47. http://dx.doi.org/10.1109/tvlsi.2005.857180.
Texto completoLiu, Lijun, Jie Han, Lin Xu, Jianshuo Zhou, Chenyi Zhao, Sujuan Ding, Huiwen Shi et al. "Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics". Science 368, n.º 6493 (21 de mayo de 2020): 850–56. http://dx.doi.org/10.1126/science.aba5980.
Texto completoSotohebo, Takashi, Minoru Watanabe y Funtinori Kobayashi. "An FPGA Implementation of Finite Physical Quantity Neural Network". Journal of Robotics and Mechatronics 15, n.º 2 (20 de abril de 2003): 136–42. http://dx.doi.org/10.20965/jrm.2003.p0136.
Texto completoTrost, Andrej, Andrej Zemva y Matjaz Verderber. "Prototyping Hardware and Software Environment for Teaching Digital Circuit Design". International Journal of Electrical Engineering & Education 38, n.º 4 (octubre de 2001): 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.
Texto completoCabrita, Daniel Mealha y Carlos Raimundo Erig Lima. "A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms". Journal of Circuits, Systems and Computers 25, n.º 02 (23 de diciembre de 2015): 1650009. http://dx.doi.org/10.1142/s0218126616500092.
Texto completoZheng, Fang Yan, Zi Ran Chen y Zhi Cheng Yu. "Signal Processing Circuit Design Based on SOPC Technology for the Electric Field Type Time Grating Sensors". Applied Mechanics and Materials 635-637 (septiembre de 2014): 755–59. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.755.
Texto completoTakahashi, T., M. Uchida, T. Takahashi, R. Yoshino, M. Yamamoto y N. Kitamura. "A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits". IEEE Journal of Solid-State Circuits 30, n.º 12 (1995): 1544–46. http://dx.doi.org/10.1109/4.482204.
Texto completoFehr, E. Scott, Stephen A. Szygenda y Granville E. Ott. "An Integrated Hardware Array for Very High Speed Logic Simulation". VLSI Design 4, n.º 2 (1 de enero de 1996): 107–18. http://dx.doi.org/10.1155/1996/13931.
Texto completoRayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar y Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes". Computer Science and Information Technologies 3, n.º 1 (1 de marzo de 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.
Texto completoTung, Dam Minh, Nguyen Van Toan y Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA". Electronics 9, n.º 4 (10 de abril de 2020): 633. http://dx.doi.org/10.3390/electronics9040633.
Texto completoPfänder, O. A., R. Nopper, H. J. Pfleiderer, S. Zhou y A. Bermak. "Comparison of reconfigurable structures for flexible word-length multiplication". Advances in Radio Science 6 (26 de mayo de 2008): 113–18. http://dx.doi.org/10.5194/ars-6-113-2008.
Texto completoOkuno, Hirotsugu y Tetsuya Yagi. "Bio-Inspired Real-Time Robot Vision for Collision Avoidance". Journal of Robotics and Mechatronics 20, n.º 1 (20 de febrero de 2008): 68–74. http://dx.doi.org/10.20965/jrm.2008.p0068.
Texto completoHidalgo-López, José A., Óscar Oballe-Peinado, Julián Castellanos-Ramos y José A. Sánchez-Durán. "Two-Capacitor Direct Interface Circuit for Resistive Sensor Measurements". Sensors 21, n.º 4 (22 de febrero de 2021): 1524. http://dx.doi.org/10.3390/s21041524.
Texto completoYoshikawa, Masaya, Yusuke Mori y Takeshi Kumaki. "Implementation Aware Hardware Trojan Trigger". Advanced Materials Research 933 (mayo de 2014): 482–86. http://dx.doi.org/10.4028/www.scientific.net/amr.933.482.
Texto completoLiu, Yixuan, Qiao Hu, Qiqiao Wu, Xuanzhi Liu, Yulin Zhao, Donglin Zhang, Zhongze Han et al. "Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy". Micromachines 13, n.º 6 (10 de junio de 2022): 924. http://dx.doi.org/10.3390/mi13060924.
Texto completoSun, Jun-Wei, Xing-Tong Zhao y Yan-Feng Wang. "Multi-Input Look-Up-Table Design Based on Nanometer Memristor". Journal of Nanoelectronics and Optoelectronics 15, n.º 1 (1 de enero de 2020): 113–21. http://dx.doi.org/10.1166/jno.2020.2721.
Texto completoCheng, Shi, JinBao Zhang, Zhan Gao y Jiehua Wang. "Circuit Implementation of Respiratory Information Extracted from Electrocardiograms". Journal of Database Management 33, n.º 2 (1 de abril de 2022): 1–12. http://dx.doi.org/10.4018/jdm.314211.
Texto completoPoghossian, Arshak, Rene Welden, Vahe V. Buniatyan y Michael J. Schöning. "An Array of On-Chip Integrated, Individually Addressable Capacitive Field-Effect Sensors with Control Gate: Design and Modelling". Sensors 21, n.º 18 (14 de septiembre de 2021): 6161. http://dx.doi.org/10.3390/s21186161.
Texto completoMayacela, Margarita, Leonardo Rentería, Luis Contreras y Santiago Medina. "Comparative Analysis of Reconfigurable Platforms for Memristor Emulation". Materials 15, n.º 13 (25 de junio de 2022): 4487. http://dx.doi.org/10.3390/ma15134487.
Texto completoYe, A. y J. Rose. "Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, n.º 5 (mayo de 2006): 462–73. http://dx.doi.org/10.1109/tvlsi.2006.876095.
Texto completoŻbik, Mateusz y Piotr Wieczorek. "Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver". Applied Sciences 9, n.º 7 (27 de marzo de 2019): 1289. http://dx.doi.org/10.3390/app9071289.
Texto completoRamezani, Hadise, Majid Mohammadi y Amir Sabbagh Molahosseini. "An efficient look up table based approximate adder for field programmable gate array". Indonesian Journal of Electrical Engineering and Computer Science 25, n.º 1 (1 de enero de 2022): 144. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp144-151.
Texto completoXu, Baohe, Li Lu y Dawei Gong. "Research on Real-time Simulation of Power Electronic Circuits Based on Simscape". Journal of Physics: Conference Series 2196, n.º 1 (1 de febrero de 2022): 012025. http://dx.doi.org/10.1088/1742-6596/2196/1/012025.
Texto completoKondo, Jun, Murali Lingalugari, Pik-Yiu Chan, Evan Heller y Faquir Jain. "Modeling and Fabrication of Quantum Dot Channel Field Effect Transistors Incorporating Quantum Dot Gate". MRS Proceedings 1551 (2013): 149–54. http://dx.doi.org/10.1557/opl.2013.899.
Texto completoAbbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer". International Journal of Electrical and Computer Engineering (IJECE) 10, n.º 4 (1 de agosto de 2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.
Texto completoPoudel, Bikash, Arslan Munir, Joonho Kong y Muazzam A. Khan. "Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem". Journal of Low Power Electronics and Applications 11, n.º 4 (12 de noviembre de 2021): 43. http://dx.doi.org/10.3390/jlpea11040043.
Texto completosriraman, Harini y Pattabiraman Venkatasubbu. "SeRA: Self-Repairing Architecture for Dark Silicon Era". Journal of Circuits, Systems and Computers 29, n.º 04 (13 de junio de 2019): 2050053. http://dx.doi.org/10.1142/s021812662050053x.
Texto completoWard, Tyler, Neil Grabham, Chris Freeman, Yang Wei, Ann-Marie Hughes, Conor Power, John Tudor y Kai Yang. "Multichannel Biphasic Muscle Stimulation System for Post Stroke Rehabilitation". Electronics 9, n.º 7 (17 de julio de 2020): 1156. http://dx.doi.org/10.3390/electronics9071156.
Texto completoM, Saravanan, Nandakumar R y Veerabalaji G. "Effectual SVPWM Techniques and Implementation of FPGA Based Induction Motor Drive". International Journal of Reconfigurable and Embedded Systems (IJRES) 1, n.º 1 (1 de marzo de 2012): 11. http://dx.doi.org/10.11591/ijres.v1.i1.pp11-18.
Texto completoLee, Bong Wan, Min Seong Seo, Ho Guen Oh y Chan Yik Park. "High-Speed Wavelength Interrogator of Fiber Bragg Gratings for Capturing Impulsive Strain Waveforms". Advanced Materials Research 123-125 (agosto de 2010): 867–70. http://dx.doi.org/10.4028/www.scientific.net/amr.123-125.867.
Texto completoZhang, Kai, Jihao Gao, YunFei Wang y MingLiang Liang. "Hardware Realization of Kinematic Mechanism and Control System of Multifunctional Industrial Robot". Security and Communication Networks 2022 (10 de septiembre de 2022): 1–5. http://dx.doi.org/10.1155/2022/1940708.
Texto completoFang, R. C. Y., K. Y. Su y J. J. Hsu. "A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits". IEEE Journal of Solid-State Circuits 20, n.º 2 (abril de 1985): 481–88. http://dx.doi.org/10.1109/jssc.1985.1052333.
Texto completoVu, T. T., R. D. Nelson, G. M. Lee, P. C. T. Roberts, K. W. Lee, S. K. Swanson, A. Peczalski et al. "Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs". IEEE Journal of Solid-State Circuits 23, n.º 1 (febrero de 1988): 224–38. http://dx.doi.org/10.1109/4.283.
Texto completoLi, Xin, Qiufan Cheng, Shiliang Guo y Zhiquan Li. "Research of Gate-Tunable Phase Modulation Metasurfaces Based on Epsilon-Near-Zero Property of Indium-Tin-Oxide". Photonics 9, n.º 5 (9 de mayo de 2022): 323. http://dx.doi.org/10.3390/photonics9050323.
Texto completoOukaira, Aziz, Ahmad Hassan, Mohamed Ali, Yvon Savaria y Ahmed Lakhssassi. "Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC)". Sensors 22, n.º 15 (7 de agosto de 2022): 5904. http://dx.doi.org/10.3390/s22155904.
Texto completoZhang, Bingda, Xianglong Jin, Sijia Tu, Zhao Jin y Jie Zhang. "A New FPGA-Based Real-Time Digital Solver for Power System Simulation". Energies 12, n.º 24 (8 de diciembre de 2019): 4666. http://dx.doi.org/10.3390/en12244666.
Texto completoOhkawa, Takeshi, Daichi Uetake, Takashi Yokota y Kanemitsu Ootsu. "Component-Based FPGA Circuit Design and Verification for Robotic Systems Using JavaRock and ORB Engine - A Case Study". Applied Mechanics and Materials 433-435 (octubre de 2013): 1849–52. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1849.
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