Tesis sobre el tema "GaN Power Devices"

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 163-170).
Power electronics based on Gallium Nitride (GaN) is expected to significantly reduce the losses in power conversion circuits and increase the power density. This makes GaN devices very exciting candidates for next-generation power electronics, for the applications in electric vehicles, data centers, high-power and high-frequency communications. Currently, both lateral and vertical structures are considered for GaN power devices. In particular, vertical GaN power devices have attracted significant attention recently, due to the potential for achieving high breakdown voltage and current levels without enlarging the chip size. In addition, these vertical devices show superior thermal performance than their lateral counterparts. This PhD thesis addresses several key obstacles in developing vertical GaN power devices. The commercialization of vertical GaN power devices has been hindered by the high cost of bulk GaN. The first project in this PhD thesis demonstrated the feasibility of making vertical devices on a low-cost silicon (Si) substrate for the first time. The demonstrated high performance shows the great potential of low-cost vertical GaN-on-Si devices for 600-V level high-current and high-power applications. This thesis has also studied the origin of the off-state leakage current in vertical GaN pn diodes on Si, sapphire and GaN substrates, by experiments, analytical calculations and TCAD simulations. Variable-range-hopping through threading dislocations was identified as the main off-state leakage mechanism in these devices. The design space of leakage current of vertical GaN devices has been subsequently derived. Thirdly, a novel GaN vertical Schottky rectifier with trench MIS structures and trench field rings was demonstrated. The new structure greatly enhanced the reverse blocking characteristics while maintaining a Schottky-like good forward conduction. This new device shows great potential for using advanced vertical Schottky rectifiers for high-power and high-frequency applications. Finally, we investigated a fundamental and significant challenge for GaN power devices: the lack of reliable and generally useable patterned pn junctions. Two approaches have been proposed to make lateral patterned pn junctions. Two devices, junction barrier Schottky devices and super-junction devices, have been designed and optimized. Preliminary experimental results were also demonstrated for the feasibility of making patterned pn junctions and fabricating novel power devices.
by Yuhao Zhang.
Ph. D.

Recent emergence of data-driven and computation hungry algorithms has fuelled the demand for energy and processing power at an unprecedented rate. Semiconductor industry is, therefore, under constant pressure towards developing energy efficient devices. A Shift towards materials with higher figure-of-merit compared to Si, such as GaN for power conversion is one of the options currently being pursued. A minimisation in parasitic and static power losses in GaN can be brought about by realising on-chip CMOS based gate drivers for GaN power devices. At present, p-channel MOSHFETs in GaN show poor performance due to the low mobility and the severe trade-off between |ION| and |Vth|. For the first time, it is shown that despite a poor hole mobility, it is possible to improve the on-current as well as minimise |ION| - |Vth| trade-off, by adopting a combination of techniques: using an AlGaN cap, biased two-dimensional electron gas, and shrinking source-gate and gate-drain access region and channel lengths. As part of this work, a novel vertical p-channel heterojunction tunnel FET (TFET) utilising polarisation induced tunnel junction (PITJ) is also explored, which unlike common TFETs, shows non-ambipolar transfer characteristics and a better electrostatic control over the tunneling region via the gate. Meeting the ever-increasing demand for computation would require continuous scaling of transistor physical dimensions and supply voltage. While a further reduction in physical dimension is expected to come from adopting a vertical integration scheme, scaling in supply voltage would require achieving sub-60 mV/dec of subthreshold swing. The two common approaches to achieve this are TFETs and negative capacitance (NC) FETs, where the NC operation is commonly associated with ferroelectric materials. This work develops a model to explain sub-60 mV/dec, observed in Ta2O5/ZnO thin-film-transistors, which is governed by the motion of oxygen ions inside Ta2O5, leading to NC under dynamic gate bias sweep.

Les matériaux semi-conducteurs à grand gap tels que le carbure de silicium (SiC) et le nitrure de gallium (GaN) sont utilisés pour fabriquer des composants semi-conducteurs de puissance, qui vont jouer un rôle très important dans le développement des futurs systèmes de conversion d'énergie. L'objectif est de réaliser des convertisseurs avec de meilleurs rendements énergétiques et fonctionnant à haute température. Pour atteindre cet objectif, il est donc nécessaire de bien connaître les caractéristiques de ces nouveaux composants afin de développer des modèles qui seront utilisés lors de la conception des convertisseurs. Cette thèse est donc dédiée à la caractérisation et la modélisation des composants à grand gap, mais également l'étude des dispositifs de mesure des courants des commutations des composants rapides. Afin de déterminer les caractéristiques statiques des composants semi-conducteurs, une méthode de mesure en mode pulsé est présentée. Dans le cadre de cette étude, une diode SiC et un JFET SiC "normally-off" sont caractérisés à l'aide de cette méthode. Afin de mesurer les capacités inter-électrodes de ces composants, une nouvelle méthode basée sur l'utilisation des pinces de courant est proposée. Des modèles comportementaux d'une diode Si et d'un JFET SiC sont proposés en utilisant les résultats de caractérisation. Le modèle de la diode obtenu est validé par des mesures des courants au blocage (recouvrement inverse) dans différentes conditions de commutation. Pour valider le modèle du JFET SiC, une méthode de mesure utilisant une pince de courant de surface est proposée
Compared to traditional silicon (Si) semiconductor material, wide bandgap (WBG) materials like silicon carbide (SiC) and gallium nitride are gradually applied to fabricate power semiconductor devices, which are used in power converters to achieve high power efficiency, high operation temperature and high switching frequency. As those power devices are relatively new, their characterization and modeling are important to better understand their characteristics for better use. This dissertation is mainly focused on those WBG power semiconductor devices characterization, modeling and fast switching currents measurement. In order to measure their static characteristics, a single-pulse method is presented. A SiC diode and a "normally-off" SiC JFET is characterized by this method from ambient temperature to their maximal junction temperature with the maximal power dissipation around kilowatt. Afterwards, in order to determine power device inter-electrode capacitances, a measurement method based on the use of multiple current probes is proposed and validated by measuring inter-electrode capacitances of power devices of different technologies. Behavioral models of a Si diode and the SiC JFET are built by using the results of the above characterization methods, by which the evolution of the inter-electrode capacitances for different operating conditions are included in the models. Power diode models are validated with the measurements, in which the current is measured by a proposed current surface probe

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.
ENGLISH ABSTRACT: The main focus of this thesis is to document the formulation, extraction and validation of nonlinear models for the on-wafer gallium nitride (GaN) high-electron mobility (HEMT) devices manufactured at the Interuniversity Microelectronics Centre (IMEC) in Leuven, Belgium. GaN semiconductor technology is fast emerging and it is expected that these devices will play an important role in RF and microwave power amplifier applications. One of the main advantages of the new GaN semiconductor technology is that it combines a very wide band-gap with high electron mobility, which amounts to higher levels of gain at very high frequencies. HEMT devices based on GaN, is a fairly new technology and not many nonlinear models have been proposed in literature. This thesis details the design of hardware and software used in the development of the nonlinear models. An intermodulation distortion (IMD) measurement setup was developed to measure the second and higher-order derivative of the nonlinear drain current. The derivatives are extracted directly from measurements and are required to improve the nonlinear model IMD predictions. Nonlinear model extraction software was developed to automate the modelling process, which was fundamental in the nonlinear model investigation. The models are implemented in Agilent’s Advanced Design System (ADS) and it is shown that the models are capable of accurately predicting the measured S-parameters, large-signal singletone and two-tone behaviour of the GaN devices.
AFRIKAANSE OPSOMMING: Die hoofdoel van hierdie tesis is om die formulering, ontrekking en validasie van nie-lineêre modelle vir onverpakte gallium nitraat (GaN) hoë-elektronmobilisering transistors (HEMTs) te dokumenteer. Die transistors is vervaaardig by die Interuniversity Microelectronics Centre (IMEC) in Leuven, België. GaN-halfgeleier tegnologie is besig om vinnig veld te wen en daar word voorspel dat hierdie transistors ʼn belangrike rol gaan speel in RF en mikrogolf kragversterker toepassings. Een van die hoof voordele van die nuwe GaN-halfgeleier tegnologie is dat dit 'n baie wyd band-gaping het met hoë-elektronmobilisering, wat lei tot hoë aanwins by mikrogolf frekwensies. GaN HEMTs is 'n redelik nuwe tegnologie en nie baie nie-lineêre modelle is al voorgestel in literatuur nie. Hierdie tesis ondersoek die ontwerp van die hardeware en sagteware soos gebruik in die ontwikkeling van nie-lineêre modelle. 'n Intermodulasie distorsie-opstelling (IMD-opstelling) is ontwikkel vir die meting van die tweede en hoër orde afgeleides van die nie-lineêre stroom. Die afgeleides is direk uit die metings onttrek en moet die nie-lineêre IMD-voorspellings te verbeter. Nie-lineêre onttrekking sagteware is ontwikkel om die modellerings proses te outomatiseer. Die modelle word geïmplementeer in Agilent se Advanced Design System (ADS) en bewys dat die modelle in staat is om akkurate afgemete S-parameters, grootsein enkeltoon en tweetoon gedrag van die GaN-transistors te kan voorspel.

GaN-based devices have emerged as a promising solution for power management applications. The intrinsic physical properties of the Gallium Nitride are exploited in order to considerably improve the efficiency and to reduce the volume of the next generation power switching converters. The wide energy gap allows to fabricate high voltage-rate devices with a reduced area consumption, whereas the high mobility guarantees a considerably low on-Resistance of the transistor. Moreover, thanks to the reduced parasitic capacitances, the operating frequency of the devices can be higher than conventional Silicon based transistors. In order to ensure a wide spreading of Gallium Nitride technology in the power transistors market, the price of the devices needs to be kept as low as possible. The costs of native substrates for the fabrication of GaN transistors are nowadays prohibitive, so that the epitaxial growth of Gallium Nitride on Silicon substrates has been developed. GaN-on-Silicon is the most suitable technology to fabricate GaN-based devices on a cheap and large area wafers (up to 200 mm), resulting in a significant reduction of the production costs. On the other hand, growing GaN on a foreign substrate results in high dislocation and defect densities which could affect the performance of the devices in terms of both losses and reliability issues. A so-called “buffer decomposition experiment” allowed to evaluate the role of the different layers which compose the vertical stack of a GaN-on-Silicon wafer by characterizing samples obtained by stopping the epitaxial growth at different stages of the process. It is demonstrated that both the thickness and the composition of the epitaxial stack, beside enhancing the breakdown voltage, improve the material quality by limiting the propagation of defects and dislocations. Moreover, a study on the reliability of the Aluminum Nitride layer grown on silicon is presented, showing that the AlN fails due to a wear-out process following a Weibull distribution. Furthermore, an extensive analysis on the reliability of the GaN-on-Silicon vertical stack is presented, as well as a systematic study on the failure statistic. It is shown that the time to failure of the GaN-on-Silicon stack is Weibull distributed, and, although it is weakly temperature-activated, it exponentially depends on the applied voltage. Moreover, the expected lifetime of the tested devices at the operating voltage is extracted. Aiming to further improve the performance of lateral High Electrons Mobility Transistors (HEMTs) in terms of vertical robustness and losses reduction, the impact of the resistivity of the silicon substrates has been evaluated. It is shown that highly resistive p-doped substrate results in a plateau region in the IV characteristic which considerably increases the vertical breakdown voltage of the devices. Nevertheless, the existence of a trade-off between the vertical robustness and the stability of the threshold voltage is demonstrated. A set of electrical characterization ascribes the threshold voltage shift to the positive backgating effect possibly related to the capacitive coupling of the partially depleted substrate which only occurs if lowly p-doped silicon is used. The origin of the plateau region is further investigated by means of a set of TCAD simulations, allowing to develop a two-diodes model which confirms the hypothesis on the substrate depletion. Even if stable and reliable lateral HEMTs are commercially available, their operating voltage is limited to ~ 900 V. In order to expand the applications field of the GaN-based devices to higher operating voltage, different device concepts have been developed so far. A promising solution is represented by (semi-)vertical trench gate devices, which are characterized by a thick drift layer where the OFF-state electric field spreads vertically in a bulky region, thus avoiding surface effects. Thanks to the vertical architecture, the OFF-state breakdown only depends on the thickness of the epitaxial stack, thus allowing to reach high breakdown voltages with a limited area consumption. Since the carriers must flow vertically, the gate of the devices lies in an etched trench, and it consists of a Metal Oxide Semiconductor (MOS) system. Within this thesis the gate leakage is deeply studied on devices with different gate dielectric, by means of electrical characterizations performed with different connection configurations and different bias polarities. Moreover, the gate capacitance is analytically calculated, and the experimental behavior observed for the Gate-Source and Gate-Drain capacitances over the applied voltage is discussed and modeled considering the GaN bias condition close to the dielectric interface. Lastly, a preliminary dielectric trap characterization is performed by evaluating the capacitance hysteresis induced by the electric field within different gate oxide materials. The last section of this work presents a custom setup developed for the characterization of the threshold voltage variations over the time. The stability of the threshold voltage is fundamental for allowing a device to operate properly in a switching converter. Standard pulsed systems used for the characterization of the threshold voltage allow to evaluate the impact of the bias level on the threshold variation, but no details on the time evolution can be obtained. The presented threshold transient setup monitors the threshold voltage variation over a wide time-interval, ranging from 10 µs to 100 s, allowing the analysis of the trapping and detrapping kinetics. Moreover, by monitoring the transient variation as a function of the temperature it is possible to full characterize (energy level and cross section) the traps involved in the observed instabilities.

The recent application of semiconductor materials, such as GaN, to power electronics has led to the development of a new generation of devices, which promise lower losses, higher operating frequencies and reductions in equipment size. The aim of this research is to study the capabilities of emerging GaN power devices, to understand their advantages, drawbacks, the challenges of their implementation and their potential impact on the performance of power converters. The thesis starts by presenting the development of a simple model for the switching transients of a GaN cascode device under inductive load conditions. The model enables accurate predictions to be made of the switching losses and provides an understanding of the switching process and associated energy flows within the device. The model predictions are validated through experimental measurements. The model reveals the suitability of the cascode device to soft-switching converter topologies. Two GaN cascode transistors are characterised through experimental measurement of their switching parameters (switching speed and switching loss). The study confirms the limited effect of the driver voltage and gate resistance on the turn-off switching process of a cascode device. The performance of the GaN cascode devices is compared against state-of-the-art super junction Si transistors. The results confirm the feasibility of applying the GaN cascode devices in half and full-bridge circuits. Finally, GaN cascode transistors are used to implement a 270V - 28V, 1.5kW, 1 MHz phase-shifted full-bridge isolated converter demonstrating the use of the devices in soft-switching converters. Compared with a 100 kHz silicon counterpart, the magnetic component weight is reduced by 69% whilst achieving a similar efficiency of 91%.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.

This thesis reports the main reliability results and failure mechanisms analysis on Gallium Nitride High Electron Mobility Transistors (GaN-HEMTs) obtained during the three years of PhD activity. The activity has been focused (i) on the main reliability issues of GaN HEMTs for both high frequency applications, like telecommunication or satellite applications, and high power applications, like high-power switching, (ii) on the failure analysis study of the critical device degradation under high electric-field bias conditions, (iii) and on the deep analysis of few parasitic effects that influence the static and dynamic behaviour of this technology. The work has followed the ending of the European project KorriGaN and few research collaborations with European research centers and private companies, exploiting the possibility of understanding what critical issues are actually considered the main threat of each specific application, with the opportunity of using the acquired knowledge on the other GaN transistor's operating fields. The first part of the thesis reports all the activity performed inside the last task of the reliability sub-project of the European project KorriGaN (Key ORganisation for Research on Integrated circuit in GaN technology), called Task-Force project. The purpose was to define the most critical working conditions over the last set of devices developed with the knowledge acquired along the project, and to study the failure mechanisms that reduce the main performances on short and long time period, on devices with different substrate quality. OFF-state reliability tests have shown the improved robustness of the technology with critical failure voltages beyond 100V, much better than older devices developed during the previous batches of KorriGaN project, underlining the great influence of a good device processing which can overcome poor quality of the epitaxial or the substrate layers. Looking at the possible dominant failure mechanisms in on-state conditions, and the related degradation accelerating factors of this robust technology, further analysis have highlighted a failure mechanism accelerated by hot-electron effects in the on-state medium-term reliability, with a negligible effect of the temperature. This result is one of the first reported study where the hot electrons clearly accelerate the performance degradation of GaN-HEMT devices. Similar reliability activities have been performed within the research collaboration with the European Space Agency. In particular, the work has been accomplished both with the activity performed inside the Padova microelectronic laboratories and with 5 cumulative months of placement at the ESA-ESTEC research center in the Netherlands. The studies on a quite stable technology of GaN-HEMT devices suitable for space applications have highlighted a good stability of the main static and RF performances with temperature. From the storage and the reliability analysis, the following results have been observed: good thermal stability of all the main parameters up to a quite critical temperature (T=350°C), beyond which diode degradation happens even during the first hours of test; optimal robustness capabilities above 100V of drain voltage during short-term tests at ambient temperature and at higher temperatures; stable behaviour of the space-designed devices even during high junction-temperature long-term DC stress. Following previous activities carried out on older devices of KorriGaN project, the next part of the thesis describes a deep analysis on the off-state reliability of GaN devices. Many efforts have been spent to better understand the failure mechanisms involved on the critical gate degradation of previous technologies of AlGaN/GaN HEMTs, due to some open questions that literature has still not completely explained. Despite the common acceptance of the last years on the "critical voltage" definition, some different results have been obtained testing the gate reverse-bias behaviour of GaN HEMTs, suggesting a failure mechanism correlated with the initial defectivity of the device under test. Further analysis with fixed negative gate bias have shown the same failure mechanism even below the estimated critical voltage. Failure analysis tools, guided by the electroluminescence emission images (EL), have been used for a deeper investigation on the physical evolution of the damage, following few failure analysis studies reported in the literature. Results have allowed to verify the presence of pre-existent defects and only sometimes to identify the appearance of stress-induced defects, highlighting the big difficulty and sometimes the impossibility to locate material cracks with nanometer-scale size on the semiconductor, at least at the early stages of the device degradation. On the last part of the thesis, some deep investigations on parasitic effects have been reported, with a special focus on the kink effect and on the current collapse effect. These activities have been performed inside the "Preliminary deep levels characterization in materials and test structures" work-package of the European project MANGA (Manufacturable GaN). Studying devices coming from old technologies, it has been possible to correlate the presence of the kink effect with a parasitic EL increase of the emission spectrum in the range of the yellow-red band, even correlated with a yellow broad-band peak founded during cathodoluminescence measurements (CL). These results well support a previous work that assumes the channel electrons interaction with two parasitic levels inside the GaN energy-gap as the origin of the kink effect. Studying AlGaN/GaN devices with different composition and doping of the barrier and the buffer layer respectively, it has been possible to correlate the presence of iron doping in the GaN buffer layer with an increase of the current collapse effect at the high electric-field quiescent points, identifying the activation energy of the trap responsible of this dynamic degradation. Furthermore, the combined use of Secondary Ion Mass Spectroscopy measurements (SIMS) and numerical simulations have allowed to provide a better physical demonstration of the experimental trend, confirming the measured results obtained on both the current collapse measurements and the trap activation-energy analysis.
Questa tesi riassume i principali risultati ottenuti nello studio dell'affidabilità e dei principali meccanismi di guasto nei transistor ad alta mobilità basati su Nitruro di Gallio (GaN-HEMT). L'attività di ricerca dei tre anni di dottorato è stata incentrata (i) sulle principali problematiche affidabilistiche degli HEMT su GaN adatti sia alle applicazioni ad alta frequenza, come il campo delle telecomunicazioni o satellitare, sia alle applicazioni ad alta potenza, come il campo degli switch per alta potenza, (ii) sull'analisi fisica del degrado causato dall'applicazione di alti campi elettrici, (iii) e sull'analisi approfondita di alcuni effetti parassiti che influenzano le caratteristiche statiche e dinamiche di tale tecnologia. Il lavoro ha seguito le ultime fasi del progetto europeo KorriGaN e alcune collaborazioni con centri di ricerca europei e aziende private, integrando la possibilità di capire quali possano essere le problematiche attualmente considerate più critiche in ogni specifica applicazione degli HEMT su GaN, con l'opportunità di trasferire le conoscenze acquisite anche all'interno degli altri campi operativi. La prima parte della tesi riassume tutta l'attività svolta all'interno del progetto Task-Force, attività conclusiva del settore affidabilità del progetto europeo KorriGaN (Key ORganisation for Research on Integrated circuit in GaN technology). Scopo del progetto era individuare le condizioni di funzionamento più critiche nell'ultimo set di dispositivi sviluppati a partire dai risultati ottenuti durante i precedenti anni di progetto, dando particolare importanza ai meccanismi di guasto responsabili della riduzione delle principali prestazioni nel breve e nel medio periodo, e ai diversi comportamenti indotti dalle diverse qualità dei substrati utilizzati nella crescita di tali dispositivi. I test di affidabilità a canale chiuso hanno dimostrato un significativo miglioramento della robustezza rispetto ai dispositivi sviluppati nei precedenti anni di progetto, con tensioni critiche di rottura oltre i 100V. Tali risultati sono stati confermati in tutti i wafer, indipendentemente dalla qualità del substrato, sottolineando come un buon processing dei dispositivi possa completamente mascherare la scarsa qualità dell'epitassia o dei substrati utilizzati. A canale aperto invece, l'analisi dei principali meccanismi di guasto e dei fattori di accelerazione del degrado ha mostrato un particolare meccanismo di degradazione accelerato dagli elettroni caldi (hot electrons) presenti all'interno del canale, con una trascurabile influenza della temperatura di test. Questo risultato è uno dei primi che mostra chiaramente l'influenza degli elettroni caldi nei meccanismi di degrado degli HEMT basati su Nitruro di Gallio. Analoghi studi su affidabilità e meccanismi di guasto sono stati eseguiti all'interno dell'attività di collaborazione con l'Agenzia Spaziale Europea. In particolare, l'attività è stata sviluppata sia all'interno dei laboratori di microelettronica di Padova, sia presso il centro di ricerca dell'Agenzia Spaziale ESA-ESTEC in Olanda, per un periodo complessivo di mobilità di 5 mesi. Gli studi sono stati eseguiti su una tecnologia di dispositivi ormai abbastanza consolidata, adattata alle esigenze specifiche delle applicazioni satellitari. I risultati hanno mostrato una buona stabilità delle principali perfomance DC e RF dei dispositivi al variare delle temperatura, e una buona stabilità nei test di storage fino ai 350°C, temperatura critica alla quale i diodi di gate cominciano rapidamente a degradare. Una significativa affidabilità è stata inoltre rilevata sia nei test a breve termine, con ottima stabilità oltre i 100V di tensione di drain a temperatura ambiente e ad alte temperature, sia nei test a lungo termine, eseguiti sui dispositivi designati per l'applicazione spaziale con test ad elevate temperature di giunzione. La successiva parte della tesi tratta un'analisi approfondita dell'affidabilità a canale chiuso dei transistor su GaN, seguendo precedenti lavori volti allo stesso scopo. Molti studi sono stati eseguiti per comprendere meglio quali siano i meccanismi di guasto coinvolti nella degradazione del gate delle precedenti tecnologie di GaN-HEMT, a causa di alcune questioni ancora irrisolte sulle quali la letteratura non ha ancora dato una completa chiarificazione. Nonostante la definizione di "critical voltage" (tensione critica) ormai comunemente accettata, alcuni test sul comportamento del gate in polarizzazione inversa hanno evidenziato risultanti contrastanti, suggerendo un diverso meccanismo di guasto correlato alla difettosità iniziale del campione. Altre analisi in polarizzazione costante hanno mostrato lo stesso meccanismo di guasto a tensioni di gate ben al di sotto della tensione critica. In seguito, su alcuni campioni sono state eseguite approfondite indagini di guasto per meglio comprendere l'evoluzione fisica del meccanismo di rottura, seguendo alcuni studi recentemente riportati in letteratura. Guidati dalle misure di elettroluminescenza (EL) precedentemente ottenute, tali analisi hanno permesso di verificare la presenza di difetti pre-esistenti e solo in certi casi di identificare la comparsa di alcuni difetti indotti dallo stress, evidenziando l'enorme difficoltà e talvolta l'impossibilità di localizzare dei difetti con dimensioni di scala nanometrica nei diversi strati di semiconduttore (cracks), almeno durante le prime fasi di degrado del campione. L'ultima parte della tesi riporta alcune indagini approfondite su specifici effetti parassiti presenti negli HEMT su GaN, in particolar modo analizzando l'effetto kink e il collasso di corrente (current collapse). Questi studi sono stati svolti all'interno del progetto europeo MANGA (Manufacturable GaN), nel settore dedicato all'indagine dei livelli energetici responsabili degli effetti parassiti. Studiando alcuni dispositivi appartenenti a tecnologie meno recenti, è stato possibile correlare la presenza dell'effetto kink con un aumento inusuale dello spettro di elettro-luminescenza nel range della banda rosso-gialla, a sua volta correlato con un largo picco di emissione nel giallo rilevato durante misure di catodo-luminescenza negli stessi dispositivi. Tali studi confermano un precedente lavoro in cui si assume che l'effeto kink sia originato dall'interazione degli elettroni nel canale con due livelli energetici parassiti presenti all'interno dell'energy gap del GaN. Studiando invece alcuni dispositivi HEMT basati sull'eterostruttura AlGaN/GaN, ma con differenti composizioni dello strato barriera e drogaggio dello strato buffer, è stato possibile correlare la concentrazione del ferro, usato come drogante all'interno del buffer, con un incremento del current collapse nei punti di polarizzazione a maggior campo elettrico, identificando poi l'energia di attivazione della trappola responsabile di tale degrado delle caratteristiche dinamiche. L'uso combinato di misure SIMS (Secondary Ion Mass Spectroscopy) e simulazioni numeriche hanno permesso di dare una dimostrazione fisica dell'effetto osservato nelle misure di laboratorio, confermando sia i risultati ottenuti in termini di collasso di corrente, sia la valutazione sperimentale dell'energia di attivazione della trappola.

Le projet industriel français MEGaN vise le développement de module de puissance à base de compostant HEMT en GaN. Une des application industrielle concerne l’aéronautique avec une forte contrainte en isolation galvanique (>100 kV/s) et en température ambiante (200°C). Le travail de thèse a été concentré sur une brique module de puissance (bras d’onduleur 650 V 30 A). L’objectif est d’atteindre un prototype de facteur de forme peu épais, 30 cm2 et embarquant l’ensemble des fonctions driver, alimentation de driver, la capacité de bus et capteur de courant phase. Cet objectif implique un fort rendement énergétique, et le respect de l’isolation galvanique alors que la contrainte en surface est forte. Le manuscrit, outre l’état de l’art relatif au module de puissance et notamment celui à base de transistor GaN HEMT, aborde une solution d’isolation de signaux de commande à base de micro-transformateur. Des prototypes de micro-transformateur ont été caractérisés et vieillis pendant 3000 H pour évaluer la robustesse de la solution. Les travaux ont contribué à la caractérisation de plusieurs composants GaN afin de mûrir des modèles pour la simulation circuit de topologie de convertisseur. Au sein du travail collaboratif MEGaN, notre contribution ne concernait pas la conception du circuit intégré (driver de grille), tout en ayant participé à la validation des spécifications, mais une stratégie d’alimentation du driver de grille. Une première proposition d’alimentation isolée pour le driver de grille a privilégié l’utilisation de composants GaN basse-tension. La topologie Flyback résonante avec clamp permet de tirer le meilleur parti de ces composants GaN mais pose la contrainte du transformateur de puissance. Plusieurs technologies pour la réalisation du transformateur ont été validées expérimentalement et notamment une proposition originale enfouissement du composant magnétique au sein d’un substrat polymère haute-température. En particulier, un procédé de fabrication peu onéreux permet d’obtenir un dispositif fiable (1000 H de cyclage entre - 55 ; + 200°C), avec un rendement intrinsèque de 88 % pour 2 W transférés. La capacité parasite d’isolation est réduite par rapport aux prototypes précédent. Deux prototypes d’alimentations à forte intégration utilisent soit les transistors GaN basse tension (2.4 MHz, 2 W, 74 %, 6 cm2), soit un circuit intégré dédié en technologie CMOS SOI, conçu pour l’application (1.2 MHz, 2 W, 77 %, 8.5 cm2). Le manuscrit propose par la suite une solution intégrable de mesure de courant de phase du bras de pont, basé sur une magnétorésistance. La comparaison expérimentale vis à vis d’une solution à résistance de shunt. Enfin, deux prototypes de convertisseur sont décrits, dont une a pu faire l’objet d’une validation expérimentale démontrant des pertes en commutation réduites
The french industrial project MEGaN targets the development of power module based on GaN HEMT transistors. One of the industrial applications is the aeronautics field with a high-constraint on the galvanic isolation (>100 kV/s) and ambient temperature (200°C). The intent of this work is the power module block (3 phases inverter 650 V 30 A). The goal is to obtain a small footprint module, 30 cm2, with necessary functions such as gate driver, gate driver power supply, bulk capacitor and current phase sensor. This goal implies high efficiency as well as respect of the constraint of galvanic isolation with an optimized volume. This dissertation, besides the state of the art of power modules and especially the GaN HEMT ones, addressed a control signal isolation solution based on coreless transformers. Different prototypes based on coreless transformers were characterized and verified over 3000 hours in order to evaluate their robustness. The different studies realized the characterization of the different market available GaN HEMTs in order to mature a circuit simulation model for various converter topologies. In the collaborative work of the project, our contribution did not focus on the gate driver chip design even if experimental evaluation work was made, but a gate driver power supply strategy. The first gate driver isolated power supply design proposition focused on the low-voltage GaN HEMT conversion. The active-clamp Flyback topology allows to have the best trade-off between the GaN transistors and the isolation constraint of the transformer. Different transformer topolgies were experimentally performed and a novel PCB embedded transformer process was proposed with high-temperature capability. A lamination process was proposed for its cost-efficiency and for the reliability of the prototype (1000 H cycling test between - 55; + 200°C), with 88 % intrinsic efficiency. However, the transformer isolation capacitance was drastically reduced compared to the previous prototypes. 2 high-integrated gate driver power supply prototypes were designed with: GaN transistors (2.4 MHz, 2 W, 74 %, 6 cm2), and with a CMOS SOI dedicated chip (1.2 MHz, 2 W, 77 %, 8.5 cm2). In the last chapter, this dissertation presents an easily integrated solution for a phase current sensor based on the magnetoresistance component. The comparison between shunt resistor and magnetoresistance is experimentally performed. Finally, two inverter prototypes are presented, with one multi-level gate driver dedicated for GaN HEMT showing small switching loss performance

Cette thèse étudie les possibilités de réduction des interférences électromagnétiques pour les convertisseurs d'électroniques de puissance utilisant des transistors GaN dans trois domaines principaux: la stratégie de contrôle, la conception des circuits imprimés ainsi que l'agencement des composants de puissance et les éléments magnétiques à haute fréquence. Sur la base d'un convertisseur Buck, l’impact de la contribution de la commutation dure et douce sur le bruit conduit généré (mode commun (CM) et mode différentiel (DM)) a été étudiée. L'effet positif de la commutation douce sur la réduction des perturbations CEM dans une gamme de fréquence spécifique a été démontré. L'impact des attributs de la conception de l'agencement a également été observé et la nécessité de l'optimiser a été soulignée. Ensuite, une étude détaillée de l'identification des éléments parasites dans un seul bras d'onduleur est présentée. Des domaines spécifiques de préoccupation ont été détaillés et examinés plus loin dans la thèse. Le flux de travail de simulation développé dans Digital Twin utilisé pour étudier l'impact des éléments de disposition individuels sur la CEM est présenté. Le banc d'essai de laboratoire utilisé pour les mesures CEM est également présenté, ainsi qu'une description des précautions nécessaires. En outre, les deux concepts clés mis en œuvre dans l'agencement - le blindage et le Power-Chip-on-Chip (PCoC) - sont présentés. Leur efficacité dans la réduction des interférences électromagnétiques de près de 20~dB a été confirmée par la simulation et l'expérimentation. Enfin, le concept d'inducteur intégré est présenté, qui peut être mis en œuvre en même temps que les solutions précédentes. L'efficacité d'un inducteur intégré planaire connecté au point central du pont a été démontrée par des études de simulation. La méthode de l'auteur pour identifier l'impédance de l'inducteur intégré et les principaux éléments parasites (en termes de CEM) a également été développée et présentée en détail. En conclusion, ce travail présente une série de solutions qui réduisent de manière significative l'EMI dans les convertisseurs à base de GaN, qui ont été validées par simulation et expérience et qui peuvent être appliquées à tous les types de convertisseurs électroniques de puissance
The thesis investigates the possibility of EMI mitigation for power electronic converters with GaN transistors in three key areas: control strategy, layout design, and integrated magnetic filter. Based on a Buck converter, the contribution of hard and soft switching to the generated conducted noise (Common Mode (CM) and Differential Mode (DM)) has been investigated. The positive effect of soft switching on EMI reduction in a specific frequency range was demonstrated. The impact of layout design attributes was also observed and the need to optimize it was highlighted. Next, a detailed study of the identification of parasitic elements in a single inverter leg is presented. Specific areas of concern were detailed and considered later in the thesis. The developed simulation workflow in Digital Twin used to study the impact of individual layout elements on EMC is presented. The laboratory test bench used for EMC measurements is also presented, together with a description of the necessary experimental precautions. Furthermore, the two key concepts implemented in the layout - shielding and Power-Chip-on-Chip (PCoC) - are presented. Their effectiveness in reducing EMI by almost 20~dB was confirmed by simulation and experiment. Finally, the Integrated Inductor concept is presented, which can be implemented together with the previous solutions. The effectiveness of a planar Integrated Inductor connected to the middle point of the bridge was demonstrated by simulation studies. The author's method for identifying the impedance of the Integrated Inductor and the key parasitic elements (in terms of EMC) has also been developed and presented in details. In conclusion, the work presents a series of solutions that significantly reduce EMI in GaN-based converters, which have been validated by simulation and experiment and can be applied to all types of power electronic converters

GaN has the potential to revolutionize the high power electronics industry, enabling high voltage applications and better power conversion efficiency due to its intrinsic material properties and newly available high purity bulk substrates. However, unintentional impurity incorporation needs to be reduced. This reduction can be accomplished by reducing the source of contamination and exploration of extreme growth conditions which reduce the incorporation of these contaminants. Newly available bulk substrates with low threading dislocations allow for better study of material properties, as opposed to material whose properties are dominated by structural and chemical defects. In addition, very thick films can be grown without cracking due to exact lattice and thermal expansion coefficient match. Through chemical and electrical measurements, this work aims to find growth conditions which reduces contamination without a severe impact on growth rate, which is an important factor from an industry standpoint. The proposed thicknesses of these devices are on the order of one hundred microns and requires tight control of the intentional dopants.
Doctor of Philosophy
GaN is a compound semiconductor which has the potential to revolutionize the high power electronics industry, enabling new applications and energy savings due to its inherent material properties. However, material quality and purity requires improvement. This improvement can be accomplished by reducing contamination and growing under extreme conditions. Newly available bulk substrates with low defects allow for better study of material properties. In addition, very thick films can be grown without cracking on these substrates due to exact lattice and thermal expansion coefficient match. Through chemical and electrical measurements, this work aims to find optimal growth conditions for high purity GaN without a severe impact on growth rate, which is an important factor from an industry standpoint. The proposed thicknesses of these devices are on the order of one hundred microns and requires tight control of impurities.

Auxiliary power supply (APS) plays a key role in ensuring the safe operation of the main circuit elements including gate drivers, sensors, controllers, etc. in medium voltage (MV) silicon carbide (SiC)-based converter systems. Such a converter requires APS to have high insulation capability, low common-mode coupling capacitance (Ccm ), and high-power density. Furthermore, considering the lifetime and simplicity of the auxiliary power supply system design in the MV converter, partial discharge (PD) free and multi-load driving ability are the additional two factors that need to be addressed in the design. However, today’s state-of-the-art products have either low power rating or bulky designs, which does not satisfy the demands. To improve the current designs, this thesis presents a 1 MHz isolated APS design using gallium nitride (GaN) devices with MV insulation reinforcement. By adopting LCCL-LC resonant topology, the proposed APS is able to supply multiple loads simultaneously and realize zero voltage switching (ZVS) at any load conditions. Since high reliability under faulty load conditions is also an important feature for APS in MV converter, the secondary side circuit of APS is designed as a regulated stage. To achieve MV insulation (> 20 kV) as well as low Ccm value (< 5 pF), a current-based transformer with a single turn structure using MV insulation wire is designed. Furthermore, by introducing different insulated materials and shielding structures, the APS is capable to achieve different partial discharge inception voltages (PDIV). In this thesis, the transformer design, resonant converter design, and insulation strategies will be detailly explained and verified by experiment results. Overall, this proposed APS is capable to supply multiple loads simultaneously with a maximum power of 120 W for the sending side and 20 W for each receiving side in a compact form factor. ZVS can be realized regardless of load conditions. Based on different insulation materials, two different receiving sides were built. Both of them can achieve a breakdown voltage of over 20 kV. The air-insulated solution can achieve a PDIV of 6 kV with Ccm of 1.2 pF. The silicone-insulated solution can achieve a PDIV of 17 kV with Ccm of 3.9 pF.
M.S.
Recently, 10 kV silicon carbide (SiC) MOSFET receives strong attention for medium voltage applications. Asit can switch at very high speed, e.g. > 50 V/ns, the converter system can operate at higher switching frequency condition with very small switching losses compared to silicon (Si) IGBT [8]. However, the fast dv/dt noise also creates the common mode current via coupling capacitors distributed inside the converter system, thereby introducing lots of electromagnetic interference (EMI) issues. Such issues typically occur within the gate driver power supplies due to the high dv/dt noises across the input and output of the supply. Therefore, the ultra-small coupling capacitor (<5 pF) of a gate driver power supply is strongly desired.[37] To satisfy the APS demands for high power modular converter system, a solution is proposed in this thesis. This work investigates the design of 1 MHz isolated APS using gallium nitride (GaN) devices with medium voltage insulation reinforcement. By increasing switching frequency, the overall converter size could be reduced dramatically. To achieve a low Ccm value and medium voltage insulation of the system, a current-based transformer with a single turn on the sending side is designed. By adopting LCCL-LC resonant topology, a current source is formed as the output of sending side circuity, so it can drive multiple loads importantly with a maximum of 120 W. At the same time, ZVS can use realized with different load conditions. The receiving side is a regulated stage, so the output voltage can be easily adjusted and it can operate in a load fault condition. Different insulation solutions will be introduced and their effect on Ccm will be discussed. To further reduce Ccm, shielding will be introduced. Overall, this proposed APS can achieve a breakdown voltage of over 20 kV and PDIV up to 16.6 kV with Ccm<5 pF. Besides, multi-load driving ability is able to achieve with a maximum of 120 W. ZVS can be realized. In the end, the experiment results will be provided.

Il y a actuellement un intérêt croissant pour la construction des dispositifs électroniques à semiconducteur pour les applications domotiques. La technologie des semiconducteurs de puissance a été essentiellement limitée au silicium. Récemment, de nouveaux matériaux ayant des propriétés supérieures sont étudiés en tant que remplaçants potentiels, en particulier : le nitrure de gallium et le carbure de silicium. L'état actuel de développement de la technologie 4H-SiC est beaucoup plus mature que pour le GaN. Cependant, l'utilisation de 4H-SiC n’est pas une solution économiquement rentable pour la réalisation des redresseurs Schottky 600 V. Les progrès récents dans le développement des couches épitaxiées de GaN de type n sur substrat Si offrent de nouvelles perspectives pour le développement des dispositifs de puissance à faible coût. C’est dans ce cadre que ma thèse s’inscrit pour réaliser avec ce type de substrat, un redresseur Schottky de puissance avec un calibre en tension de l’ordre de 600V. Deux architectures de redresseurs sont exposées. La première est une architecture pseudo-verticale proposée dans le cadre du projet G2ReC et la deuxième est une architecture latérale à base d’hétérojonction AlGaN/GaN obtenue à partir d'une structure de transistor HEMT. L’optimisation de ces deux dispositifs en GaN est issue de simulation par la méthode des éléments finis. Dans ce cadre, une adaptation des modèles de simulation à partir des paramètres physiques du GaN extraits depuis la littérature a été effectuée. Ensuite, une étude d’influence des paramètres géométriques et technologiques sur les propriétés statiques en direct et en inverse des redresseurs a été réalisée. Enfin, des structures de tests ont été fabriquées et caractérisées afin d’évaluer et d’optimiser le caractère prédictif des simulations par éléments finis. Ces études nous ont conduit à identifier l'origine des limites des structures de première génération et de définir de nouvelles structures plus performantes
There is increasing interest in the fabrication of power semiconductor devices in home automation applications. Power semiconductor technology has been essentially confined to Si. Recently, new materials with superior properties are being investigated as potential replacements, in particular silicon carbide (SiC) and gallium nitride (GaN). The current state of development of SiC technology is much more mature than for GaN. However, the use of 4H-SiC is not a cost effective solution for realizing a medium and high voltage Schottky diode. Recent advances on the development of thick n-type GaN epilayers on Si substrate offer new prospects for the development of a low-cost Schottky rectifiers for at least medium voltage range 600 V. In the context of our thesis, two types of GaN based rectifier architectures have been studied. The first one is a pseudo-vertical architecture proposed during previous G2ReC project. The second one has a lateral structure with AlGaN/GaN heterojunction, derived from a HEMT structure. The optimization of the Schottky rectifiers has been achieved by finite element simulations. As a first step, the models are implemented in the software and adjusted with the parameters described in the literature. The influence of the geometrical and physical parameters on the specific on-resistance and on the breakdown voltage has been analysed. Finally, the test devices have been realized and characterized to optimize and to validate the parameters of these models. These studies lead to identify the limits of the structures and create a new generation of powerful structures

京都大学
0048
新制・課程博士
博士(工学)
甲第22447号
工博第4708号
新制||工||1735(附属図書館)
京都大学大学院工学研究科電子工学専攻
(主査)教授 木本 恒暢, 教授 山田 啓文, 准教授 船戸 充
学位規則第4条第1項該当
Doctor of Philosophy (Engineering)
Kyoto University
DFAM

Depuis plusieurs années, la technologie de transistors à effet de champ à haute mobilité (HEMT) sur Nitrure de Gallium (GaN) a démontré un potentiel très important pour la montée en puissance et en fréquence des dispositifs. Malheureusement, la présence des effets parasites dégrade les performances dynamiques des composants ainsi que leur fiabilité à long-terme. En outre, l'origine de ces pièges et leur emplacement physique restent incertains jusqu'à aujourd'hui. Une partie du travail de recherche menée dans cette thèse est axée sur la caractérisation des pièges existant dans les dispositifs HEMTs GaN à partir de mesures de paramètre S basse fréquence (BF), les mesures du bruit BF et les mesures I(V) impulsionnelles. Parallèlement, nous avons effectué des simulations physiques basées sur TCAD afin d'identifier la localisation des pièges dans le transistor. De plus, notre étude expérimentale de caractérisation et de simulation montre que les mesures BF pourraient constituer un outil efficace pour caractériser les pièges existant dans le buffer GaN, alors que la caractérisation de Gate-lag pourrait être plus utile pour identifier les pièges de barrière des dispositifs GaN HEMT. La deuxième partie de ce travail de recherche est axée sur la caractérisation des dispositifs AlN/GaN HEMT sur substrat Si et SiC. Une méthode d’extraction simple et efficace de la résistance canal et de la résistance de contact a été mise au point en utilisant conjointement la simulation physique et les techniques de caractérisation. Le principe de l’extraction de la résistance canal est basée sur la mesure de la résistance RON. Celle-ci est calculée à partir des mesures de courant de drain IDS et de la tension VDS pour différentes valeurs de températures En outre, nous avons procédé à une évaluation complète du comportement thermique de ces composants en utilisant conjointement les mesures et les simulations thermiques tridimensionnelles (3D) sur TCAD. La résistance thermique (RTH) a été extraite pour les transistors de différentes géométries à l'aide des mesures et ensuite validée par les simulations thermiques sur TCAD
GaN High Electron Mobility Transistors (HEMTs) have demonstrated their capabilities to be an excellent candidate for high power microwave and mm-wave applications. However, the presence of traps in the device structure significantly degrades the device performance and also detriments the device reliability. Moreover, the origin of these traps and their physical location remains unclear till today. A part of the research work carried out in this thesis is focused on characterizing the traps existing in the GaN/AlGaN/GaN HEMT devices using LF S-parameter measurements, LF noise measurements and drain-lag characterization. Furthermore, we have used TCAD-based physical device simulations in order to identify the physically confirm the location of traps in the device. Moreover, our experimental characterization and simulation study suggest that LF measurements could be an effective tool for characterizing the traps existing in the GaN buffer whereas gate-lag characterization could be more useful to characterize the AlGaN barrier traps of GaN HEMT devices. The second aspect of this research work is focused on characterizing the AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrate. We attempt to characterize the temperature-dependent on-resistance (RON) extraction of these devices using on-wafer measurements and TCAD-based physical simulations. Furthermore, we have proposed a simplified methodology to extract the temperature and bias-dependent channel sheet resistance (Rsh) and parasitic series contact resistance (Rse) of AlN/GaN HEMT devices. Further, we have made a comprehensive evaluation of thermal behavior of these devices using on-wafer measurements and TCAD-based three-dimensional (3D) thermal simulations. The thermal resistance (RTH) has been extracted for various geometries of the device using measurements and validated using TCAD-thermal simulations

Switch mode power supplies are widely used in different applications. High efficiency and high power density are two driving forces for power supply systems. However, high dv/dt and di/dt in switch mode power supplies will cause severe EMI noise issue. In a typical front-end converter, the EMI filter usually occupies 1/3 to 1/4 volume of total converter. Hence, reducing the EMI noise of power converter can help reduce the volume of EMI filter and improving the total power density of the converter. The EMI noise can be separated as differential mode (DM) noise and common mode (CM) noise. For off-line switch mode power supplies, DM noise is dominated by PFC converter. CM noise is a more complicated issue. It is contributed by both PFC converter and DC/DC converter. The DM noise is contributed by input current ripple. Therefore, one method to reduce DM noise is interleaving. There are three methods to reduce CM noise: symmetry, balance and shielding. The idea of symmetry concept is generating another dv/dt source to cancel the original dv/dt source. However, this method is very difficult to achieve and usually has more loss. The balance technique forms a Wheatstone bridge circuit to minimize the CM noise. However, the balance technique cannot achieve very good attenuation at high frequency due to parasitics. Shielding technique is very popular in isolated DC-DC converters to reduce CM noise. However, the previous shielding method requires precise control of parasitic capacitance and dv/dt. It is very difficult to achieve good CM noise attenuation in mass production. In this dissertation, a novel one-layer shielding method for PCB winding transformer is provided. This shielding technique can block CM noise from primary side and also cancel the CM noise from secondary side. In addition, shielding does not increase the loss of converter too much. Furthermore, this shielding technique can be applied to matrix transformer structure. For matrix transformer LLC converter, the inter-winding capacitor is very large and will cause severe CM noise problem. By adding shielding layer, CM noise has been greatly reduced. Although flyback and LLC resonant converter are used as examples to demonstrate the concept, the novel shielding technique can also be applied to other topologies that have similar transformer structure. With Wide-band-gap power devices, the switching frequency of power converter can be pushed 10 times higher than traditional Si based converters. This provides an opportunity to use PCB winding magnetics. In order to reduce the switching loss, critical conduction mode is used in PFC converter. Because of high AC current in the inductor winding, litz wire was used to build the inductor. However, with coupled inductor concept and the proposed winding structure, CRM inductor is integrate into PCB winding for the first time. Furthermore, balance technique is applied to reduce CM noise for PFC converter. With PCB winding, the balance technique has better high frequency performance. The PCB winding inductor can achieve high power density, high efficiency and automated manufacture. Traditionally, two-stage EMI filter was utilized to achieve required EMI noise attenuation. With the developed high frequency, low EMI noise converter, single-stage EMI filter can be applied. However, there are self-parasitic and mutual parasitic components to impact the filter performance on high frequency. The near-field measurement is utilized to visualize the magnetic flux near those filter components. Thus, a better filter design and layout can be achieved to have better high frequency performance.
Ph. D.

Gallium Nitride is a promising wide-bandgap material for electronics. With GaN based devices it is possible to achieve higher operative frequencies and power densities in comparison to Silicon. The first GaN-based High Electron Mobility Transistor (HEMT) has been designed in the 1995, and after twenty years this technology start to be ready to compete in the market with Silicon-based devices. There are several reason why it was necessary all this time to obtain a stable technology. Unlike Silicon, it is still not possible to grow a gallium nitride crystal starting from a seed, with reasonable quality dimensions and costs. Thus, itis necessary to grow it on different substrates, like Silicon Carbide, Sapphire or Silicon. Therefore, the obtained crystals have a high defects concentration that limits the device performances. With the optimization of the process and the introduction suitable nucleation layer on the substrate it is now possible to grow GaN wafers with a tolerable defectivity. The main problems induced by the defects are trap states and reliability issues. The trap states generate problems during dynamic operation, inducing a drop in the output characteristics. In addition to this recoverable phenomena, the GaN-HEMTs can even present problem of reliability, that have been widely explored in the past. Nowadays, the estimated device life time of the last technologies allow to start the production of electronics both for consumer market than for the more demanding space applications. Within this work it will be presented a summary of the research activity performed during my PhD. In the first part is presented a short summary of the state of the art of GaN-HEMT technology. In the last two years a lot of new results have been demonstrated in literature, showing the last technological improvements. Then, a short summary on the trapping phenomena and reliability issue is presented, that is fundamental to understand all the obtained results. The research activities involved the two main GaN-based HEMTs applications: the RF devices and the power switching transistors. For the RF applications the transistor is used as an amplifier, in a frequency range from 1 GHz to 100 GHz. The main applications are radar and telecommunications for mobile phone, radio and satellites. I collaborated in a project of the European Space Agency, with subject “Preliminary Validation of Space Compatible Foundry Processes”. They will be presented all the results of the reliability assessment carried out within this project. The purpose was to validate a GaN-HEMT technology for space applications, trying to estimate the device lifetime and the failure mechanisms. We will see that the two analysed technologies are very stable, and the estimated life time exceed the twenty years. Nevertheless, not all the failure mechanisms are clear, but we found some degradation signatures that can be related to the gate metallization. On the side of power switching transistors I will report first the results obtained in a collaboration with ON Semiconductor on the development of d-mode MIS-HEMTs. Our role was to give a feedback on the device performance improvement, mainly focused on the on-resistance. It represents indeed one of the main problems of GaN-HEMT working in switching conditions and it is mainly related to trapping phenomena. Then, we developed a new original measurement procedure that allows to test the devices in a condition closer to the operative one. This new setup helps us to demonstrate the impressive stability of the last device generations. Now this technology is ready to work at 600 V in switching operation, with performances better than Silicon. The second part about the power devices will report the work carried out during the period by the Ferdinand-Braun-Institut, Leibniz-Institut für Hochfrequenztechnik (FBH), in Berlin. The target was to investigate the reliability of the p-GaN devices developed by the research center by means of long term on-state life test. The gate leakage current is suspected to be one of the main problem for the reliability of this kind of device in on-state operation. However, there are not many works in literature that analyse this issue, and we will see how our test helps to consolidate one of the proposed degradation modes. Within this analysis it was fundamental the role of physical based simulations, for which is devoted a separated chapter. The simulations were very helpful for the understanding of the degradation mechanism. They allowed us to have a complete vision of the conduction mechanisms and of the device weakness. In this way we can give fundamental information to the device developers, in particular which device regions need to be improved.
Il nitruro di gallio è un promettente materiale a semiconduttore con ampio energy gap. Tramite dispositivi bastai su GaN è possibile raggiungere frequenze operative e densità di potenza maggiori in confronto al silicio. Il primo transistor HEMT (High Electron Mobility Transistor) basato su GaN è stato sviluppato nel 1995, e dopo vent'anni questa tecnologia inizia ad essere pronta a competere sul mercato con dispositivi basati su silicio. Ci sono diversi motivi per cui è servito del tempo per ottenere una tecnologia stabile. A differenza del silicio, non è possibile crescere cristalli di nitruro di gallio partendo da un seme, non almeno con costi, qualità e dimensioni ragionevoli. Perciò è necessario crescere il nitruro di gallio su substrati diversi, come il carburo di silicio, lo zaffiro o il silicio. Perciò, i cristalli ottenuti hanno una concentrazione di difetti che limita le prestazioni dei dispositivi. Con l'ottimizzazione del processo e l'introduzione di un adeguato strato di transizione, detto nucleation layer, è possibile ottenere dei wafer con una difettività tollerabile. Il problema principale introdotto dai difetti sono gli stati trappola e questioni di affidabilità. Gli stati trappola danno problemi durante il funzionamento dei transistor, creando un calo temporaneo della caratteristica di uscita. Oltre a questo fenomeno temporaneo gli HEMT basati su GaN presentano problemi di affidabilità, ampiamente studiati in passato. Al giorno d'oggi il tempo di vita medio stimato delle ultime generazioni di transistor permette la produzione di dispositivi elettronici sia per il settore commerciale che per applicazioni spaziali. In questo lavoro sarà presentato un riassunto delle attività di ricerca svolte durante il dottorato. Nella prima parte è presentato un riepilogo dello stato dell'arte della tecnologia GaN-HEMT. Negli ultimi due anni in letteratura sono stati dimostrati nuovi risultati, rivelando un notevole miglioramento tecnologico. Verrà poi presentato un breve riassunto sui fenomeni di trapping e sull'affidabilità, che risulterà fondamentale per comprendere al meglio i risultati ottenuti. Le attività di ricerca hanno coinvolto le due applicazioni principali dei transistor GaN-HEMT: i dispositivi RF e i transistor di potenza. Per applicazioni RF il transistor è usato come amplificatore, in un range di frequenze tra 1 GHz e 100 GHz. Le applicazioni principali sono radar e telecomunicazioni per telefonia mobile, radio e satellitare. Ho collaborato in un progetto dell'Agenzia Spaziale Europea dal titolo: “Preliminary Validation of Space Compatible Foundry Processes”. Verranno presentati i risultati della valutazione dell'affidabilità svolta in questo progetto. Lo scopo era di validare la tecnologia GaN-HEMT per applicazioni spaziali, provando a stimare il tempo di vita dei dispositivi e i meccanismi di guasto. Vedremo come la tecnologia analizzata sia stabile, con un tempo di vita stimato che oltrepassa i vent'anni. Ciò nonostante, non sono ancora chiari tutti i meccanismi di guasto, ma è stata trovata qualche caratteristica tipica del degrado legata alla metallizzazione di gate. Dal lato dei transistor di potenza verranno riportati prima i risultati ottenuti nella collaborazione con ON Semiconductor, nello sviluppo di dispositivi MISHEMT normally-on. Il nostro ruolo era di dare un feedback all'azienda riguardo alle performance dei dispositivi, in particolare in termini di resistenza in on-state. Questo rappresenta infatti uno dei problemi maggiori dei transistor GaNHEMT che lavorano in condizioni switching ed è dovuto a fenomeni di trapping. Poi, è stato sviluppata una nuova procedura di misura che permette di testare i dispositivi in condizione vicine a quelle operative. Questo nuovo setup è stato d'aiuto per dimostrare l'eccezionale stabilità delle ultime generazioni di transistor. Ora questa tecnologia è pronta per lavorare a 600 V con prestazioni migliori di quelle del silicio. La seconda parte relativa ai dispositivi di potenza parlerà del lavoro svolto presso il Ferdinand-Braun-Institut, Leibniz-Institut für Hochfrequenztechnik (FBH), a Berlino. L'obiettivo principale era quello di investigare l'affidabilità dei dispositivi p-GaN sviluppati presso il centro di ricerca, tramite stress in on-state a lungo termine. La corrente di leakage di gate è sospettata di essere uno dei problemi principali per l'affidabilità di questo tipo di dispositivi in on-state. Tuttavia, non ci sono tanti lavori in letteratura che analizzano il problema, e si vedrà come i test svolti aiutano a consolidare uno dei modelli proposti. In questa analisi è stato fondamentale il ruolo delle simulazioni, a cui è stato riservato un capitolo a parte. Le simulazioni sono state di grande aiuto nella comprensione dei meccanismi di guasto e hanno permesso di avere una visione completa dei meccanismi di conduzione e dei punti deboli del dispositivo. In questo modo possono essere date informazioni essenziali a chi sviluppa i transistor, in particolare quali sono le regioni del dispositivo che andrebbero migliorate.

Wide band-gap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have been widely investigated these years for their preferred operation at higher switching frequency, higher blocking voltage, higher temperature, with a compacter volume, in comparison with the traditional silicon (Si) devices. SiC MOSFETs have been utilized in photovoltaic systems, wind turbine converters, electric vehicles, solid-state transformers, more electric ships, and airplanes. GaN based transistors have also been adopted in the DC-to-DC converters in data centers, personal computers, AC-to-DC power factor correction converters for the consumer electronic adaptors, and DC-to-AC photovoltaic micro-inverters. The first part of this dissertation is regarding the lifetime modeling and condition monitoring for the SiC MOSFETs. Since SiC-based devices have different failure modes and mechanisms compared with Si counterparts, a comprehensive review will be conducted to develop accurate lifetime prediction, condition monitoring, and lifetime extension strategies. First, a novel comprehensive online updated system-level lifetime modeling approach will be presented. Second, to monitor the SiC MOSFET ageing, the typical degradation indicators of SiC MOSFET gate oxide will be investigated. Third, to measure the junction temperature, the dynamic temperature-sensitive electrical parameters for the medium-voltage SiC devices will be studied. The other part is the topology investigation of these emerging wide band-gap devices. A generalized topology that would leverage the advantages of the wide band-gap devices will be introduced and analyzed in detail. Following it is a new evaluation index for comparing different topologies with the consideration of the semiconductor die information. The topology and its derivatives will be utilized in the subsequent chapters for three applications. First, a 100 kW switched tank converter (STC) will be designed using SiC MOSFETs for transportation power electronic systems. Second, an updated STC topology integrating with the partial-power voltage regulation will be introduced for electric vehicle applications. Third, two novel single-phase resonant multilevel modular boost inverters will be designed based on the voltage-regulated STC. These topologies will be validated through designed prototypes. As a result, the high power density and high efficiency will be realized by combining the well-suited topologies and the advantages of the WBG devices.

La gestion de l'énergie constitue l'un des plus importants défis que notre société va devoir relever au cours du XXIe siècle. Dans ce contexte, il est indispensable de concevoir de nouveaux interrupteurs de puissance à semi-conducteurs afin d'assurer une meilleure gestion de l'énergie électrique. Les matériaux à large bande interdite tels que le GaN sont les candidats adéquats pour répondre à ce nouveau défi. L'inconvénient actuel et majeur des transistors à haute mobilité (High Electron Mobility Transistor - HEMT -) en Nitrure de Gallium (GaN) conventionnels est que leur blocage se fait à des tensions négatives ; c'est ce que l'on appelle un composant normally-on ("normalement fermé"). Or, la plupart des applications de puissance requièrent l'utilisation d'interrupteurs normally-off ("normalement ouverts"). Plusieurs architectures de HEMT en GaN normally-off ont été proposées dans la littérature (" recess gate " partiel ou total, grille P-GaN, cascode associant un HEMT en GaN et un transistor MOS en Si, etc...) mais chacune de ces solutions présente des inconvénients aussi bien technologiques qu'en termes de performances. Nos travaux se proposent d'explorer une nouvelle voie pour obtenir des interrupteurs HEMT AlGaN/GaN normally-off. L'idée générale repose sur le principe de fonctionnement d'un JFET dans lequel la largeur de la région de conduction N serait tellement étroite que les Zones de Charge d'Espace (ZCE) de déplétion des jonctions PN se rejoignent naturellement de manière à assurer la déplétion totale de la zone de type N. Le développement des zones de charge d'espace à l'équilibre thermodynamique étant faible, la conception des grilles doit obligatoirement passer par une nano-structuration. La grille du HEMT développée est donc constituée d'une succession de caissons ou "puits" GaN de type P dont la profondeur doit traverser le canal 2DEG et l'espacement entre deux puits permettre le recouvrement naturel des zones de charge d'espace. Après avoir dressé un état de l'art des structures HEMT AlGaN normally-off, nous avons dans un premier temps effectué des simulations physiques à éléments finis à l'aide de SENTAURUS TCAD, en 2D et 3D, afin de définir la meilleure structure de grille permettant d'obtenir la fonctionnalité normally-off désirée. Nous avons ainsi optimisé les paramètres géométriques et technologiques des caissons P-GaN (profondeur, largeur, espacement et dopage P du GaN) ainsi que le taux d'aluminium de la couche d'AlGaN. A partir des résultats obtenus, nous avons simulé la structure HEMT dans sa globalité et nous avons ainsi pu valider ce nouveau concept. Nous avons ensuite développé et optimisé les différentes étapes technologiques critiques permettant d'obtenir la nano-structuration de la grille à savoir : la lithographie électronique de la résine HSQ afin de réaliser des caissons P-GaN à des dimensions nanométriques, la gravure plasma des puits et leur remplissage avec du GaN dopé Magnésium par épitaxie localisée par jets moléculaires. Nous décrivons par la suite le procédé de fabrication complet du HEMT à grille P-GaN nano-structurée. Nous présentons enfin les différentes caractérisations physiques et électriques de la structure HEMT ainsi réalisée
Energy management is one of the biggest challenges facing our society in the 21st century. In this context, it is essential to design new semiconductor power switches to ensure better management of electrical energy. Wide bandgap materials such as GaN are ideal candidates for meeting this new challenge. The current major disadvantage of conventional Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) is that they are blocked at negative voltages(normally-on device). However, most power applications require the use of normally-off switches. Several normally-off GaN HEMT architectures have been proposed in the literature (partial or total recess gate, P-GaN gate, cascode combining a GaN HEMT and a Si MOS transistor, etc.), but each of these solutions has drawbacks in terms of both technology and performance. The aim of our work is to explore a new way of obtaining normally-off AlGaN/GaN HEMT switches. The general idea is based on the operating principle of a JFET in which the width of the N conduction region is so narrow that the depletion Space Charge Regions (SCRs) of the PN junctions naturally come together to ensure total depletion of the N-type region. Since the development of space charge regions at thermodynamic equilibrium is low, the design of grids must necessarily involve nano-structuring. The HEMT gate developed therefore consists of a succession of P-type GaN 'wells' whose depth must cross the 2DEG channel and the spacing between two wells must allow the space charge zones to overlap naturally. After reviewing the state of the art in AlGaN normally-off HEMT structures, we first carried out physical finite-element simulations using SENTAURUS TCAD, in 2D and 3D, to define the best gate structure for achieving the desired normally-off functionality. We optimised the geometric and technological parameters of the P-GaN wells (depth, width, spacing and P-doping of the GaN) as well as the aluminium content of the AlGaN layer. Based on the results obtained, we simulated the entire HEMT structure, enabling us to validate this new concept. We then developed and optimised the various critical technological steps required to achieve the nano-structuring of the gate, namely: electron lithography of the HSQ resin to produce P-GaN wells with nanometric dimensions, plasma etching of the wells and filling them with GaN doped with magnesium by localised molecular beam epitaxy. We then describe the complete manufacturing process for the nano-structured P-GaN HEMT. Finally, we present the various physical and electrical characterisations of the resulting HEMT structure

This paper describes the design, fabrication, and testing of a 1.2 kV, 6.5 mΩ, half-bridge, SiC MOSFET power module to evaluate the impact of parametric device tolerances on electrical and thermal performance. Paralleling power devices increases current handling capability for the same bus voltage. However, inherent parametric differences among dies leads to unbalanced current sharing causing overstress and overheating. In this design, a symmetrical DBC layout is utilized to balance parasitic inductances in the current pathways of paralleled dies to isolate the impact of parametric tolerances. In addition, the paper investigates the benefits of flexible PCB in place of wire bonds for the gate loop interconnection to reduce and minimize the gate loop inductance. The balanced modules have dies with similar threshold voltages while the unbalanced modules have dies with unbalanced threshold voltages to force unbalanced current sharing. The modules were placed into a clamped inductive DPT and a continuous, boost converter. Rogowski coils looped under the wire bonds of the bottom switch dies to observe current behavior. Four modules performed continuously for least 10 minutes at 200 V, 37.6 A input, at 30 kHz with 50% duty cycle. The modules could not perform for multiple minutes at 250 V with 47.7 A (23 A/die). The energy loss differential for a ~17% difference in threshold voltage ranged from 4.52% (~10 µJ) to -30.9% (~30 µJ). The energy loss differential for a ~0.5% difference in V_th ranged from -2.26% (~8 µJ) to 5.66% (~10 µJ). The loss differential was dependent on whether current unbalance due to on-state resistance compensated current unbalance due to threshold voltage. While device parametric tolerances are inherent, if the higher threshold voltage devices can be paired with devices that have higher on-state resistance, the overall loss differential may perform similarly to well-matched dies. Lastly, the most consistently performing unbalanced module with 17.7% difference in V_th had 119.9 µJ more energy loss and was 22.2°C hotter during continuous testing than the most consistently performing balanced module with 0.6% difference inV_th.
Master of Science
This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to different parts of the vehicle; for example, energy is stored in a battery as direct current (DC) power, but the motor requires alternating current (AC) power. Therefore, power electronics can alter the energy to be delivered as DC or AC. In order to carry more power, multiple devices can be used together just as 10 people can carry more weight than 1 person. However, because the devices are not perfect, there can be slight differences in the performance of one device to another. One device may have to carry more current than another device which could cause failure earlier than intended. In this research project, multiple power devices were placed into a package, or "module." In a control module, the devices were selected with similar properties to one another. In an experimental module, the devices were selected with properties very different from one another. It was determined that the when the devices were 17.7% difference, there was 119.9 µJ more energy loss and it was 22.2°C hotter than when the difference was only 0.6%. However, the severity of the difference was dependent on how multiple device characteristics interacted with one another. It may be possible to compensate some of the impact of device differences in one characteristic with opposing differences in another device characteristic.

The concern for climate changes and the increase in the electricity demand turned the attention towards the production, sorting and use of electric energy through zero emission (CO2) and highly efficient solutions (e.g. for electric vehicle), respectively. As a consequence, the need for high performance, reliable and low cost power transistors adopted for power applications is increasing as well. Gallium nitride seems to be the most promising candidate for the next generation of devices for power electronics, thanks to its excellent properties and comparable cost with respect to Si counterpart. The main and most adopted GaN-based device is the high electron mobility transistor (HEMT). In particular, in the case of switching power applications, HEMTs repeatedly are switched between high current on-state and high voltage off-state operation. For both operation modes a good reliability must be guaranteed. This thesis is focused on the reliability issues related to the off-state operation. The results have been obtained during a six months research period at imec (Belgium) on 200V p-GaN gate AlGaN/GaN HEMTS. Different devices have been investigated, differing for gate-to-drain distance, field plates lengths, AlGaN and GaN layers properties. Time-dependent dielectric breakdown and hard breakdown tests have been performed in combination with TCAD simulations. It has been demonstrated that the gate-to-drain distance (LGD) impacts the breakdown voltage and the kind of failure mechanism. If LGD ≤3um the breakdown occurs through the GaN channel layer due to short channel effects. In this case, by reducing the thickness of the GaN channel layer such behaviour can be attenuated, eventually leading to longer time-to-failure. If LGD≥ 4um the breakdown occurs between the 2DEG and the source field plates, where the properties of the AlGaN barrier layer (i.e. thickness and Al concentration) and the field plates configuration play the main role on the time-to-failure.

The superior characteristics of silicon carbide, compared with silicon, have suggested considering this material for the next generation of power semiconductor devices. Among the different power switches, the bipolar junction transistor (BJT) can provide a very low forward voltage drop, a high current capability and a fast switching speed. However, in order to compete on the market, it is crucial to a have high current gain and a breakdown voltage close to ideal. Moreover, the absence of conductivity modulation and long-term stability has to be solved. In this thesis, these topics are investigated comparing simulations and measurements. Initially, an efficient etched JTE has been simulated and fabricated. In agreement with the simulations, the fabricated diodes exhibit the highest BV of around 4.3 kV when a two-zone JTE is implemented. Furthermore, the simulations and measurements demonstrate a good agreement between the electric field distribution inside the device and the optical luminescence measured at breakdown. Additionally, an accurate model to simulate the forward characteristics of 4H-SiC BJTs is presented. In order to validate the model, the simulated current gains are compared with measurements at different temperatures and different base-emitter geometries. Moreover, the simulations and measurements of the on-resistance are compared at different base currents and different temperatures. This comparison, coupled with a detailed analysis of the carrier concentration inside the BJT, indicates that internal forward biasing of the base-collector junction limits the BJT to operate at high current density and low forward voltage drop simultaneously. In agreement with the measurements, a design with a highly-doped extrinsic base is proposed to alleviate this problem. In addition to the static characteristics, the comparison of measured and simulated switching waveforms demonstrates that the SiC BJT can provide fast switching speed when it acts as a unipolar device. This is crucial to have low power losses during transient. Finally, the long-term stability is investigated. It is observed that the electrical stress of the base-emitter diode produces current gain degradation; however, the degradation mechanisms are still unclear. In fact, the analysis of the measured Gummel plot suggests that the reduction of the carrier lifetime in the base-emitter region might be only one of the causes of this degradation. In addition, the current gain degradation due to ionizing radiation is investigated comparing the simulations and measurements. The simulations suggest that the creation of positive charge in the passivation layer can increase the base current; this increase is also observed in the electrical measurements.
QC 20120522

Interest in wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and diamond has increased due to their ability to deliver high power, high switching frequency and low loss electronic devices for power conversion applications. To meet these requirements, semiconductor material defects, introduced during growth and fabrication, must be minimized. Otherwise, theoretical limits of operation cannot be achieved. In this dissertation, the non-ideal current- voltage (IV) behavior of GaN-based Schottky diodes is discussed first. Here, a new model is developed to explain better the temperature dependent performance typically associated with a multi-Gaussian distribution of barrier heights at the metal-semiconductor interface [Section 3.1]. Application of this model gives researches a means of understanding not only the effective barrier distribution at the MS interface but also its voltage dependence. With this information, the consequence that material growth and device fabrication methods have on the electrical characteristics can be better understood. To show its applicability, the new model is applied to Ru/GaN Schottky diodes annealed at increasing temperature under normal laboratory air, revealing that the origin of excess reverse leakage current is attributed to the low-side inhomogeneous barrier distribution tail [Section 3.2]. Secondly, challenges encountered during MOCVD growth of low-doped GaN drift layers for high-voltage operation are discussed with focus given to ongoing research characterizing deep-level defect incorporation by deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) [Section 3.3 and 3.4]. It is shown that simply increasing TMGa so that high growth rates (>4 µm/hr) can be achieved will cause the free carrier concentration and the electron mobilities in grown drift layers to decrease. Upon examination of the deep-level defect concentrations, it is found that this is likely caused by an increase in 4 deep level defects states located at E C - 2.30, 2.70, 2.90 and 3.20 eV. Finally, samples where the ammonia molar flow rate is increased while ensuring growth rate is kept at 2 µm/hr, the concentrations of the deep levels located at 0.62, 2.60, and 2.82 eV below the conduction band can be effectively lowered. This accomplishment marks an exciting new means by which the intrinsic impurity concentration in MOCVD-grown GaN films can be reduced so that >20 kV capable devices could be achieved.
Doctor of Philosophy

Interest in wide bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and diamond has increased due to their ability to deliver high power, high switching frequency and low loss electronic devices for power conversion applications. To meet these requirements, semiconductor material defects, introduced during growth and fabrication, must be minimized. Otherwise, theoretical limits of operation cannot be achieved. In this dissertation, the non-ideal current- voltage (IV) behavior of GaN-based Schottky diodes is discussed first. Here, a new model is developed to explain better the temperature dependent performance typically associated with a multi-Gaussian distribution of barrier heights at the metal-semiconductor interface [Section 3.1]. Application of this model gives researches a means of understanding not only the effective barrier distribution at the MS interface but also its voltage dependence. With this information, the consequence that material growth and device fabrication methods have on the electrical characteristics can be better understood. To show its applicability, the new model is applied to Ru/GaN Schottky diodes annealed at increasing temperature under normal laboratory air, revealing that the origin of excess reverse leakage current is attributed to the low-side inhomogeneous barrier distribution tail [Section 3.2]. Secondly, challenges encountered during MOCVD growth of low-doped GaN drift layers for high-voltage operation are discussed with focus given to ongoing research characterizing deep-level defect incorporation by deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) [Section 3.3 and 3.4]. It is shown that simply increasing TMGa so that high growth rates (>4 µm/hr) can be achieved will cause the free carrier concentration and the electron mobilities in grown drift layers to decrease. Upon examination of the deep-level defect concentrations, it is found that this is likely caused by an increase in 4 deep level defects states located at E C - 2.30, 2.70, 2.90 and 3.20 eV. Finally, samples where the ammonia molar flow rate is increased while ensuring growth rate is kept at 2 µm/hr, the concentrations of the deep levels located at 0.62, 2.60, and 2.82 eV below the conduction band can be effectively lowered. This accomplishment marks an exciting new means by which the intrinsic impurity concentration in MOCVD-grown GaN films can be reduced so that >20 kV capable devices could be achieved.
Doctor of Philosophy

De nos jours, les énergies renouvelables remplacent les énergies fossiles. Pour assurer une l’interconnexion entre toutes ces installations électriques, l’électronique de puissance est nécessaire. Les principales spécifications de la prochaine génération de convertisseur de puissances sont un rendement et une densité de puissance élevés, fiabilité et faibles coûts. L’intégration PCB des composants actifs et/ou passifs est perçue comme une approche prometteuse, peu onéreuse et efficace. Les délais ainsi que les coûts de fabrication des convertisseurs de puissance peuvent considérablement réduits. L’intégration permet également d’améliorer les performances des convertisseurs. Dans ce but, un concept original d’inductance 3D pliable utilisant la technologie PCB est présenté. Il permet un coût faible pour une production en série, ainsi qu’une excellente reproductibilité. Un usinage partiel de la carte PCB est utilisé, permettant le pliage et la conception des enroulements de l’inductance. Différents prototypes sont développés par le biais d’une procédure d’optimisation. Des tests électriques et thermiques sont réalisés pour valider l’applicabilité du concept au sein de convertisseurs de puissance.Le développement d’une procédure d’optimisation appliqué aux convertisseurs hautement intégrés utilisant l’enterrement PCB est présenté. Tous les choix importants, facilitant l’intégration PCB, e.g. réduction des composants passifs, sont présentés. Cela inclut la sélection de la topologie adéquate avec la modulation associée. La procédure de design et les modèles analytiques sont introduits. Il en résulte un convertisseur comprenant quatre pont-complet entrelacés avec des bras fonctionnant à basse (50 Hz) et haute (180 kHz) fréquences. Cette configuration autorise une variation de courant importante dans les inductances, assurant ainsi la commutation des semi-conducteurs à zéro de tension (ZVS), et ceux sur une période complète du réseau. L’impact de la forte variation de courant sur le filtre CEM est compensé par l’entrelacement. Deux prototypes d’un convertisseur AC/DC bidirectionnel de 3.3 kW sont présentés, les résultats théorique et pratique sont analysés.Pour augmenter la densité de puissance du system, un filtre actif de type “Buck” est étudié. La procédure d’optimisation est adaptée à partir de la procédure implémentée pour le convertisseur AC/DC. L’approche utilisée, mène à un convertisseur opérant également en ZVS durant une période compète du réseau, et ce, à fréquence de commutation fixe. Les technologies sélectionnées, condensateur céramique et inductance compatible avec la technologie PCB sont favorable à l’intégration et sont implémenté sur le prototype
Nowadays, the green energy sources are replacing fossil energies. To assure proper interconnections between all these different electrical facilities, power electronics is mandatory. The main requirements of next generation converters are high efficiency, high power density, high reliability and low-cost. The Printed Circuit Board (PCB) integration of dies and/or passives is foreseen as a promising, low-cost and efficient approach. The manufacturing time and cost of power converters can be drastically reduced. Moreover, integration allows the converter performances to be improved. For this purpose, an original 3D folded power inductor concept using PCB technology is introduced. It is low cost for mass production and presents good reproducibility. A partial milling of the PCB is used to allow bending and building the inductor winding. Prototypes are designed through an optimisation procedure. Electrical and thermal tests are performed to validate the applicability in power converters. The development of an optimisation procedure for highly integrated converters, using PCB embedding, is presented. All important choices, facilitating the PCB integration, e.g. reduction of passive components, are presented. It includes the selection of the suitable converter topology with the associated modulation. The design procedure and implemented analytical models are introduced. It results in four interleaved full-bridges operating with low (50 Hz) and high (180 kHz) frequency legs. The configuration allows high current ripple in the input inductors inducing zero voltage switching (ZVS) for all the semiconductors, and for a complete grid period. The impact of high current ripple on the EMI filter is compensated by the interleaving. Two prototypes of a 3.3 kW bidirectional AC/DC converters are presented, theoretical and practical results are discussed. To further increase the power density of the overall system, a Buck power pulsating buffer is investigated. The optimisation procedure is derived from the procedure implemented for the AC/DC converter. The result favours an original approach, where the converter also operates with ZVS along the entire main period at a fixed switching frequency. The selected technologies for prototyping are integration friendly as ceramic capacitors and PCB based inductors are implemented in the final prototype

Pour contrôler le flux d'énergie électrique de la source à la charge, l'électronique de puissance constitue un des éléments phares dans l'acheminement de cette énergie. La gestion et la conversion de cette énergie électrique nécessitent des convertisseurs de puissance efficaces, basés sur des interrupteurs présentant des performances élevées en commutation et en conduction, à haute puissance et haute fréquence. Bien que les dispositifs à base de silicium dominent depuis longtemps l'électronique de puissance, les propriétés physiques de ce matériau limitent les performances des dispositifs en termes de température maximale d'opération, de tension de claquage, de résistance à l'état passant et de vitesse de commutation. La recherche des matériaux prometteurs présentant des performances supérieures à celles du silicium est donc nécessaire. Le nitrure de gallium (GaN) est l'un des matériaux qui permet, grâce à ses propriétés physiques, de répondre aux exigences de fabrication des convertisseurs de puissance. En outre, le transistor à haute mobilité électronique (HEMT) à hétérostructure AlGaN/GaN est un composant qui contribue à l'innovation des technologies de conversion de puissance. Cependant, de nombreux problèmes de fiabilité affectent les performances électriques de ces dispositifs et nécessitent un effort d'analyse et de compréhension. Les contributions du présent travail s'inscrivent précisément dans ce domaine. La caractérisation de la résistance à l'état passant de ce transistor, qui est un problème critique, est nécessaire pour comprendre la dynamique de certains phénomènes tels que le piégeage. Dans ce travail, on s'intéresse tout particulièrement à la caractérisation des effets du piégeage induit par des défauts qui peuvent exister dans les différentes couches de la structure. Nous proposons une nouvelle méthodologie générale de mesure permettant d'obtenir des résultats fiables et reproductibles et montrant l'importance de maîtriser les conditions initiales avant chaque mesure. Les phénomènes dynamiques sont caractérisés à l'aide des mesures du courant en fonction du temps, réalisées sur des structures TLM issues de différents lots technologiques, sous stimulations électrique et/ou optique. Deux méthodes de caractérisation de ces défauts sont ainsi proposées. Le but de la première est de stresser le dispositif par une tension négative appliquée sur le substrat pour stimuler les défauts présents entre ce dernier et le canal 2DEG, alors que la deuxième consiste à illuminer le dispositif sous test par une source lumineuse dont l'énergie de photon correspondante est choisie de façon à ce qu'elle n'affecte que les pièges présents dans les matériaux. L'effet de l'illumination sur les résistances de contact est ensuite étudié, montrant une contribution non négligeable de ces résistances dans la résistance totale et mettant ainsi en évidence, pour la première fois, que la dynamique de la résistance à l'état passant peut-être due non seulement à des phénomènes dans le canal 2DEG mais également à des phénomènes au niveau des contacts ohmiques[...]
To control the flow of electrical energy from source to load, power electronics is one of the key elements for the management of this energy. Managing and converting electrical energy requires efficient power converters, based on switches exhibiting high switching and conduction performance, at high power and high frequency. Although silicon-based devices have dominated power electronics for long time, the physical properties of this material limit the performance of these devices in terms of maximum operating temperature, breakdown voltage, dynamic On-state resistance and switching speed. The search for promising materials exhibiting superior performance compared to silicon is therefore contemplated. Gallium nitride (GaN) is one of the materials that, thanks to its physical properties, meet the manufacturing requirements of power converters. Furthermore, the AlGaN/GaN heterostructure high electronic mobility transistor (HEMT) is one a power device that contributes to the innovation in power conversion technologies. However, many reliability issues affect the electrical performance of these devices and require efforts of analysis and understanding. The contributions of this work fit precisely in this topic. The characterization of the dynamic On-state resistance of GaN HEMT transistors, which is a critical problem, is necessary to understand the dynamics of certain phenomena such as trapping. In this work, we focus on characterizing the effects of trapping induced by defects that may exist in the different layers of the structure. We propose a new general measurement methodology allowing reliable and reproducible results and showing the importance of mastering the initial conditions before each measurement. These dynamic phenomena are characterized using current measurements as a function of time, realized on TLM structures coming from different technological batches, under electrical and/or optical stimulations. Two characterization methods of these defects are proposed. The purpose of the first method is to stress the device by a negative voltage applied to the substrate to stimulate the defects located between the 2DEG channel and the substrate, while the second one consists in illuminating the device under test with a light source whose corresponding photon energy is chosen to affect only the traps present in the materials. The effect of the illumination on the contact resistances is then studied, showing a non-negligible contribution of these resistances in the total resistance and thus highlighting, for the first time, that the degradation of the dynamic on-state resistance may be due not only to phenomena in the 2DEG channel but also to phenomena at the ohmic contacts.[...]

Les composants de puissance grand gap présentent d'ores et déjà des caractéristiques statiques et dynamiques supérieures à leurs homologues en silicium. Mais ces composants d'un nouvel ordre s'accompagnent de différences susceptibles de modifier le fonctionnement de la cellule de commutation. Les travaux qui furent menés au cours de cette thèse se sont intéressés aux composants grand gap et à leur commande au sein d'un convertisseur de puissance synchrone robuste, haut rendement et haute densité de puissance. En particulier deux points critiques ont été identifiés et étudiés. Le premier est la grande sensibilité des composants grand gap aux composants parasites. Le second est l'absence de diode parasite interne entre le drain et la source de nombreux transistors grand gap. Pour répondre aux exigences de ces nouveaux composants et en tirer le meilleur profit, nous proposons des solutions innovantes, robustes, efficaces et directement intégrables aux circuits de commande. Des circuits de commande entièrement intégrés ont ainsi été conçus spécifiquement pour les composants grand gap. Ceux-ci permettent entre autres le contrôle précis des formes de commutation par l'adaptation de l'impédance de grille, et l'amélioration de l'efficacité énergétique et de la robustesse d'un convertisseur de puissance à base de composants grand sans diodes par une gestion dynamique et locale de temps morts très courts
Wide band gap devices already demonstrate static and dynamic performances better than silicon transistors. Compared to conventional silicon devices these new wide band gap transistors have some different characteristics that may affect power converter operations. The work presented in this PhD manuscript deals with a specific gate drive circuit for a robust, high power density and high efficiency wide band gap devices-based power converter. Two critical points have been especially studied. The first point is the higher sensitivity of wide band gap transistors to parasitic components. The second point is the lack of parasitic body diode between drain and source of HEMT GaN and JFET SiC. In order to drive these new power devices in the best way we propose innovative, robust and efficient solutions. Fully integrated gate drive circuits have been specifically developed for wide band gap devices. An adaptive output impedance gate driver provides an accurate control of wide band gap device switching waveforms directly on its gate side. Another gate drive circuit improves efficiency and reliability of diode-less wide band gap devices-based power converters thanks to an auto-adaptive and local dead-time management

Dans ce projet de thèse, qui s'appuie sur l'optimisation d'un réacteur de croissance du diamant et la construction d'un prototype, nous avons démontré l'épitaxie par étapes de couches de diamant, orientées (100), lourdement dopées au bore sur des couches de dopage plus faible dans le même processus, sans arrêter le plasma. Plus original, nous avons démontré la situation inverse. Nous présentons aussi des croissances assez lentes pour l'épitaxie de films d'épaisseur nanométriques avec de grands sauts de dopage, appelé delta-dopage. L'accent a été porté sur le gain en raideur des interfaces. Nous démontrons la présence d'interfaces fortement abruptes, issues de gravures in-situ optimisées, par une analyse conjointe en spectrométrie de masse à ionisation secondaire et en microscopie électronique en transmission à balayage en champ sombre annulaire aux grands angles. Des super-réseaux de dopages abrupts montrent des pics satellites de diffraction X typiques de la super-période.

Today, the investigation of fuel economy improvements in internal combustion engines (ICEs) has become the most significant research interest among the automobile manufacturers and researchers. The scarcity of natural resources, progressively increasing oil prices, carbon dioxide taxation and stringent emission regulations all make fuel economy research relevant and compelling. The enhancement of engine performance solely using incylinder techniques is proving increasingly difficult and as a consequence the concept of exhaust energy recovery has emerged as an area of considerable interest. Three main energy recovery systems have been identified that are at various stages of investigation. Vapour power bottoming cycles and turbo-compounding devices have already been applied in commercially available marine engines and automobiles. Although the fuel economy benefits are substantial, system design implications have limited their adaptation due to the additional components and the complexity of the resulting system. In this context, thermo-electric (TE) generation systems, though still in their infancy for vehicle applications have been identified as attractive, promising and solid state candidates of low complexity. The performance of these devices is limited to the relative infancy of materials investigations and module architectures. There is great potential to be explored. The initial modelling work reported in this study shows that with current materials and construction technology, thermo-electric devices could be produced to displace the alternator of the light duty vehicles, providing the fuel economy benefits of 3.9%-4.7% for passenger cars and 7.4% for passenger buses. More efficient thermo-electric materials could increase the fuel economy significantly resulting in a substantially improved business case. The dynamic behaviour of the thermo-electric generator (TEG) applied in both, main exhaust gas stream and exhaust gas recirculation (EGR) path of light duty and heavy duty engines were studied through a series of experimental and modelling programs. The analyses of the thermo-electric generation systems have highlighted the need for advanced heat exchanger design as well as the improved materials to enhance the performance of these systems. These research requirements led to the need for a systems evaluation technique typified by hardware-in-the-loop (HIL) testing method to evaluate heat exchange and materials options. HIL methods have been used during this study to estimate both the output power and the exhaust back pressure created by the device. The work has established the feasibility of a new approach to heat exchange devices for thermo-electric systems. Based on design projections and the predicted performance of new materials, the potential to match the performance of established heat recovery methods has been demonstrated.

This thesis describes the analysis, design and implementation of a high performance DSP-based servo drive for a limited-angle torque motor used in thermal imaging applications. A limited-angle torque motor is an electromagnetic actuator based on the Laws' relay principle, and in the present application the rotation required was from - 10° to + 10° in 16 ms, with a flyback period of 4 ms. To ensure good quality picture reproduction, an exceptionally high linearity of ±0.02 ° was necessary throughout the forward sweep. In addition, the drive voltage to the exciting winding of the motor should be less than the +35 V ceiling of the drive amplifier. A research survey shows that little literature was available, probably due to the commercial sensitivity of many of the applications for torque motors. A detailed mathematical model of the motor drive, including high-order linear dynamics and the significant nonlinear characteristics, was developed to provide an insight into the overall system behaviour. The proposed control scheme uses a multicompensator, multi-loop linear controller, to reshape substantially the motor response characteristic, with a non-linear adaptive gain-scheduled controller to compensate effectively for the nonlinear variations of the motor parameters. The scheme demonstrates that a demanding nonlinear control system may be conveniently analysed and synthesised using frequency-domain methods, and that the design techniques may be reliably applied to similar electro-mechanical systems required to track a repetitive waveform. A prototype drive system was designed, constructed and tested during the course of the research. The drive system comprises a DSP-based digital controller, a linear power amplifier and the feedback signal conditioning circuit necessary for the closed-loop control. A switch-mode amplifier was also built, evaluated and compared with the linear amplifier. It was shown that the overall performance of the linear amplifier was superior to that of the switch-mode amplifier for the present application. The control software was developed using the structured programming method, with the continuous controller converted to digital form using the bilinear transform. The 6- operator was used rather than the z-operator, since it is more advantageous for high speed sampling systems. The gain-scheduled control was implemented by developing a schedule table, which is controlled by the DSP program to update continuously the controller parameters in synchronism with the periodic scanning of the motor. The experimental results show excellent agreement with the simulated results, with linearity of ±0.05 ° achieved throughout the forward sweep. Although this did not quite meet the very demanding specifications due to the limitations of the experimental drive system, it clearly demonstrates the effectiveness of the proposed control scheme. The discrepancies between simulated and experimental results are analyzed and discussed, the control design method is reviewed, and detailed suggestions are presented for further work which may improve the drive performance.

Dihydro-1,2,4,5-tetrazine-3,6-dicarboxylate was introduced into the chemically stable UiO-66 structure by a postsynthetic linker exchange reaction to create an optical sensor material for the detection of oxidative agents such as nitrous gases. The incorporated tetrazine unit can be reversibly oxidized and reduced, which is accompanied by a drastic colour change from yellow to pink and vice versa. The high stability of the framework during redox reaction was proven by powder X-ray diffraction and nitrogen physisorption measurements.

L’utilisation des semi-conducteurs à large bande interdite (wide bandgap ou WBG) tels que le carbure de silicium SiC, le nitrure de gallium GaN, le diamant, etc… s’est répandue dans le domaine de l’électronique de puissance ces dernières décennies. Leurs caractéristiques électroniques et mécaniques font des WBGs des solutions alternatives pour remplacer le traditionnel silicium. Cependant, des études supplémentaires sont indispensables pour améliorer la tenue en tension, les pertes statiques et dynamiques et les performances en fonctionnement à haute température des composants WBGs. Dans ce cadre, deux bancs expérimentaux OBIC (Optical Beam Induced Current) spécifiques « en cours de développement » sont mis en place pendant cette thèse. L’OBIC consiste à éclairer avec un faisceau laser de longueur d’onde appropriée une jonction polarisée en inverse, des porteurs de charge sont alors créés par absorption photonique. On peut alors mesurer un courant induit par faisceau optique (OBIC) lorsque les porteurs sont générés dans la zone de charge d’espace. Après une première phase de préparation et d’adaptation de l’environnement expérimental, des essais ont mené à la démonstration du principe de génération multi-photonique en éclairant une jonction SiC avec un faisceau vert (532 nm). L’analyse des différentes mesures OBIC nous a permis de construire une image du champ électrique à la surface de la diode : une analyse non destructive pour étudier l’efficacité des protections périphériques des jonctions et pour détecter les défauts dans la structure cristalline. Egalement, la durée de vie des porteurs minoritaires a été déduite par l’analyse de la décroissance du courant OBIC au bord de la jonction. Les coefficients d’ionisation sont également déterminés par la méthode OBIC, ces coefficients sont des paramètres clés pour la prévision de la tension de claquage des composants. Nous avons réalisé des mesures OBIC dans le GaN, et nous avons observé un effet d’absorption bi-photonique dans le diamant avec un faisceau UV (349 nm)
In the last few decades, the use of wide bandgap (WBG) semiconductors (silicon carbide SiC, gallium nitride GaN, diamond, etc…) has become popular in the domain of power electronics. Their electronic and mechanical characteristics made of the WBGs a good alternative to the traditional silicon. However, additional studies are mandatory to improve the breakdown voltage, static and dynamic losses, and the performance at high temperature of the WBG devices. In this context, two specific experimental benches OBIC (Optical Beam Induced Current) -under development- are set up during this thesis. OBIC method consists to generate free charge carriers in a reverse biased junction by illuminating the device with an appropriate wavelength. An OBIC signal is measured if the charge carriers are generated in the space charge region. After a first phase of preparation and adaptation of the experimental environment, OBIC measurements led to demonstrate the multi-photonic generation by illuminating a SiC junction with a green laser (532 nm). OBIC measurements allowed giving an image of the electric field at the surface of the diode: OBIC presents a non-destructive analysis to study the efficiency of the peripheral protection and to detect the defects in the semi-conductor. Minority carrier lifetime was also deduced by studying the OBIC decrease at the edge of the space charge region. Ionization rates were extracted using OBIC method; these coefficients are key parameters to predict the breakdown voltage of the devices. OBIC measurements were also realized on the GaN, and two-photon generation was highlighted by measuring an OBIC current in the diamond when illuminating it with a UV laser beam (349 nm)

Об’єкт дослідження – зрівноважувальний пристрій відцентрового насоса – гідроп’ята. Предмет дослідження – гідроп’ята. Мета дослідження – дослідити вплив опору обвідної труби на величину втрат енергії на гідроп’яті та на жорсткість її статичної характеристики. Методи дослідження – задача розв’язувалась в межах одновимірної моделі течії рідини в рухомій системі відліку; застосовувались елементи гідромеханіки, такі як: відносний спокій рідини, сила тиску на плоску стінку та інші; використовувались отримані залежності для визначення втрат потужності в циліндричному і торцевому дроселях. Розроблена методика розрахунку гідроп’яти на базі замкнутої системи рівнянь по геометричним параметрам за умови мінімальних втрат потужності при врахуванні втрат в обвідній трубі. Виконані дослідження запропонованої методики розрахунку гідроп’яти для прийнятого значення жорсткості статичної характеристики. Результати апробації методики розрахунку гідроп’яти проведені на базі живильного насосу ПЕ 600 - 300. Отримано, що втрати потужності в обвідній трубі, для прийнятої жорсткості статичної характеристики, майже не впливають на величину і розташування оптимуму з втрат потужності на гідроп’яті. Проте збільшення коефіцієнта опору обвідної труби призводить до зменшення довжини циліндричного дроселя гідроп’яти.

碩士
國立中央大學
電機工程學系
105
Gallium Nitride (GaN) power transistors exist better material properties than Si-based transistors such as higher electron mobility, higher breakdown voltage, higher current density, lower on-state resistance, lower gate charge and smaller output capacitance. It is particularly suitable to function as high speed switches for power electronic circuit applications. The thesis aims to design a circuit module to measure three electrical parameters of depletion-mode GaN power transistors in order to provide information for power electronic circuit design. Three major parameters include switching time, gate charge, and DC-IV curve. A detailed description of the designed circuits is given and measurement results are compared to the estimation model. The measurement error is about 32% because of design issues of the circuit module.

博士
國立交通大學
機械工程系所
106
Work on wide band gap materials and devices has been going on for many years. One of the important wide band gap materials showing great promise for the future for both switching and power applications is Gallium Nitride (GaN). Heteroepitaxial GaN devices on Si is restricted to lateral device structures. The most common lateral device structure is the HEMT (High Electron Mobility Transistor). Wide band gap and high critical field give GaN an advantage when high power is a key desirable device feature. However, the relatively poor thermal conductivity of GaN makes heat management for GaN devices a challenge for system designers to contend with. This study presents the packaging development of high power AlGaN/GaN HEMTs on Si substrate. By foremost carrying out electro-thermal simulation with Silvaco TCAD and related thermal measurements with infrared thermography and Raman spectroscopy for basic 5 mm GaN HEMTs, the location of hot spot in operating device can be obtained. Based on the outcome, further packaged GaN HEMT is analyzed. The packaging structure is designed on the device periphery surface for enhancing Si substrate thermal dissipation. The effects of structure design and fabrication processes on the device performance were studied. In addition, this study investigates the thermal performance of packaged normally-on multi-finger AlGaN/GaN HEMTs that are cascaded with a low-voltage MOSFET and a SiC Schottky barrier diode (SBD). The analytical results are confirmed by comparing them with the infrared thermographic measurements and numerical results obtained from simulation using Ansys Icepak. To increase the output power, the GaN HEMTs are connected in parallel and the related researches are also displayed. Finally, the packaged GaN devices are applied in power conversion systems.

Dottorato in Tecnologie dell’informazione e della comunicazione, Ciclo XXXI
The wide spectrum of power electronics applications, including their role in renewable energy conversion and energy saving, require the innovation from conventional Silicon (Si) technology into new materials and architectures that allow the fabrication of increasingly lightweight, compact, efficient and reliable devices. However, the trade-off between long lifetime, high performance and low cost in the emerging technologies represents a huge limitation that has gained the attention of different research groups in the last years. Gallium Nitride (GaN) is a wide-bandgap semiconductor (WBGS) that constitutes an excellent candidate for high-power and high-frequency applications due to its remarkable features such as high operating temperature, high dielectric strength, high current density, high switching speed, and low on-resistance. Compared with its Silicon counterpart, GaN is superior in terms of high breakdown field ( 3 MV/cm), exceptional carrier mobility, and power dissipation. By taking into account other WBG materials such as SiC, GaN grown on Si substrates promises similar performance but at a much lower cost in the low to mid power and high-frequency range. Since GaN allows size and weight device reduction due to a better relationship between on-resistance and breakdown voltage, it is suitable for a variety of applications such as RF power amplifiers, power switching systems, sensors, detectors, etc. Especially, in the field of energy efficiency, GaN technology appears as a future successor of Si in power conversion circuits. However, some drawbacks related to technology cost, integration, and long-term reliability have to be overcome for its wide adoption in the power applications market. One of the worst inconveniences of AlGaN/GaN High Electron Mobility Transistors (HEMTs) is the normally-ON operation. Since a two-dimensional electron gas (2DEG) channel is formed at the AlGaN/GaN interface due to inherent material properties, a negative bias has to be applied at the gate to switch the device off. Among the proposed solutions to fabricate normally-OFF devices, the metaloxide/ insulator-semiconductor (MOS/MIS) structure with different insulators has shown remarkable improvements in gate leakage reduction and drain current increase. Also in AlGaN/GaN Schottky Barrier Diodes (SBDs), the introduction of a MOS structure to create a gated edge termination (GET) at the anode area has resulted in significant improvements in reverse diode leakage and forward diode voltage. Nevertheless, the improvement in the device performance by the introduction of a dielectric could seriously affect the device long-term reliability since additional degradation in this layer and at its interfaces with AlGaN or GaN occurs. In the case of conversion systems, power devices are continuously switched from an OFF-state condition at high drain bias to an ON-state condition at large drain current. Therefore, the reliability of GaN-based devices has to be proven for the complete ON/OFF operation. This dissertation focuses on providing a more comprehensive analysis of two main reliability issues related to the dielectric insertion under the gate/anode stacks by analyzing the use of different dielectric materials and device architectures. The first issue is the positive bias temperature instability (PBTI), which is related to the degradation of electrical parameters when high gate voltages and temperatures are applied and is especially observed during the ON-state operation of the transistor. By using MOS-HEMT structures with different gate dielectrics (SiO2, Al2O3, and AlN/Al2O3), the impact of the stress voltage, recovery voltage and temperature on the device reliability is analyzed including the role of oxide traps and the interface states to provide physical insights into this mechanism. The second phenomenon discussed in this thesis is the time-dependent dielectric breakdown (TDDB) observed on GET-SBDs during its OFF-operation. The percolation model and Weibull distribution are used to understand this degradation mechanism. As a result, it has been demonstrated that the time to breakdown tBD is influenced by the GET structure (single vs. double), the passivation thickness, the preclean process at the anode region before the GET dielectric deposition and the capping layer. Finally, by using 2D TCAD simulations, the long-term reliability improvement has been related to the reduction of the electric fie
University of Calabria