Artículos de revistas: "FD-SOI (transistors)"

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Angelov, George V., Dimitar N. Nikolov y Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices". Journal of Electrical and Computer Engineering 2019 (3 de noviembre de 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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2

Lagaev, Dmitriy A., Aleksey S. Klyuchnikov y Nikolay A. Shelepin. "Prospects for applying FD-SOI technology to space applications". Journal of Physics: Conference Series 2388, n.º 1 (1 de diciembre de 2022): 012135. http://dx.doi.org/10.1088/1742-6596/2388/1/012135.

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Abstract In this work, using numerical simulation, the reasons for the occurrence of increased values of leakage currents in NMOS fully depleted SOI (FD-SOI) transistors during interaction with ionizing radiation. It has shown that the main reason for the formation of leakage currents is the charge accumulated in the latent oxide upon interaction with ionizing radiation. The effectiveness of applying a bias on the substrate and the formation of a well under the buried oxide (BOX) to reduce the leakage currents is investigated. Based on the obtained results, it was concluded that it is promising to use transistors made using FD-SOI technology for space applications.

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3

Taher Abuelma’atti, Muhammad. "Harmonic and intermodulation distortion in SOI FD transistors". Solid-State Electronics 47, n.º 5 (mayo de 2003): 797–800. http://dx.doi.org/10.1016/s0038-1101(02)00453-7.

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4

Assalti, Rafael, Denis Flandre y Michelly De Souza. "Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs". Journal of Integrated Circuits and Systems 13, n.º 2 (5 de octubre de 2018): 1–7. http://dx.doi.org/10.29292/jics.v13i2.15.

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This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The influence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measurements. The transconductance, output conductance, Early voltage and intrinsic voltage gain have been used as figure of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been obtained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.

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5

Schmidt, Alexander, Holger Kappert y Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing". Journal of Microelectronics and Electronic Packaging 10, n.º 4 (1 de octubre de 2013): 171–82. http://dx.doi.org/10.4071/imaps.389.

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Analog circuits realized in a PD-SOI (partially-depleted silicon-on-insulator) CMOS technology for a wide temperature range up to 400°C are significantly affected by the transistor characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, for example, intrinsic gain and bandwidth, tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that RBB (reverse body biasing) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300°C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS technology by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400°C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, current mirrors, a two-stage operational amplifier, and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby, the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. As the method has also been applied to essential analog circuits, it has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400°C.

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6

Mota Barbosa da Silva, Lucas, Bruna Cardoso Paz y Michelly De Souza. "Analysis of Mobility in Graded-Channel SOI Transistors Aiming at Circuit Simulation". Journal of Integrated Circuits and Systems 15, n.º 2 (31 de julio de 2020): 1–5. http://dx.doi.org/10.29292/jics.v15i2.188.

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This work presents an analysis of the behavior of the effective mobility of graded-channel FD SOI transistors using an Y-Function-based technique. Low field mobility, linear and quadratic attenuation factors were extracted from two-dimensional numerical simulations. The influence of the length of both channel regions over these parameters was analyzed. The parameters extracted from experimental data were used in a SPICE simulator, showing that it is possible to simulated GC SOI MOSFET using a regular SOI MOSFET model, by adjusting its parameters.

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7

Schmidt, Alexander, Holger Kappert y Rainer Kokozinski. "Enhanced High Temperature Performance of PD-SOI MOSFETs in Analog Circuits Using Reverse Body Biasing". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (1 de enero de 2013): 000122–33. http://dx.doi.org/10.4071/hiten-ta14.

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Analog circuit realized in a PD-SOI (Partially-Depleted Silicon-on-Insulator) CMOS process for a wide temperature range up to 400 °C are significantly affected by the MOSFET device characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, e.g. intrinsic gain and bandwidth tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that reverse body biasing (RBB) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300 °C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS process by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400 °C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, basic current mirrors, a two-stage operational amplifier and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. The method has also been applied to basic analog circuits. It has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400 °C.

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8

Cerdeira, A., M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde y F. J. Garcı́a Sánchez. "New method for determination of harmonic distortion in SOI FD transistors". Solid-State Electronics 46, n.º 1 (enero de 2002): 103–8. http://dx.doi.org/10.1016/s0038-1101(01)00258-1.

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9

Gaillardin, Marc, Philippe Paillet, Veronique Ferlet-Cavrois, Jacques Baggio, Dale McMorrow, Olivier Faynot, Carine Jahan, Lucie Tosti y Sorin Cristoloveanu. "Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors". IEEE Transactions on Nuclear Science 54, n.º 6 (diciembre de 2007): 2355–62. http://dx.doi.org/10.1109/tns.2007.910860.

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10

Lee, Noriyuki, Ryuta Tsuchiya, Yusuke Kanno, Toshiyuki Mine, Yoshitaka Sasago, Go Shinkai, Raisei Mizokuchi et al. "16 x 8 quantum dot array operation at cryogenic temperatures". Japanese Journal of Applied Physics 61, SC (16 de febrero de 2022): SC1040. http://dx.doi.org/10.35848/1347-4065/ac4c07.

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Abstract We developed a 16 x 8 quantum dot array and CMOS circuit hybrid chip (Q-CMOS). By optimizing the transistor design of Q-CMOS formed by fully depleted (FD)-SOI, it is possible to selectively control each of 16 x 8 quantum dots, and obtained characteristics of quantum dot variation for the first time. Due to the mesoscopic effect, the variation in the characteristics of the quantum dots is larger than the threshold voltage variation of the transistors. Thus, we have obtained an important finding that it is necessary to suppress the variability in order to realize a large-scale quantum computer. We have also confirmed that the characteristics of the quantum dots change depending on the applied gate voltages.

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11

Vasileska, D., K. Raleva, A. Hossain y S. M. Goodnick. "Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors". Journal of Computational Electronics 11, n.º 3 (18 de mayo de 2012): 238–48. http://dx.doi.org/10.1007/s10825-012-0404-0.

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12

Hartmann, Jean-Michel, Francois Aussenac, Olivier Glorieux, David Cooper, Sebastien Kerdilès, Zdenek Chalupa, Francois Boulard et al. "Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs". ECS Transactions 114, n.º 2 (27 de septiembre de 2024): 185–205. http://dx.doi.org/10.1149/11402.0185ecst.

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We have evaluated the feasability of selectively growing, with a chlorinated chemistry, 20 to 30 nm thick SiGe:B Raised Sources and Drains with Ge concentration gradients (from 50% down to 20%-30%, typically) on each side of FD-SOI transistors. The motivation was twofold: (i) inject meaningful amounts of compressive strain in the channel of p-type MOS devices thanks to high Ge concentrations in layers sitting in the same plane than Si or SiGe channels and (ii) benefit from lower Ge concentration SiGe layers on top that are easier to germano-silicide. Growing a thin Si(:B) cap on SiGe:B otherwise yields more uniform and stable contacts. We have thus studied the Si capping of SiGe 20% or 30% layers. As growth has to be conducted, for Si, at temperatures significantly higher than that of SiGe (750°C, to be compared with 700°C for SiGe 20% and 650°C for SiGe 30%, typically), we have quantified the impact of using temperature ramping-ups with SiH2Cl2 + HCl flowing into the growing chamber. The purpose of such active ramps was to prevent elastic strain relaxation, e.g. the formation of SiGe surface undulations that would happen with temperature ramps under H2 only.

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13

Bhoir, Mandar S. y Nihar R. Mohapatra. "Effects of Scaling on Analog FoMs of UTBB FD-SOI MOS Transistors: A Detailed Analysis". IEEE Transactions on Electron Devices 67, n.º 8 (agosto de 2020): 3035–41. http://dx.doi.org/10.1109/ted.2020.3002878.

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14

Nocera, Claudio, Giuseppe Papotto y Giuseppe Palmisano. "Two-Path 77-GHz PA in 28-nm FD-SOI CMOS for Automotive Radar Applications". Electronics 11, n.º 8 (18 de abril de 2022): 1289. http://dx.doi.org/10.3390/electronics11081289.

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This paper presents a 77 GHz two path power amplifier (PA) for automotive radar applications. It was fabricated in 28-nm fully depleted silicon-on-insulator CMOS technology, which provides transistors with a transition frequency of about 270 GHz and a general-purpose low cost back-end-of-line. The proposed PA consists of a 50 Ω input buffer followed by two power units, which are made up of a current-reuse common source driver for improved efficiency and a stacked cascode power stage for enhanced output power. A peak detector was also embedded into the PA for output power monitoring. The designed PA achieved a saturated output power as high as 17.4 dBm at 77 GHz with an excellent power added efficiency of 19%, while drawing 150 mA from a 2 V power supply. The core die size was 500 μm × 300 μm.

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15

Barboni, Leonardo. "Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors". Journal of Low Power Electronics and Applications 10, n.º 2 (15 de mayo de 2020): 17. http://dx.doi.org/10.3390/jlpea10020017.

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The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramifications on the field of process modeling, simulation and circuit design.

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16

Al Mamun, Fahad, Sarma Vrudhula, Dragica Vasileska, Hugh Barnaby y Ivan Sanchez Esqueda. "Evidence of Transport Degradation in 22 nm FD-SOI Charge Trapping Transistors for Neural Network Applications". Solid-State Electronics 209 (noviembre de 2023): 108783. http://dx.doi.org/10.1016/j.sse.2023.108783.

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17

Favre, Luc, Mohammed Bouabdellaoui, Elie Assaf, Imene Guelil, Antoine Ronda y Isabelle Berbezier. "(Invited) SiGe/SOI System: Mechanisms of Condensation and Strain Relaxation". ECS Meeting Abstracts MA2022-01, n.º 20 (7 de julio de 2022): 1088. http://dx.doi.org/10.1149/ma2022-01201088mtgabs.

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Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies. In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

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18

Le, Minh-Son, Thi-Nhan Pham, Thanh-Dat Nguyen y Ik-Joon Chang. "A Variation-Aware Binary Neural Network Framework for Process Resilient In-Memory Computations". Electronics 13, n.º 19 (28 de septiembre de 2024): 3847. http://dx.doi.org/10.3390/electronics13193847.

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Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of 128×128, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%.

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19

Bertrand, Isabelle, Philippe Flatresse, Guillaume Besnard, Jean-Marc Bethoux, Zdenek Chalupa, Christophe Plantier, Martin Rack, Massinissa Nabet, Jean-Pierre Raskin y Frederic Allibert. "(G02 Best Paper Award Winner) Development Of High Resistivity FD-SOI Substrates for mmWave Applications". ECS Meeting Abstracts MA2022-01, n.º 29 (7 de julio de 2022): 1273. http://dx.doi.org/10.1149/ma2022-01291273mtgabs.

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The mmWave era opens up the door to revolutionary applications in the fields of communication, radar, imager, security, etc. FD-SOI CMOS technology is entering the mmW realm providing undeniable benefits in terms of data-rates, bandwidth, latency and power consumption improvements. The high resistivity substrate option is seen as a major booster to reach ultimate mmW performances. The engineering challenges related to this new wafer generation are addressed in this paper. In the different options for highly resistive silicon, low and high interstitial oxygen (Oi) materials are the most common ones, typically used to reach resistivity performance on SOI handles. Those materials are less compatible with FD-SOI technology, as they can be very sensitive to slip-line issues or wafer deformation, in specific SOI processing and customer’s line, possibly leading to overlay error. In addition, we can encounter inspectability and co-integration issues due to Crystal Originated Particules (COPs) presence for high Oi substrates. For the targeted technologies with FD-SOI, equal or below 28 nm, the handle properties will be key, as deformation and inspectability considerations are even more critical. One of the main challenges was to develop specific materials and processes to get both good resistivity and stability towards fabrication processes (SOI line and customer processing), and good mechanical behavior towards slip-line and potential deformation leading to error, together with low COPs handle material. In this paper, we will show how substrates were engineered specifically, to reach the appropriate resistivity targets around 1000 Ω.cm, and to be stable in depth with different additional anneals, in order to control compatibility with customer processes. In addition, we managed to achieve good performances in terms of mechanical behavior, such as slip-line generation during fabrication processes. We also had no overlay issues usually linked with slip-lines or excessive Bulk Micro Defects (BMD) presence in depth, generating dislocations and plastic deformation. We will review the material and process steps requirements to reach the best performances. The initial material requirements will be the oxygen content, together with the resistivity. The process requirements will be the final oxygen precipitation status, affected by specific thermal treatments and presence of sites for BMD nucleation and growth. A specific precipitation range will lead to good robustness towards both slip-lines sensitivity and overlay risks, by creating enough BMDs but not in excess. Besides, this specific precipitation state also helps to decrease the amount of residual interstitial oxygen left inside the High Resistivity substrate, and then decreases the oxygen thermal donor generation during back-end treatments in the 375-425°C range, improving resistivity stability. We will present all the characterizations performed on final SOI wafers, and after additional treatments, to highlight both handle substrate resistivity stability and mechanical robustness. Specific measurements were carried out to ensure that going from standard to high resistivity substrates did not adversely impact the behavior of logic devices. Test structures were implemented with 28 nm design rules on FD-SOI substrates with either 10 Ω.cm or 5 kΩ.cm handle resistivity. Compared figures of merit included transistors’ VTH and minimum gate length devices Ion/Ioff tradeoff as well as several devices built in the bulk of the wafer such as bipolar devices, diodes and capacitors. Obtained results will be shown to be within the natural process dispersion. Those substrates being destined to RF and mmWave applications, their performance was measured in terms of linearity and attenuation using coplanar waveguides built directly on top of the 20 nm buried oxide. Second harmonics measurements up to 28 GHz of fundamental frequency will be shown. The small signal measurements results will be compared to simulations including a thicker dielectric mimicking the very thick back-end of line available in advanced nodes. In conclusion, we will summarize how specific material for eSoC.1-HR handle was developed, showing performances in agreement with expectations on resistivity stability and mechanical robustness. Those substrates are leading to improved RF parameters compared to standard FD-SOI substrates, without degrading logic devices parameters.

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Gao, Shaochen, Duc-Tung Vu, Thibauld Cazimajou, Patrick Pittet, Martine Le Berre, Mohammadreza Dolatpoor Lakeh, Fabien Mandorlo et al. "Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology". Photonics 11, n.º 6 (1 de junio de 2024): 526. http://dx.doi.org/10.3390/photonics11060526.

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The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).

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21

Zheng, Qiwen, Jiangwei Cui, Liewei Xu, Bingxu Ning, Kai Zhao, Mingjie Shen, Xuefeng Yu et al. "Total Ionizing Dose Responses of Forward Body Bias Ultra-Thin Body and Buried Oxide FD-SOI Transistors". IEEE Transactions on Nuclear Science 66, n.º 4 (abril de 2019): 702–9. http://dx.doi.org/10.1109/tns.2019.2901755.

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22

de Souza, Michelly, Denis Flandre, Rodrigo Trevisoli Doria, Renan Trevisoli y Marcelo Antonio Pavanello. "On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration". Solid-State Electronics 117 (marzo de 2016): 152–60. http://dx.doi.org/10.1016/j.sse.2015.11.018.

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23

Zhang, Guohe, Junhua Lai, Yali Su, Binhong Li, Bo Li, Jianhui Bu y Cheng-Fu Yang. "Study on the Thermal Conductivity Characteristics for Ultra-Thin Body FD SOI MOSFETs Based on Phonon Scattering Mechanisms". Materials 12, n.º 16 (15 de agosto de 2019): 2601. http://dx.doi.org/10.3390/ma12162601.

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The silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) suffer intensive self-heating effects due to the reduced thermal conductivity of the silicon layer while the feature sizes of devices scale down to the nanometer regime. In this work, analytical models of thermal conductivity considering the self-heating effect (SHE) in ultra-thin body fully depleted (UTB-FD) SOI MOSFETs are presented to investigate the influences of impurity, free and bound electrons, and boundary reflection effects on heat diffusion mechanisms. The thermal conductivities of thin silicon films with different parameters, including temperature, depth, thickness and doping concentration, are discussed in detail. The results show that the thermal dissipation associated with the impurity, the free and bound electrons, and especially the boundary reflection effects varying with position due to phonon scattering, greatly suppressed the heat loss ability of the nanoscale ultra-thin silicon film. The predictive power of the thermal conductivity model is enhanced for devices with sub-10-nm thickness and a heavily doped silicon layer while considering the boundary scattering contribution. The absence of the impurity, the electron or the boundary scattering leads to the unreliability in the model prediction with a small coefficient of determination.

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24

Watkins, A. C., S. T. Vibbert, J. V. D'Amico, J. S. Kauppila, T. D. Haeffner, D. R. Ball, E. X. Zhang, K. M. Warren, M. L. Alles y L. W. Massengill. "Mitigating Total-Ionizing-Dose-Induced Threshold-Voltage Shifts Using Back-Gate Biasing in 22-nm FD-SOI Transistors". IEEE Transactions on Nuclear Science 69, n.º 3 (marzo de 2022): 374–80. http://dx.doi.org/10.1109/tns.2022.3146318.

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25

Yamaoka, M., R. Tsuchiya y T. Kawahara. "SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors". IEEE Journal of Solid-State Circuits 41, n.º 11 (noviembre de 2006): 2366–72. http://dx.doi.org/10.1109/jssc.2006.882891.

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26

Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini y Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors". Electronics 10, n.º 17 (31 de agosto de 2021): 2114. http://dx.doi.org/10.3390/electronics10172114.

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This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

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27

Lespiaux, Justine, Joël Kanyandekwe, Tanguy Marion, Lazhar Saidi, Valérie Lapras, Alice Bond, Fabien Bringuier et al. "Selective Epitaxial Growth of SiGe(:B) for Advanced p-Type Fd-SOI". ECS Meeting Abstracts MA2024-02, n.º 32 (22 de noviembre de 2024): 2356. https://doi.org/10.1149/ma2024-02322356mtgabs.

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Epitaxy is of major importance during the manufacturing of p-type metal oxide semiconductor field effect transistors (p-MOSFETs) for next generation fully depleted-silicon on insulator (FD-SOI) integrated circuits. A compressive-strained SiGe channel has indeed to be present in p-type regions for threshold voltage tuning and hole mobility boosting. In-situ boron-doped SiGe raised sources/drains (RSD) have otherwise to be used to reduce access resistance and, ideally, inject uniaxial compressive strain in the channel. Selective epitaxial growth (SEG) is needed for both types of layers,with deposition occurring solely in Si or SiGe areas surrounded by dielectrics. Reduced pressure-chemical vapor deposition (RP-CVD) processes in the 600–800 °C range have been under study for years. We are however still facing technical constraints during their use into complex process flows. Hence, optimizations are required to achieve suitable films in terms of Ge and B compositions (with sometimes dopant incorporation above their solubility limit), morphology (significantly thicker layers in small patterns) and structure (faceting and anisotropic effects). We focus here on various SEG processes used during the manufacturing of advanced p-MOSFET devices, as depicted in Fig. 1: (i) 20 nm thick in-situ boron doped Si0.7Ge0.3 layers grown at 650 °C, 20 Torr then capped with 5 nm of Si:B (at 730 °C, 20 Torr) for RSDs and (ii) 8 nm intrinsic SiGe layer grown at 650–700 °C, 20 Torr for channels. For each process, growth rate, layer composition and selectivity (e.g. poly-nuclei density) were first assessed through depositions on 300 mm bare Si (001) substrates or wafers fully covered by dielectrics (SiO2 or Si3N4). Subsequently, optimal blanket conditions were evaluated on test-patterned substrates then tailored for a use during electrical device fabrication. First of all, the Si0.7Ge0.3:B growth kinetics and doping was evaluated at 650 °C, 20 Torr with a SiH2Cl2 + GeH4 + HCl + B2H6 + H2 chemistry. As expected, we had a linear increase of the SiGe:B growth rate with the B2H6 partial pressure (Fig. 2(a)). This was due to a catalysis of H desorption on B surface sites. Selectivity was initially assessed on oxide surfaces to determine the appropriate amounts of B2H6 and HCl for given SiH2Cl2 and GeH4 mass-flows. As shown in Fig. 2(b), two different B2H6 partial pressures, 0.03 and 0.11 mTorr, resulted in a lack and the presence of poly-nuclei on SiO2 surfaces, respectively. “Apparent” and atomic Ge contents, from high resolution X-ray diffraction (HRXRD) and X-ray fluorescence (XRF) measurements, are plotted as functions of the B2H6 partial pressure in Fig. 2(c). The difference between the two gave us access to the substitutional B concentrations, which will soon be compared with atomic and possibly electrically active B concentrations (from SIMS and Hall effect measurements). Given the challenges associated with the formation of germano-salicides with the right properties, we have also evaluated the growth of a Si:B cap on SiGe:B. Various process parameters at 730 °C and 20 Torr were examined in order to have selectivity, thanks to the proper F(SiH2Cl2)/F(HCl) mass-flow ratio, and a meaningful growth rate (addition of B2H6). Active temperature ramps were adopted to prevent elastic relaxation and thus the formation of undulated SiGe:B surfaces. The growth rates (Fig. 3(a)) and structural quality (Fig. 3(b)) of {SiGe:B/Si:B} stacks were assessed with XRD for different Si:B cap thicknesses. SEG of {SiGe:B/Si:B cap} was then used to thicken the SD regions on each side of FD-SOI pMOSFETs. The right thicknesses, a high crystalline quality and a smooth SiGe:B/Si:B interface were obtained, as shown by Fig. 4 TEM cross-section. Challenges faced during the integration of such a SEG process will be discussed, including the selection of the right surface preparation strategy on SiGe channels, faceting and loading effects. Finally, SiGe 20%–30% SEG followed by high temperature oxidation is used to fabricate the SiGe channels of SOI devices. To that end, SEG must be strictly controlled. A blanket study was therefore performed at 20 Torr with SiH2Cl2, GeH4 and HCl. Three temperatures (650, 675 and 700 °C) were evaluated in terms of intrinsic SiGe growth rate, Ge content (Fig.5 (a)) and selectivity versus SiN surfaces. We had at 700 °C a severe layer corrugation and islanding for 8 nm of SiGe grown on patterned SOI wafers, as shown by Fig. 5(b) SEM images. Reducing the growth temperature minimized the surface roughness, with definitely longer growth durations as growth rates were smaller, then. When switching to real patterned devices, a combination of in-line monitoring techniques will be mandatory to properly determine the thickness and Ge content of such thin SiGe channels. Figure 1

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Bhoir, Mandar S., Yogesh Singh Chauhan y Nihar R. Mohapatra. "Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines". IEEE Transactions on Electron Devices 66, n.º 2 (febrero de 2019): 861–67. http://dx.doi.org/10.1109/ted.2018.2888799.

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Kanyandekwe, Joel, Jean-Michel Hartmann, Justine Lespiaux, Tanguy Marion, Lazhar Saidi, Valérie Lapras, Alice Bond et al. "Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices". ECS Meeting Abstracts MA2024-02, n.º 32 (22 de noviembre de 2024): 2355. https://doi.org/10.1149/ma2024-02322355mtgabs.

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Fabricating advanced Fully Depleted SOI (FD-SOI) Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOS) require numerous material and process improvements. Junctions between metal contacts and the channel are considered to be of major importance as they have a direct impact on device performances. A well-controlled increase of the active dopant concentration in the sources and drains regions close to the channel is indeed required to lower the contact resistance. The Selective Epitaxial Growth of tens of nm thick heavily in-situ doped SiGe:B or Si:P Raised Sources and Drains (RSDs) on each side of pMOS or nMOS devices will lower that contact resistance, inject some uniaxial compressive or tensile strain in the channel and yield enough material for (gemano-)silicidation. We study here the impact of process conditions on (i) the incorporation of phosphorus, (ii) the Si:P lattice deformation and (iii) the electrical resistivity of blanket, highly doped Si:P films (>1×10²¹ atoms.cm-3) grown at relatively high temperatures. We then evaluate Si:P growth selectivity on patterned structures. Layers were deposited in an industrial RP-CVD epitaxy reactor at relatively high temperatures (600-750°C) with conventional Si, P and Cl gaseous precursors. Reactor pressures were high (above 100 Torr). The Si:P layers were characterized thanks to XRD, Spectroscopic Ellipsometry, AFM, 4 point probe, Tof-SIMS and Haze measurements. A SiH2Cl2 + PH3 + HCl + H2 chemistry was first of all used to grow those Si:P layers on blanket Si(001) wafers. The partial pressure of phosphine P(PH3) was increased to enhance the phosphorous content [P] in films. Figure 1 shows XRD scans for such layers. Even if [P] increased as P(PH3) increased, the resulting P concentrations were not that high ([P] increased from 0.3% up to 1.6% for a 4-fold increase of P(PH3). Layer resistivities are provided in Figure 2. As expected, there is a resistivity drop from 0.507 mOhm.cm down to 0.405 mOhm.cm whenP(PH3) increases from 8 up to 32Torr. Above 32Torr, there is a plateau close to 0.4 mOhm.cm. This plateau is most likely due to the formation of electrically inactive PxV clusters above a given P concentration. Looking for highly doped SiP layers, we evaluated other solutions to increase [P]. Figure 3 shows HRXRD scans for films grown with a fixed PH3 flow and various SiH2Cl2 partial pressures. Increasing the SiH2Cl2 partial pressure resulted, for a given PH3 flow, in higher Si:P growth rates and P concentrations, as shown in Figure 4 (data coming from Fig. 3 HRXRD profiles). An increase of the PH3 partial pressure with a weak silicon flow indeed ended up in P surface saturation and P desorption. In Figure 5, we show a HRXRD scan typical of a highly tensile-strained, good crystalline quality Si:P film with a phosphorus concentration of 4.35×10²¹ atoms.cm-3. The electrical resistivity of that layer is 0.82 mΩ.cm. Above a P concentration threshold, the electrical resistivity indeed re-increases as [P] increases and reaches really high values (formation of huge numbers of electrically inactive PxV clusters). A Tof-SIMS depth profile of [P] in that sample is provided in Figure 6. TheP concentration from HRXRD is close to the one from Tof-SIMS (4.62×10²¹ cm-3), which is steady as a function of depth. Increasing too much the P content in the Si:P lattice to, ideally, obtain ultra-highly doped and really tensile-strained layers (to increase electron mobility in the channel nearby) is at first sight a no-go, as it results in electrical resistivity degradation. A significant fraction of electrically inactive PxV clusters can however be dissolved with the right annealing scheme to simultaneously have low resistivity and high tensile strain. In order to prepare the integration of such layers into FD-SOI devices, we then investigated selectivity on blanket oxide wafers (not shown here). Finally, we evaluated selectivity for mid P content Si:P layers ([P] = 3.6%) on actual FD-SOI devices. Figure 7 top-view SEM images show 2D Si:P RSDswithout any poly-nuclei on SiO2 isolation, SiN hard mask and spacers of gates. We thus succeeded in introducing highly doped tensile-strained SiP layers into FD-SOI devices. Figure 8 micro-Reciprocal Space Map around the (113) Bragg reflection used to to extract [P] in a 50×100 µm2 measurement box. It was 3.2%, a value slightly lower than on bulk, blanket Si, possibly because of loading effects. Figure 1

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Kochiyama, M., T. Sega, K. Hara, Y. Arai, T. Miyoshi, Y. Ikegami, S. Terada, Y. Unno, K. Fukuda y M. Okihara. "Radiation effects in silicon-on-insulator transistors with back-gate control method fabricated with OKI Semiconductor 0.20μm FD-SOI technology". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 636, n.º 1 (abril de 2011): S62—S67. http://dx.doi.org/10.1016/j.nima.2010.04.086.

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Carvalho, Henrique Lanfredi, Ricardo Cardoso Rangel, Katia Sasaki, Leonardo Yojo, Paula Agopian y Joao Martino. "Improved RFET Performance Using Dual-Aluminum-Contact (DAC)". ECS Meeting Abstracts MA2023-01, n.º 33 (28 de agosto de 2023): 1855. http://dx.doi.org/10.1149/ma2023-01331855mtgabs.

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The reconfigurable field effect transistors (RFET) enable the integration of MOS-type transistors (N-type and P-type) in a single device. The programming gate voltage (VPG) controls the transistor type [1]. A greater area efficiency in logic circuits can be obtained, due to the possible different logic operation, such as NAND to NOR in a single circuit [2 - 3]. Others application include the use of RFET in circuits for security reason in order to avoid the reverse engineering [4]. Figure 1 (A) and (B) show a special type of RFET called BESOI MOSFET that will be one of the devices used in this work. Many conventional RFETs contain NiSi source/drain (S/D) contacts, or other contacts with mid-gap S/D material, providing a symmetrical current between holes and electrons. However such contacts decrease injection of current [5 - 7]. Devices based on dual-doping (DD), provided a significant improvement in the current level, in addition to the ease fabrication due to the absence of the silicidation process, such technology cannot act in doping-free CMOS processes [6] [8]. Figure 2 shows the drain current as a function of the control gate voltage (IDS -VCG) for the BESOI MOSFET. This work presents a new proposal for a dual-contact S/D (DC) RFET, without the presence of DD regions and doping process, enabling dopants-free CMOS processes, using only S/D aluminum contacts, performed through Sentaurus TCAD simulations [9]. Recently in the Integrable Systems Laboratory of the University of São Paulo (LSI-USP), two RFET with aluminum S/D contacts were reported. Both presented a high current for only one type of carrier (holes or electrons) [10 - 13]. The BESOI MOSFET conducts current through its back interface, where the channel between S/D contacts is formed by the bias of the programming gate (VPG), thus its operating mode is divided into P-type (VPG < 0 ) and N-type (VPG > 0). The transistor drain current is controlled by control gate voltage (VCG) [5] [10 - 11]. The Figure 3 shows the drain current balanced as a function of the control gate voltage (ID -VCG), for aluminum BESOI MOSFET’s with and without annealing process (W/A, Wo/A) after the metal deposition [10 - 11]. Using both BE SOI MOSFET with S/D aluminum contact, without process doping, a new RFET Dual Aluminum Contact (DAC) is shown Figure 4. The challenge the design is to flow of current (holes) through the outer contact (W/A contact), due to the influence of the inner schottky low-barrier aluminum contact (Wo/A contact) near to the back interface. Figure 5 shows the carrier density as a function of the depth of the silicon under the inner contact, for different silicon thicknesses (tSi) and fixed programming gate voltage (VPG). The high concentration of electrons near to the inner contact, provided an ohmic contact for electrons [11], however near the back interface, an increasing concentration of holes, due to VPG. Increasing the tSi reduces the influence of charges near the back interface, for tSi=30nm the current flow between the outer contact is possible. However, increasing the tSi decreases the efficiency of the control gate, added to the high electric field in back interface increases IOFF (similar effect described for FD SOI [14]). The Figure 6 shows the drain current as a function of the control gate voltage of BESOI nMOSFET with tSi = 30nm. Such effect can be mitigated, optimizing the coupling the gates. Figure 7 shows the final proposal of the BESOI MOSFET DAC. Figure 8 shows the IDS-VCG for different thicknesses in the S/D contacts (tsi cont). As shown in Figure 5, a greater thickness in the contacts makes possible a smaller influence of the inner contact near the back interface, allowing greater concentrations of gaps, so consequently there is an increase in the p-mode current. However, increasing the thickness of the contacts promotes a reduction in the electron current, due to the increase in the series resistance in inner contact in n-mode. Figure 9 presents the ID-VCG for different VPG bias for the DAC BESOI MOSFET (A) and NiSi BESOI MOSFET (B). Using the DAC BESOI MOSFET, an increase in current was obtained in relation to the NiSi contact (900% in n-type and 300% in p-type), without the addition of doping regions (dual-doping) and using a single contact metal (Aluminum). Figure 1

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32

Goffioul, Michael, Gilles Dambrine, Danielle Vanhoenacker y Jean-Pierre Raskin. "Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs". Journal of Telecommunications and Information Technology, n.º 3-4 (30 de diciembre de 2000): 72–80. http://dx.doi.org/10.26636/jtit.2000.3-4.25.

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The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD) and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lengths and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 um FD SOI n-MOSFETs with a total gate width of 100 um present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for Vds=0.75

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33

Kanyandekwe, Joël, Matthias Bauer, Tanguy Marion, Lazhar Saidi, Jean-Baptiste Pin, Jeremie Bisserier, Jérôme Richy et al. "Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices". ECS Meeting Abstracts MA2022-02, n.º 32 (9 de octubre de 2022): 1190. http://dx.doi.org/10.1149/ma2022-02321190mtgabs.

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Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T<500°C, for the integration of SiP Raised Sources & Drains (RSD) in the upper devices without degrading the electrical performances of the bottom ones. We also target a lowering of the RSD resistance and an increase of the electron mobility in the channel of NMOS devices thanks to tensile strain [2]. Such a know-how will be useful to minimize the contact resistance and fabricate other types of devices such as FINFETs or h-GAA (e.g. nano-sheet devices) with Si (110) surfaces. Experiments were carried out in an Applied Materials epitaxy reactor featuring (i) liquid precursor delivery, together with H2, N2 or He carrier gas capability, enabling the use of Cl2; (ii) “High Precision Temperature Control (HPTC)”, allowing excellent LT control and enabling flexible rotation speeds; (iii) “precision flow distribution PFD-III”, enhancing uniformity performances. Selective Epitaxial Growth (SEG) is usually obtained with “co-flow” processes at rather high temperatures (>600°C). Chlorinated precursors (SiH2Cl2 (+ GeH4) + HCl, typically) are then sent simultaneously into the growth chamber. At LT (<500C°C), HCl cannot decompose, however. To overcome those limitations, we used a Cyclic Deposition Etch (CDE) strategy, with non-selective depositions followed by selective chemical vapor etches, to obtain SiP SEG. This strategy allowed us to obtain high quality films, as shown in Fig.1. The Omega-2Theta scans around the (004) X-Ray Diffraction order for tensile SiP (t-SiP) layers grown at T < 500°C with different Phosphorus concentrations were indeed typical of monocrystalline layers, with well-defined and intense peaks together with numerous thickness fringes. The substitutional P contents in those ~ 60 nm thick t-SiP layers were in the 1.02% - 5.42% range. The good layer uniformity in terms of thickness and P content, over a 300mm wafer radius, is shown in figure Fig.2. These layers grown at T <500°C were smooth, as shown in Fig.3, with a 0.21 nm Root Mean Square (RMS) roughness for a 60nm thick Si:P layer, i.e. a value close to the typical RMS roughness for t-SiP layers grown at high temperature with a chlorinated chemistry. The electrical resistivity in various t-SiP layers is plotted in Fig.4 as function of the substitutional phosphorus concentration and for various growth temperatures in the 450°C – 525°C range. Reducing the temperature by 75°C halved the electrical resistivity. We were able to achieve a resistivity as low as 0.21 mOhm.cm for a t-SiP layer with 5.8% of P grown at 450°C. We then evaluated, at first on tests structures without gates, our process selectivity. A top view Scanning Electron Microscopy image of a t-SiP layer grown non-selectively, with numerous amorphous SiP nuclei on SiO2, is shown in Fig 5.a. After some careful optimization, we succeeded in having fully selective processes versus SiO2, as shown in Fig 5.b. We then tested such optimized processes on low density FD-SOI devices with 28 nm design rules. A top-view SEM image of transistors after such a growth is shown in Fig.6. The growth selectivity was excellent, with nitride spacers and hard masks as well as isolations free of a-SiP nuclei for 31 nm of t-SiP with 4.5% of P deposited in the Sources/Drains. The surface was smooth, with a RMS roughness as low as 0.30nm on active areas, as shown in Fig.7. Thanks to High Resolution Reciprocal Space Maps (HR-RSM), we measured a Phosphorus concentration of 4.5% for that SiP layer grown on SOI. The very high quality of that epitaxy layer, with well-defined thickness fringes, is obvious in Fig.8. Cross-sectional Transmission Electron Microscopy (TEM) images such as the one shown in Fig. 9 enabled us to confirm, at the nanoscale, the excellent quality of such layers in RSDs. To sum up, we were able to develop a tensile Si:P process which was shown to be selective, at a temperature lower than 500°C, against SiO2 and SiN. Such t-SiP layers were successfully integrated in the Sources/Drains regions of FD-SOI 28nm devices. The very low material resistivity and the high phosphorus content should yield, notably because of tensile strain, performant NMOS devices in the near future. [1] C. Fenouillet-Beranger et al., IEEE TED 68, 3142-3148 (2021) [2] V. Chan et al., IEEE 2005 Custom Integrated Circuits Conference 2005, pp. 667-674 Figure 1

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Karsenty, Avi y Avraham Chelly. "Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process". Active and Passive Electronic Components 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/609828.

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Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

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Bédécarrats, Thomas, Philippe Galy, Claire Fenouillet-Béranger y Sorin Cristoloveanu. "Investigation of built-in bipolar junction transistor in FD-SOI BIMOS". Solid-State Electronics 159 (septiembre de 2019): 177–83. http://dx.doi.org/10.1016/j.sse.2019.03.057.

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Harame, David L. "Perspectives on How the "Sige, Ge, & Related Compounds: Materials, Processing, and Devices" Field Has Changed over the Last 20 Years". ECS Meeting Abstracts MA2022-02, n.º 32 (9 de octubre de 2022): 1181. http://dx.doi.org/10.1149/ma2022-02321181mtgabs.

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The field of electronic devices and materials has seen major changes over the last ~20 years. The SiGe, Ge, & Related Compounds: Material Processing, and Devices symposium has documented much of this change. In 2004 the meeting grew out of a desire for the ECS to have a special ongoing symposium on SiGe & Ge as a materials system with increasing importance in silicon semiconductor technology. In 2008 the symposium was expanded to include Ge and Related compounds including SiC and III-Vs on Silicon to recognize the important work in these areas. In 2010 the symposium was expanded to include work in nano-wires, nano-membranes, and light emitting structures with SiGe and/or Ge. In 2012 the symposium explored finfet devices and expanded to include the area of GeSn. In 2014 the symposium explored the use SiGe and related compounds in more complex and advanced structures. In 2016 the conference had a theme around SOI and the FDSOI technology in particular. In 2018 the themes were the ever expanding device structures and role epitaxy has played in it. Each year the plenary talks were selected to give a view of the industry and the conference. These talks give us insight into the symposium and how the field has changed over time. In 2004 the first symposium “SiGe 1: Materials, Processing, and Devices” focused on the SiGe HBT transistor performance and SiGe epitaxial technology. But CMOS scaling was also presented. These trends were reflected in the plenary talks were given by John Cressler on “Using SiGe HBTs for Mixed-Signal Circuits and Systems: Opportunities and Challenges” and Judy Hoyt on “Enhanced Mobility CMOS.” This was the first symposium and we set the conference organization with multiple topical committees and published the first proceedings. In 2006 the “SiGe and Ge 2” symposium continued the themes of SiGe and Ge Epitaxy, SiGe HBT, CMOS scalling, and added silicon photonics. The Plenary talks were given by Dimitris Antoniadis on “Channel Material Innovations for Continuing the Historical MOSFET Performance Increase with Scaling” and Cary Gunn on “CMOS Photonics for High Speed Interconnects.” In 2008 the “SiGe, Ge, & Related Compounds 3” symposium changed in composition bringing IIIV and other compounds into the symposium. The Plenary papers were by Krishna Saraswat on “Germanium for High-Performance MOSFETS and Optical Interconnects,” and Wiebe B. de Boer on “Si and SiGe Epitaxy in Perspective.” Krishna focused on the role of Ge in modern devices and Wiebe focused on the history of SiGe epitaxy at ASM. In 2010 the “SiGe, Ge, & Related Compounds 4” greatly expanded topics while maintaining the core of SiGe HBT and CMOS scaling. The plenary papers were given by K. Kuhn on “Past, Present, and Future: SiGe and CMOS Transistor Scaling” and L. Kimmerling on “Scaling Energy and Form Factor with Germanium Microphotonics.” The conference emphasis continued on SiGe epitaxy, CMOS scaling, and HBT performance with a new optoelectronics focus area. In 2012 the “SiGe, Ge, & Related Compounds 5” focused on the finfet and GeSn. The plenary papers were given by E. Nowak “Advanced CMOS scaling and FinFET Technology” and C. Hu on “FinFET and UTB – How to make very short channel MOSFETs.” There were 4 sessions containing papers with GeSn. In 2014 the “SiGe, Ge, & Related Compounds 6” returned to CMOS scaling and the SiGe HBT. The plenary papers were given by K. Uchida and T. Takahashi on “Extending the FETs: Challenges and Opportunities for New Materials and Structures” and L. Zimmermann (IHP) on “High-Performance Photonic BiCMOS – Next Generation More-than-Moore Technology for the Large Bandwidth Era.” In 2016 the “SiGe, Ge, & Related Compounds 7” focused on FDSOI. The plenary papers were given by Bruce Doris “FDSOI Past, Present and Future” and Carlos Mazure and S. Cristoloveanu “ FD-SOI: The History from Early Transistors to Today.” In 2018 the “SiGe, Ge, & Related Compounds 8” focused on CMOS scaling and SiGe as an enabling material. The plenary papers were given by Maszara, Witold on “Contemporary and Future Logic Devices” and by Tsu-Jae Liu on “ Silicon-Germanium: Enabler of Moore's Law.” In 2020 the “SiGe, Ge, & Related Compounds 9” symposium focused on III-Vs and Silicon Photonic Sensors. The plenary papers were given by N. Collaert on “The revival of compound semiconductors and how they will change the world in the 5G/6G era,” and Ben Miller on “Creating the Interface Universe between the Universe and Data with Integrated Photonic Sensors." Highlights from these plenary talks and symposium topics will be presented.

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Galy, Philippe, S. Athanasiou y S. Cristoloveanu. "BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology". Solid-State Electronics 115 (enero de 2016): 192–200. http://dx.doi.org/10.1016/j.sse.2015.09.001.

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38

Kanyandekwe, Joel, Jean-Michel Hartmann, Justine Lespiaux, Tanguy Marion, Lazhar Saidi, Valérie Lapras, Alice Bond et al. "Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices". ECS Transactions 114, n.º 2 (27 de septiembre de 2024): 253–70. http://dx.doi.org/10.1149/11402.0253ecst.

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The epitaxy of sources and drains is a critical enabler for enhanced transistor performances. In N-type MOS devices, selective SiP epitaxy can simultaneously yield (i) very high levels of electrically active dopants which is crucial for contact resistance minimization and (ii), tensile strain in Raised Sources and Drains (RSD) on each side of Si FD-SOI channels. This study present process solutions in order to benefit from large amounts of phosphorus in a silicon lattice and have thereby tensile strain, while maintaining excellent crystal quality, good surface morphology and a low electrical resistivity. We use here industrial precursors widely used in manufacturing, e.g. a [SiH2Cl2 + PH3 + HCl + H2] chemistry, for the selective deposition, in the 600°C-700°C range, of SiP in conventional epitaxy reactors. We achieved phosphorous concentrations as high as 4.6×10²¹ cm-3 (9.3%) in blanket SiP layers while preserving good crystal quality. In FD-SOI devices, we succeeded in having a selective process yielding rather smooth and free of defects Si:P films with 1.6×10²¹ cm-3(3.2%) of P.

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Kevkić, Tijana S., Vojkan R. Nikolić, Vladica S. Stojanović, Dragana D. Milosavljević y Slavica J. Jovanović. "Modeling electrostatic potential in FDSOI MOSFETS: An approach based on homotopy perturbations". Open Physics 20, n.º 1 (1 de enero de 2022): 106–16. http://dx.doi.org/10.1515/phys-2022-0012.

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Abstract Modeling of the electrostatic potential for fully depleted (FD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is presented in this article. The modeling is based on the analytical solution of two-dimensional Poisson’s equation obtained by using the homotopy perturbation method (HPM). The HPM with suitable boundary conditions results in the so-called HPM solution in general and closed-form, independent of the surface potential. The HPM solution has been applied in modeling the output characteristics of the FDSOI MOSFET, which show good agreement compared with the numerical results.

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40

Srikanya, K. "Low-Power Redundant-Transition-Free TSPC DET-FF with STCB for Enhanced Power and Area Efficiency". International Journal for Research in Applied Science and Engineering Technology 12, n.º 11 (30 de noviembre de 2024): 956–62. http://dx.doi.org/10.22214/ijraset.2024.65246.

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Abstract: In the contemporary era dominated by graphics processing units (GPUs) and artificial intelligence (AI), flip-flops (FFs) have emerged as power-intensive components within processors. Addressing this power consumption challenge, a pioneering approach introduces a single-phase clock dual-edge-triggering (DET) FF leveraging a single-transistor clocked (STC) buffer (STCB). This STCB employs a singular clocked transistor in the data sampling path, eliminating clock redundant transitions (RTs) and internal RTs observed in alternative DET designs. Validated through post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, the proposed STC-DET surpasses existing state-of-the-art low-power DETs in power efficiency, boasting the lowest power-delay-product (PDP) among its counterparts. The modified clock gating, Sapon, Transmission Gate, and gate approach, detailed in the base paper, further refines the TSPC STCDET design, presenting techniques to reduce parameters such as delay or power

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41

Sharma, Rajneesh, Rituraj S. Rathore y Ashwani K. Rana. "Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET". Journal of Circuits, Systems and Computers 27, n.º 04 (6 de diciembre de 2017): 1850063. http://dx.doi.org/10.1142/s0218126618500639.

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The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

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42

Sweeney, Clint, Donald Y. C. Lie, Jill C. Mayeda y Jerry Lopez. "Broadband Millimeter-Wave Front-End Module Design Considerations in FD-SOI CMOS vs. GaN HEMTs". Applied Sciences 14, n.º 23 (9 de diciembre de 2024): 11429. https://doi.org/10.3390/app142311429.

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Millimeter-wave (mm-Wave) phased array systems need to meet the transmitter (Tx) equivalent isotropic radiated power (EIRP) requirement, and that depends mainly on the design of two key sub-components: (1) the antenna array and (2) the Tx power amplifier (PA) in the front-end-modules (FEMs). Simulations using an electromagnetic (EM) solver carried out in Cadence AWR with AXIEM suggest that for two uniform square patch antenna arrays at 24 GHz, the 4 element array has ~6 dB lower antenna gain and twice the half power beam width (HPBW) compared to the 16 element array. We also present measurements and post-layout parasitic-extracted (PEX) EM simulation data taken on two broadband mm-Wave PAs designed in our lab that cover the key portions of the fifth-generation (5G) FR2-band (i.e., 24.25–52.6 GHz) that lies between the super-high-frequency (SHF, i.e., 3–30 GHz) band and the extremely-high-frequency (EHF, i.e., 30–300 GHz) band: one designed in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS process, and the other in an advanced 40 nm Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) process. The FD-SOI PA achieves saturated output power (POUT,SAT) of ~14 dBm and peak power-added efficiency (PAE) of ~20% with ~14 dB of gain and 3 dB bandwidth (BW) from ~19.1 to 46.5 GHz in measurement, while the GaN PA achieves measured POUT,SAT of ~24 dBm and peak PAE of ~20% with ~20 dB gain and 3 dB BW from ~19.9 to 35.2 GHz. The PAs’ measured data are in good agreement with the PEX EM simulated data, and 3rd Watt-level GaN PA design data are also presented, but with simulated PEX EM data only. Assuming each antenna element will be driven by one FEM and each phased array targets the same 65 dBm EIRP, millimeter wave (mm-Wave) antenna arrays using the Watt-level GaN PAs and FEMs are expected to achieve roughly 2× wider HPBW with 4× reduction in the array size compared with the arrays using Si FEMs, which shall alleviate the thorny mm-Wave line-of-sight (LOS)-blocking problems significantly.

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43

Cao, Yong-Feng, M. Arsalan, J. Liu, Yu-Long Jiang y J. Wan. "A Novel One-Transistor Active Pixel Sensor With In-Situ Photoelectron Sensing in 22 nm FD-SOI Technology". IEEE Electron Device Letters 40, n.º 5 (mayo de 2019): 738–41. http://dx.doi.org/10.1109/led.2019.2908632.

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44

Artemio Schoulten, Felipe, Rémy Vauche, Jean Gaubert, Sylvain Bourdel y André Augusto Mariano. "Design of a multi-standard IR-UWB emitter in a 28 nm FD-SOI technology based on the frequency transposition pulse synthesis". Journal of Integrated Circuits and Systems 18, n.º 3 (28 de diciembre de 2023): 1–11. http://dx.doi.org/10.29292/jics.v18i3.793.

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Ultra-WideBand Impulse Radio (IR-UWB) is a wireless communication technology well-suited for short range communications (about 10 meters) and has the advantage to allow real-time location with a precision of 5 cm. However, its use has been standardized in some standards and especially in the IEEE 802.15.4 dedicated to Wireless Personnal Area Network (WPAN) and in the IEEE 802.15.6 dedicated to Wireless Body Area Network (WBAN). After presenting requirements of each standard and a literature survey on the IR-UWB emitter, the design of a multi-standard IR-emitter based on the frequency transposition pulse synthesis is proposed in a 28 nm FD-SOI technology. The proposed design has been validated at the transistor level using electrical simulations which take into account the parasitic capacitance at each critical node of the circuit. Moreover, results show that the proposed circuit has the potential to be the first multi-standard IR-UWB emitter which covers every channel of the IEEE 802.15.4 and 802.15.6 standards.

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45

Duan, F. L., S. P. Sinha, D. E. Ioannou y F. T. Brady. "LDD design tradeoffs for single transistor latch-up and hot carrier degradation control in accumulation mode FD SOI MOSFET's". IEEE Transactions on Electron Devices 44, n.º 6 (junio de 1997): 972–77. http://dx.doi.org/10.1109/16.585553.

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46

Mayeda, Jill, Donald Y. C. Lie y Jerry Lopez. "Broadband Millimeter-Wave 5G Power Amplifier Design in 22 nm CMOS FD-SOI and 40 nm GaN HEMT". Electronics 11, n.º 5 (23 de febrero de 2022): 683. http://dx.doi.org/10.3390/electronics11050683.

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Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and >20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE > 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and >12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. POUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications.

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47

Golman, Roman, Robert Giterman y Adam Teman. "Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism". Journal of Low Power Electronics and Applications 14, n.º 1 (4 de enero de 2024): 2. http://dx.doi.org/10.3390/jlpea14010002.

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Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.

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48

Giterman, Robert, Alexander Fish, Andreas Burg y Adam Teman. "A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI". IEEE Transactions on Circuits and Systems I: Regular Papers 65, n.º 4 (abril de 2018): 1245–56. http://dx.doi.org/10.1109/tcsi.2017.2747087.

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49

"(Keynote) FD-SOI: The History from Early Transistors to Today". ECS Meeting Abstracts, 2016. http://dx.doi.org/10.1149/ma2016-02/30/1952.

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50

Valdivieso, C., R. Rodriguez, A. Crespo-Yepes, J. Martin-Martinez y M. Nafria. "Resistive Switching like-behavior in FD-SOI Ω-gate transistors". Solid-State Electronics, septiembre de 2023, 108759. http://dx.doi.org/10.1016/j.sse.2023.108759.

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