Artículos de revistas sobre el tema "Extensible processor"
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Martin, Grant. "What is a configurable, extensible processor?" ACM SIGDA Newsletter 38, n.º 16 (15 de agosto de 2008): 1. http://dx.doi.org/10.1145/1862846.1862847.
Texto completoMartin, Grant. "What is a configurable, extensible processor?" ACM SIGDA Newsletter 38, n.º 17 (septiembre de 2008): 1. http://dx.doi.org/10.1145/1862849.1862850.
Texto completoGonzalez, R. E. "Xtensa: a configurable and extensible processor". IEEE Micro 20, n.º 2 (2000): 60–70. http://dx.doi.org/10.1109/40.848473.
Texto completoMartin, Grant. "Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors". Journal of Signal Processing Systems 53, n.º 1-2 (29 de noviembre de 2007): 113–27. http://dx.doi.org/10.1007/s11265-007-0153-7.
Texto completoSun, F., S. Ravi, A. Raghunathan y N. K. Jha. "Custom-Instruction Synthesis for Extensible-Processor Platforms". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 2 (febrero de 2004): 216–28. http://dx.doi.org/10.1109/tcad.2003.822133.
Texto completoMisko, Joshua, Shrikant S. Jadhav y Youngsoo Kim. "Extensible Embedded Processor for Convolutional Neural Networks". Scientific Programming 2021 (21 de abril de 2021): 1–12. http://dx.doi.org/10.1155/2021/6630552.
Texto completoNoori, Hamid, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue y Morteza Saheb Zamani. "An architecture framework for an adaptive extensible processor". Journal of Supercomputing 45, n.º 3 (1 de febrero de 2008): 313–40. http://dx.doi.org/10.1007/s11227-008-0174-4.
Texto completoDutheil, Julien Y., Sylvain Gaillard y Eva H. Stukenbrock. "MafFilter: a highly flexible and extensible multiple genome alignment files processor". BMC Genomics 15, n.º 1 (2014): 53. http://dx.doi.org/10.1186/1471-2164-15-53.
Texto completoBauer, L., M. Shafique y J. Henkel. "Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, n.º 10 (octubre de 2008): 1295–308. http://dx.doi.org/10.1109/tvlsi.2008.2002430.
Texto completoSano, Kentaro, Luzhou Wang y Satoru Yamamoto. "Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation". ACM SIGARCH Computer Architecture News 38, n.º 4 (14 de septiembre de 2010): 80–86. http://dx.doi.org/10.1145/1926367.1926381.
Texto completoLi, Lin, Shengbing Zhang y Juan Wu. "Design of Deep Learning VLIW Processor for Image Recognition". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 38, n.º 1 (febrero de 2020): 216–24. http://dx.doi.org/10.1051/jnwpu/20203810216.
Texto completoCetin, E., R. C. S. Morling y I. Kale. "An extensible complex fast Fourier transform processor chip for real-time spectrum analysis and measurement". IEEE Transactions on Instrumentation and Measurement 47, n.º 1 (1998): 95–99. http://dx.doi.org/10.1109/19.728798.
Texto completoLagadec, Loïc, Damien Picard, Youenn Corre y Pierre-Yves Lucas. "Experiment Centric Teaching for Reconfigurable Processors". International Journal of Reconfigurable Computing 2011 (2011): 1–14. http://dx.doi.org/10.1155/2011/952560.
Texto completoWAGGY, SCOTT B., ALEC KUCALA y SEDAT BIRINGEN. "PARALLEL IMPLEMENTATION OF A NAVIER–STOKES SOLVER: TURBULENT EKMAN LAYER DIRECT SIMULATION". International Journal of Computational Methods 11, n.º 05 (octubre de 2014): 1350070. http://dx.doi.org/10.1142/s0219876213500709.
Texto completoWait, Eric, Mark Winter y Andrew R. Cohen. "Hydra image processor: 5-D GPU image analysis library with MATLAB and python wrappers". Bioinformatics 35, n.º 24 (26 de junio de 2019): 5393–95. http://dx.doi.org/10.1093/bioinformatics/btz523.
Texto completoHuang, LinYun, Young-Pil Lee, Yong-Seon Moon y Young-Chul Bae. "Noble Implementation of Motor Driver with All Programmable SoC for Humanoid Robot or Industrial Device". International Journal of Humanoid Robotics 14, n.º 04 (16 de noviembre de 2017): 1750028. http://dx.doi.org/10.1142/s0219843617500281.
Texto completoLi, Hong Yi, Cheng Yang, Xiao Yu Wu y Ya Ning Wu. "A Kind of Video Abstracting System Base on Hadoop". Applied Mechanics and Materials 687-691 (noviembre de 2014): 2186–91. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2186.
Texto completoVlahopoulos, Nickolas y Michael M. Bernitsas. "Three-Dimensional Nonlinear Dynamics of Nonintegral Riser Bundle". Journal of Ship Research 35, n.º 01 (1 de marzo de 1991): 40–57. http://dx.doi.org/10.5957/jsr.1991.35.1.40.
Texto completoCASEAU, YVES, FRANÇOIS-XAVIER JOSSET y FRANÇOIS LABURTHE. "CLAIRE: combining sets, search and rules to better express algorithms". Theory and Practice of Logic Programming 2, n.º 6 (noviembre de 2002): 769–805. http://dx.doi.org/10.1017/s1471068401001363.
Texto completoSaadawi, Gilan M. y James H. Harrison. "Definition of an XML Markup Language for Clinical Laboratory Procedures and Comparison with Generic XML Markup". Clinical Chemistry 52, n.º 10 (1 de octubre de 2006): 1943–51. http://dx.doi.org/10.1373/clinchem.2006.071449.
Texto completoLOIDL, HANS-WOLFGANG, PHILIP W. TRINDER y CARSTEN BUTZ. "TUNING TASK GRANULARITY AND DATA LOCALITY OF DATA PARALLEL GPH PROGRAMS". Parallel Processing Letters 11, n.º 04 (diciembre de 2001): 471–86. http://dx.doi.org/10.1142/s0129626401000737.
Texto completoArsenault, Kristi R., Sujay V. Kumar, James V. Geiger, Shugong Wang, Eric Kemp, David M. Mocko, Hiroko Kato Beaudoing et al. "The Land surface Data Toolkit (LDT v7.2) – a data fusion environment for land data assimilation systems". Geoscientific Model Development 11, n.º 9 (5 de septiembre de 2018): 3605–21. http://dx.doi.org/10.5194/gmd-11-3605-2018.
Texto completoKamal, Mehdi, Ali Afzali-Kusha, Saeed Safari y Massoud Pedram. "Design of NBTI-resilient extensible processors". Integration 49 (marzo de 2015): 22–34. http://dx.doi.org/10.1016/j.vlsi.2014.12.001.
Texto completoShalaby, Nadia, Andy Bavier, Yitzchak Gottlieb, Scott Karlin, Larry Peterson, Xiaohu Qie, Tammo Spalink y Mike Wawrzoniak. "Building extensible routers using network processors". Software: Practice and Experience 35, n.º 12 (2005): 1155–94. http://dx.doi.org/10.1002/spe.667.
Texto completoXiao, Chenglong y Emmanuel Casseau. "Exact custom instruction enumeration for extensible processors". Integration 45, n.º 3 (junio de 2012): 263–70. http://dx.doi.org/10.1016/j.vlsi.2011.11.011.
Texto completoXiao, Chenglong, Shanshan Wang, Wanjun Liu y Emmanuel Casseau. "Parallel custom instruction identification for extensible processors". Journal of Systems Architecture 76 (mayo de 2017): 149–59. http://dx.doi.org/10.1016/j.sysarc.2016.11.011.
Texto completoFei, Y., S. Ravi, A. Raghunathan y N. K. Jha. "A Hybrid Energy-Estimation Technique for Extensible Processors". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 5 (mayo de 2004): 652–64. http://dx.doi.org/10.1109/tcad.2004.826546.
Texto completoFei Sun, S. Ravi, A. Raghunathan y N. K. Jha. "Application-specific heterogeneous multiprocessor synthesis using extensible processors". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 9 (septiembre de 2006): 1589–602. http://dx.doi.org/10.1109/tcad.2005.858269.
Texto completoChen, Xiaoyong, Douglas L. Maskell y Yang Sun. "Fast Identification of Custom Instructions for Extensible Processors". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, n.º 2 (febrero de 2007): 359–68. http://dx.doi.org/10.1109/tcad.2006.883915.
Texto completoLi, T., W. Jigang, Y. Deng, T. Srikanthan y X. Lu. "Accelerating identification of custom instructions for extensible processors". IET Circuits, Devices & Systems 5, n.º 1 (2011): 21. http://dx.doi.org/10.1049/iet-cds.2010.0073.
Texto completoBonzini, P. y L. Pozzi. "Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, n.º 10 (octubre de 2008): 1259–67. http://dx.doi.org/10.1109/tvlsi.2008.2001863.
Texto completoGoyal, Puneet y Narayan Chaturvedi. "Multiple Output Complex Instruction Matching Algorithm for Extensible Processors". International Journal of Computer Applications 49, n.º 21 (31 de julio de 2012): 31–35. http://dx.doi.org/10.5120/7897-1240.
Texto completoYazdanbakhsh, Amir, Mehdi Kamal, Sied Mehdi Fakhraie, Ali Afzali-Kusha, Saeed Safari y Massoud Pedram. "Implementation-aware selection of the custom instruction set for extensible processors". Microprocessors and Microsystems 38, n.º 7 (octubre de 2014): 681–91. http://dx.doi.org/10.1016/j.micpro.2014.05.007.
Texto completoLUKAC, RASTISLAV, PAVOL GALAJDA y ALENA GALAJDOVA. "LUM PROCESSOR WITH NEURAL DECISION". International Journal of Pattern Recognition and Artificial Intelligence 20, n.º 05 (agosto de 2006): 747–62. http://dx.doi.org/10.1142/s0218001406004934.
Texto completoSCHAFFER, KEVIN y ROBERT A. WALKER. "USING HARDWARE MULTITHREADING TO OVERCOME BROADCAST/REDUCTION LATENCY IN AN ASSOCIATIVE SIMD PROCESSOR". Parallel Processing Letters 18, n.º 04 (diciembre de 2008): 491–509. http://dx.doi.org/10.1142/s0129626408003533.
Texto completoKWON, YOUNG-SU y NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR". Journal of Circuits, Systems and Computers 19, n.º 07 (noviembre de 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.
Texto completoSun, Fei, Srivaths Ravi, Anand Raghunathan y Niraj K. Jha. "A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, n.º 11 (noviembre de 2007): 2035–45. http://dx.doi.org/10.1109/tcad.2007.906457.
Texto completoKamal, Mehdi, Ali Afzali-Kusha, Saeed Safari y Massoud Pedram. "Impact of Process Variations on Speedup and Maximum Achievable Frequency of Extensible Processors". ACM Journal on Emerging Technologies in Computing Systems 10, n.º 3 (abril de 2014): 1–25. http://dx.doi.org/10.1145/2567665.
Texto completoSari, Aitzan y Mihalis Psarakis. "A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors". Journal of Circuits, Systems and Computers 26, n.º 08 (11 de abril de 2017): 1740009. http://dx.doi.org/10.1142/s0218126617400096.
Texto completoGreer, Bruce, John Harrison, Greg Henry, Wei Li y Peter Tang. "Scientific Computing on the Itanium® Processor". Scientific Programming 10, n.º 4 (2002): 329–37. http://dx.doi.org/10.1155/2002/193478.
Texto completoHua, Jing, Yingqiong Peng, Yilu Xu, Kun Cao y Jing Jia. "Makespan Minimization for Multiprocessor Real-Time Systems under Thermal and Timing Constraints". Journal of Circuits, Systems and Computers 28, n.º 09 (agosto de 2019): 1950145. http://dx.doi.org/10.1142/s0218126619501457.
Texto completoDixon, Matthew, Jörg Lotze y Mohammad Zubair. "A portable, extensible and fast stochastic volatility model calibration using multi and many-core processors". Concurrency and Computation: Practice and Experience 28, n.º 3 (20 de noviembre de 2015): 866–77. http://dx.doi.org/10.1002/cpe.3727.
Texto completoKamal, Mehdi, Ali Afzali-Kusha, Saeed Safari y Massoud Pedram. "Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions". ACM Transactions on Design Automation of Electronic Systems 21, n.º 2 (28 de enero de 2016): 1–25. http://dx.doi.org/10.1145/2830566.
Texto completoFaraci, Giuseppe, Alfio Lombardo y Giovanni Schembra. "A Processor-Sharing Scheduling Strategy for NFV Nodes". Journal of Electrical and Computer Engineering 2016 (2016): 1–10. http://dx.doi.org/10.1155/2016/3583962.
Texto completoGünzel, Mario, Christian Hakert, Kuan-Hsun Chen y Jian-Jia Chen. "HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems". ACM Transactions on Embedded Computing Systems 20, n.º 5s (31 de octubre de 2021): 1–23. http://dx.doi.org/10.1145/3477019.
Texto completoYin, G. y Y. M. Zhu. "On W.P.1 Convergence of A Parallel Stochastic Approximation Algorithm". Probability in the Engineering and Informational Sciences 3, n.º 1 (enero de 1989): 55–75. http://dx.doi.org/10.1017/s0269964800000978.
Texto completoMahmood, Ausif. "Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures". VLSI Design 4, n.º 1 (1 de enero de 1996): 59–68. http://dx.doi.org/10.1155/1996/91035.
Texto completoAbabneh, Ismail M., Saad Bani-Mohammad y Motasem Al Smadi. "Corner-Boundary Processor Allocation for 3D Mesh-Connected Multicomputers". International Journal of Cloud Applications and Computing 5, n.º 1 (enero de 2015): 1–13. http://dx.doi.org/10.4018/ijcac.2015010101.
Texto completoNICOL, DAVID M. y WEIZHEN MAO. "ON BOTTLENECK PARTITIONING OF k-ARY n-CUBES". Parallel Processing Letters 06, n.º 03 (septiembre de 1996): 389–99. http://dx.doi.org/10.1142/s0129626496000376.
Texto completoMikheev, Andrei y Liubov Liubushkina. "Russian morphology: An engineering approach". Natural Language Engineering 1, n.º 3 (septiembre de 1995): 235–60. http://dx.doi.org/10.1017/s135132490000019x.
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