Tesis sobre el tema "ESD"
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Soldner, Wolfgang Wilhelm. "HF-ESD-Codesign". Aachen Shaker, 2009. http://d-nb.info/996579168/04.
Texto completoDrüen, Stephan [Verfasser]. "Virtual ESD Test – : An ESD Analysis Methodology at Chip Level / Stephan Drüen". Aachen : Shaker, 2007. http://d-nb.info/1166508595/34.
Texto completoSoldner, Wolfgang W. [Verfasser]. "HF ESD CODESIGN / Wolfgang W Soldner". Aachen : Shaker, 2009. http://d-nb.info/1159834857/34.
Texto completoChung, Youngeun. "Education for Sustainable Development (ESD) in Sweden: A study of ESD within a transition affected by PISA reports". Thesis, Uppsala universitet, Institutionen för geovetenskaper, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-210157.
Texto completoDukhan, Al-Hytham y Dastan Hassan. "Undersökning av alternativa ESD-skydd inom produktion". Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-19657.
Texto completoAs time goes on, the manufacturing of electronic products is increasing and evolving, which calls for the introduction of protective measures on electronic components. Electronic components can be problematic as they produce electrostatic discharge (ESD), something that the manufacturing industry aims to reduce. By implementing safety measures in various ESD-protective systems, which leads to a minimized risk of ESD damage. A project has been carried out at the company Veoneer, the project is based on a study regarding the current ESD-system and a study on two other ESD-protection systems. Literature study and experimentation have been accomplished in relation to the three ESD-protective systems to evaluate the costs and implementation possibilities of production and to further evaluate the effectiveness of neutralization of the static charge. The following ESD-protective systems examined are the currently using ESD-packaging, replacement of ESD-plastic to plastic trays only in combination with ionizers and finally adjustment of the relative humidity. The current ESD-system protects production from electrostatic discharges. The problem with the current system is the costly price ratio of the ESD-packaging. Veoneer carried out a project based on a study regarding the current ESD-system and a study on two other ESD-protective systems. Through the study of relevant literature and experimentation, the three ESD-protective systems have been analyzed to evaluate the costs and implementation possibilities of production and further evaluate the static charge's effectiveness of neutralization. The following ESD-protective systems currently use ESD-packaging, replacement of ESD-plastic trays to plastic trays with ionizers, and finally, adjusting the relative humidity. On the one hand, the current ESD-system protects production from electrostatic discharges, but the current system's problem is the costly price ratio of the ESD-packaging. Project management is centered around the project-based approach. The project-management method consists of four stages of feasibility: studies, planning, implementation, and closure. The control methodology has ensured that the project runs smoothly. The current ESD and ionizer systems were investigated through research studies and experiments, whereas adjustment of humidity was investigated solely through literature studies and company reports. To begin the experiments, measuring tools were arranged to calculate the electrostatic charge in regards to the ESD-packaging and the plastic packaging. Ionizers were utilized for the final experiment to measure the electrostatic neutralization capacity with plastic packaging. Economic calculations have been carried out by the ESD-plastic packaging in conjunction with ionizers and discovered that plastic packaging alone can determine the price difference between the ESD-systems. The experiment resulted in safe and approved readings, meaning that from an experimental perspective, the ionizer system and the current system do not expose products to any ESD-risk. The introduction of ionizers could lead to huge savings if they were to be used as a replacement option. The ionizer should not be implemented directly; more detailed studies need to be carried out before a new ESD-system is acquired. The company's humidity studies showed negative results, implying that the company could not carry out physical experiments concerning humidity. Several proposed improvements have been suggested regarding the current ESD-protection and ionizer system. The improvement proposals includes change of material from an economic and ecological sustainability perspective, and several proposals havebeen made regarding the working standards.
Muthukrishnan, Swaminathan. "ESD Protected SiGe HBT RFIC Power Amplifiers". Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/31705.
Texto completoMaster of Science
Černá, Martina. "Překážky volného pohybu pracovníků v judikatuře ESD". Master's thesis, Vysoká škola ekonomická v Praze, 2009. http://www.nusl.cz/ntk/nusl-18117.
Texto completoZupac, Dragan 1961. "ESD-induced noncatastrophic damage in power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/291470.
Texto completoCao, Yiqun [Verfasser], Stephan [Akademischer Betreuer] Frei y Bernd [Gutachter] Deutschmann. "High-voltage ESD structures and ESD protection concepts in smart power technologies / Yiqun Cao ; Gutachter: Bernd Deutschmann ; Betreuer: Stephan Frei". Dortmund : Universitätsbibliothek Dortmund, 2019. http://d-nb.info/1200209605/34.
Texto completoEscudié, Fabien. "Optimisation de modèles comportementaux de composants pour la prédiction de défaillances fonctionnelles et matérielles liées aux décharges électrostatiques (ESD)". Thesis, Toulouse 3, 2018. http://www.theses.fr/2018TOU30266/document.
Texto completoElectrical Fast Transient (EFT) are one of the concerns of embedded system engineers. They can lead to system malfunction. EFT are the cause of a large number of hardware and software failures. Our study is mainly focused on the impact of Electro Static Discharge (ESD) on embedded electronic systems, focusing on car's applications. According to a Renault's study, a car can suffer two discharges per day during its entire life. System engineers do not have any tools to predict the ESD impact on the systems. In order to predict the ESD path throughout the electronic system and adjust the ESD protection strategy to provide proper protection for all critical components, some researches around the world are in process. The research results from ESE working group from the LAAS-CNRS laboratory, were mainly on passive components, integrated circuits and electronics boards modeling methods, implemented in VHDL-AMS language. Integrated circuits have an internal ESD protection network that helps to deflect the stress from critical areas. The methodology developed in the last few years allows to model the behavior of this protection network. However, these models are basically made, they are made of the triggering level of the protection and the impedance value of the component depending on the ESD stress amplitude. No information on the transient behavior of the protections is included in this model. It is not possible to predict some failures related to the transient phenomenon of the protection like triggering and turning on time that induce very high overvoltage or mismatch on the current levels estimation. The various topics covered during this thesis allows to solve these problems by using a, proposed dynamic model. Different methods are proposed to extract the parameters used into the dynamic model. One important point also aborted into this document is that the model have to be able to predict the soft failure which can appear in the system during an ESD stress.[...]
Narasimha, Raju Divya. "Study of ESD effects on RF power amplifiers". Master's thesis, University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4993.
Texto completoID: 029809372; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (M.S.)--University of Central Florida, 2011.; Includes bibliographical references.
M.S.
Masters
Electrical Engineering and Computer Science
Engineering and Computer Science
Malobabic, Slavica. "Transient Safe Operating Area (TSOA) for ESD applications". Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5420.
Texto completoID: 031001296; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Juin J. Liou.; Title from PDF title page (viewed March 7, 2013).; Thesis (Ph.D.)--University of Central Florida, 2012.; Includes bibliographical references (p. 252-262).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
Papoušek, Tomáš. "Omezení volného pohybu pracovníků v rámci rozhodnutí ESD". Master's thesis, Vysoká škola ekonomická v Praze, 2007. http://www.nusl.cz/ntk/nusl-2476.
Texto completoBěťák, Petr. "Modelování a návrh ESD ochran v integrovaných obvodech". Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-233447.
Texto completoNolhier, Nicolas. "Methodologie de conception des protections des circuits intégrés contre les décharges électostatiques". Habilitation à diriger des recherches, Université Paul Sabatier - Toulouse III, 2005. http://tel.archives-ouvertes.fr/tel-00265344.
Texto completoBönisch, Sven Peter. "Die elektrostatische Entladung (ESD) bei kleinen Abständen und Spannungen". [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=969940599.
Texto completoZur, Nieden Friedrich [Verfasser]. "Charakterisierung und Modellierung von ESD-Prüfgeneratoren / Friedrich Zur Nieden". München : Verlag Dr. Hut, 2014. http://d-nb.info/1063221897/34.
Texto completoMrňák, Petr. "Veřejná správa v judikatuře ESD a v tuzemské praxi". Master's thesis, Vysoká škola ekonomická v Praze, 2010. http://www.nusl.cz/ntk/nusl-75771.
Texto completoNikolaidis, Théodoros. "Optimisation des performances ESD de circuits intègres CMOS submicroniques". Grenoble INPG, 1995. http://www.theses.fr/1995INPG0185.
Texto completoAlexis, Engström. "Utbildning och hållbar utveckling : En studie av innehåll och normativitet i utsagor om hållbar utveckling i utbildningssammanhang". Thesis, Uppsala universitet, Institutionen för pedagogik, didaktik och utbildningsstudier, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-233150.
Texto completoGlaser, Ulrich. "Complex ESD protection elements and issues in decananometre CMOS technologies /". Zürich : ETH, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16960.
Texto completoUngru, Thomas [Verfasser]. "Influence of ESD on integrated circuits during operation / Thomas Ungru". München : Verlag Dr. Hut, 2019. http://d-nb.info/1184090548/34.
Texto completoBoldkhuyag, Enkhtuya. "Values and pro environmental behaviour among Mongolian adolescents:Implications for ESD". Thesis, Uppsala universitet, Institutionen för geovetenskaper, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-258952.
Texto completoRomanescu, Sorin. "Modèle compact paramétrable du SCR pour applications ESD et RF". Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00648390.
Texto completoPan, Zhihao [Verfasser]. "Modeling and optimization of discrete ESD protection devices / Zhihao Pan". München : Verlag Dr. Hut, 2015. http://d-nb.info/1074063724/34.
Texto completoVicherek, Ondřej. "Vliv vybraných rozhodnutí ESD na formování společné obchodní politiky EU". Master's thesis, Vysoká škola ekonomická v Praze, 2015. http://www.nusl.cz/ntk/nusl-262003.
Texto completoMüller, Lutz. "Untersuchung und Modellierung elektrostatischer Entladungen (ESD) von elektrisch isolierenden Oberflächen". [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11380441.
Texto completoLin, Che-Shih y 林哲仕. "Study on Modeling of ESD Protection Devices for Circuit-Level ESD Simulation". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96451142963494812486.
Texto completo國立交通大學
電機學院微電子奈米科技產業專班
95
In addition to high performance, low cost, and low power, reliability is also an important issue in the development of VLSI technologies. Damage caused by ESD (Electro-static Discharge) is a serious threat to VLSI reliability. It is well know that ESD failures constitute a major portion of customer returns, so it is important to provide ESD protection in the IC chip against ESD damages If an ESD stress current flows into internal circuits, it can cause internal damage. Therefore, it is necessary to predict ESD immunity, which depends on the circuit design and layout. At present, trial-and-error approaches still dominate in ESD design, which result resource-consuming iteration. ESD simulations for the protection circuits are effective for solving this problem. The purpose of thesis is to construct an ESD circuit simulation system based on the SPICE circuit simulator. Through the SPICE simulation, we can reduce design cycle. In our ESD protection network, we choose the diodes, BJT, and NMOS as ESD protection devices. We will model those devices corresponding to the experiment and implement the models to the ESD circuit simulation system.
yi, Wang kuang y 王光一. "ESD/TLP Measurement Iustruments and ESD Immunity Anaiysis in the Electronic Device". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/05938833068028418006.
Texto completo大葉大學
電機工程學系碩士在職專班
93
ABSTRACT Reliability engineer of integrated circuit occupies a most important position when the accuracy of process got better and better . The improvement of the technical procedure will enhance the reliability of integrated circuit in design. There is another element to effect the reliability engineer when we enhances the yield. Though one of the factors is the ESD of destruction.it can be avoidable. There are many productions of the protection circuit of ESD in academic.but ESD protect the circuit and some elements which protect the circuit are often effected by the efficiency of ESD stress cause the circuit protection is useless. The reliable of the circuit protection element is queried. The thesis will use some ESD protection Devices to do ESP testing. Analyze anti ESD ability. Pick up element to avoid latch up effect . To analyze the reliable ability and ESD energy. we can use the TLP and ESD instruments which is similar to ESD stress to test the anti-static electricity ability. Prote element can maintain the voltage effectively. When the element of voltage value enter the collapse point effectively and maintain appropriate capacity of releasing the ESD. Furthermore, it also prevent the coming of second collapse point effectively. Therefore how to find and the first and second appropriate collapse point is very impertant. Analyzing the static electricity workable or not in a circuit.
Lu, Hsueh-Meng y 呂學銘. "New ESD Protection Circuits". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/22693499839469841539.
Texto completo國立臺灣科技大學
電子工程系
92
Due to the area-efficient, the SCR has become the best choice for ESD protection circuits. However, the behaviors of latchup and higher trigger voltage are the limitations for SCR’s application. Therefore, it is needed to pay much attention to design better ESD protection circuits in deep-submicron CMOS IC. In this thesis, we have proposed two new ESD protection circuits based on SCR structure. The performance of these protection circuits is really excellent when ESD event happened. One of the protection circuits is a highly latchup-immune stacked-MOSFET with silicon controlled rectifier (SM-SCR) device. The latchup effect could be avoided by using the stacked-MOSFET to turn on/off the SCR. Meanwhile, a zener diode and gate-coupled transistor can lower SM-SCR trigger voltage. The other protection circuit is a highly latchup-free ESD protection circuit with silicon controlled rectifier (LFSCR) device to demonstrate the effective ESD protection effect. The mechanism is to turn on/off the SCR by two MOSFETs during an ESD event. During the ESD event, the PMOS transistor is utilized to turn on SCR and the NMOS transistor to turn off SCR. Therefore the latchup effect can be easily eliminated by this device. Besides, the purpose of the zener diode and gate-coupled transistor could lower the trigger voltage. The implementation of these two on-chip protection circuits has been fabricated through National Science Council Chip-Implementation-Center (CIC). These two ESD protection circuits have been applied for patents in R.O.C. and U.S.A.
Liu, Rui-Hong y 劉睿閎. "ESD Protection Designs for 2.4GHz T/R Switch Front-End Circuits". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/92182912861687902240.
Texto completo國立交通大學
電子工程學系 電子研究所
104
As the CMOS technology develops so fast, radio-frequency integrated circuits (RF ICs) has been widely implemented in CMOS process. It has the advantage of a high integration and a low cost. Electrostatic discharge (ESD) has been one of the most serious reliability issues of CMOS processes, so ESD protection design is very important. However, undesirable parasitic effect is induced by the ESD protection design in RFICs. Consequently a successful RF ESD protection design needs well ESD protection ability and small parasitic effect. In this thesis, two RF ESD protection designs for T/R switch front-end circuit are proposed. The first one can reduce the parasitic effect and sustain ESD stress. The second one can sustain ESD stress without extra ESD protection device. Both ESD protection designs are applied to 2.4GHz T/R switch front-end circuit. An RF ESD protection design for traditional T/R switch front-end circuit is also proposed in this thesis. The number of the ESD protection devices is reduced in this design. Besides, silicon-controlled rectifier (SCR) is embedded in T/R switch, and the detection circuit, which is used in power-rail ESD clamp circuit, can sent trigger signals to trigger the SCR. The embedded SCR and parasitic diode can provide ESD discharge paths. Moreover, this ESD protection designs are applied to 2.4GHz traditional T/R switch front-end circuit.
Feng, Yao-Wu y 馮耀武. "ESD Characteristics of Diffusion Resistor and its Application in On-chip ESD Protection Design". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10028854190621163628.
Texto completo國立交通大學
電機學院碩士在職專班電子與光電組
97
The high current conduction in silicided N+ diffusion resistor and non-silicided N+ diffusion resistor under the 100nsec pulse condition had been characterized and modeled carefully in this work. We find the resistances of both types resistors change with the square root of the stress time. It induces the current decreasing and voltage increasing with the stress time. The root cause of the non-linear IV characteristics of the diffusion resistor under high current stress can be well explained by the Joule-heating induced the resistance change. In additional, we also find that these two diffusion resistors during high current stress will appear some different characteristics. Due to these different characteristics, the silicided device cannot use the same layout as the silicided blocking device on ESD protection design.
Chuang, Che-Hao y 莊哲豪. "ESD Protection Design with TVS (Transient Voltage Suppressor) to Meet System-Level ESD Specifications". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4h429h.
Texto completoYeh, Shih-Ping y 葉士平. "ESD Protection Technology for LCM". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/13313551003104927055.
Texto completo逢甲大學
電子工程所
91
This thesis will discuss Liquid Crystal Display module (LCM) Electro-Static Discharge(ESD) protection techniques. In order to up-grade the protection capability of LCM ESD, Also to build up LCM ESD protection design rule. This thesis will also survey ESD protection techniques in the component level and system level. Such as : Human body model(HBM)、Machine model(MM)、Charge device model(CDM)、Air discharge model、Contact discharge model, and to compare the speciality and experiment method between component level and system level for which based on the capability of integrated circuits protection. Add special LCM ESD protection design to verify and find out the best design conditions for increase LCM ESD protection. In addition to build up LCM ESD standards, We will also build up testing equipment for LCM in the ESD protection. It is also hope the proposed testing equipment and the test procedure can be applied in the industry as a dedicate ESD standard for LCMS. The experiment condition is base on the LCM for mobil phone. The constructure is Liquid crystal display(LCD)、Driver IC and Flexiable Printed Circuit board(FPC). Different protection design such as : Power protectind design、Resist protection design、Guard-Ring protection design、Induction protection design and shield protection design and so on. Judging from the above testing design. It is work on the improvement of ESD protection, will make LCMs to simulate the above protection design and build up mobile phone and ESD testing equipment. It is to be mentioned in this thesis under single protection design for LCM ESD. The performance is not as good as a multi protection design. So, it is proved that ESD protection design works on overall protection program. The ESD protection mentioned in this thesis is patent pending. The last in this thesis pointed out the best design of LCM ESD protection, LCM ESD level standard and LCM ESD testing equipment and build up the standard for LCM ESD protection design and experiment.
LI, CHENG-TAO y 李承道. "The Near Field Measurement Technology for System Level ESD Testing and Optimization of ESD Protection". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8n3m95.
Texto completo國立高雄大學
電機工程學系碩博士班
106
Consumer electronics products become more versatile and smaller in size, and the feature size of circuits becomes smaller, too. The main reason why the ability of resisting electrostatic discharge is weak is that the size of circuit is smaller. In the system level electrostatic discharge testing, the testing results of the Class B and the Class C are temporary failures. For engineers who design system level electrostatic discharge it is difficult to find broken circuit directly and it delay the schedule of new products development. If it can quickly find the location of broken circuit or discharge path by a detection method, it will not reduce the cost of product only. It can design guild rule for electrostatic discharge. For the above situation, this paper develops the time domain electrostatic discharge near field system. It combines time domain instrument with near field system to observe the magnetic field of DUT with time. In this paper, the circuit which has slot pattern is used to verify the measured results and observed the slot for impacting return current. After all, by researching the location of ferrite bead for optimizing electrostatic and signal integrity. In the future, it provides a new electrostatic discharge testing to find discharge path directly and establish the design guild for electrostatic discharge and power/signal integrity optimization.
Tsai, Ming-Hsien y 蔡銘憲. "Design of Electrostatic Discharge (ESD) Protection for RF Front-End Integrated Circuits". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/63142812027175306133.
Texto completo國立清華大學
電子工程研究所
99
By co-design methodology, this study focuses on ESD protection design techniques for RF front-end integrated circuits. In a wide frequency range (from a few GHz to millimeter wave up to V-band), the proposed circuits achieve excellent RF characteristics and high ESD protection level simultaneously. The design concept is to treat the ESD protection devices as a part of the input matching network to obtain the required ESD robustness without degrading the RF performance. For RF low-noise amplifiers (LNAs) operating at 5.8 GHz, three ESD protection topologies (dual-diode, modified-SCR, and modified-SCR with dual-diode) are investigated. We propose an ESD network with multiple ESD current paths, demonstrating a 4.3-A transmission line pulse (TLP) failure level, corresponding to a 6.5-kV human body model (HBM) protection level. In addition, a wideband LNA (2.6?{6.6 GHz) with shallow-trench-isolation (STI) diodes is realized. We propose a co-design methodology for the wideband LNA with ESD protection, demonstrating a 4-kV HBM ESD performance and no degradation on RF performance. Also, the chip area of ESD protection is much smaller compared to the published distributed ESD protection technique for wideband LNA applications. For millimeter-wave LNAs, the K-band and V-band LNAs using RF junction varactors with scalable models for ESD protection and noise optimization simultaneously are designed and realized. We propose of using the gate-source junction varactor used for noise optimization and charge device model (CDM) protection simultaneously, which has not been reported previously. A 24-GHz ESD-protected LNA presents a NF of 2.9 dB and a power gain of 15.2 dB, demonstrating a 2.7-A (corresponding to a 4-kV HBM) and an 11.4-A ESD protection levels using transmission line pulse (TLP) and very fast transmission line pulse (VFTLP) tests, respectively. In addition, the V-band LNA achieves a NF of 5.2 dB and a peak power gain of 10.9 dB at 51 GHz, achieving an over 2-kV ESD protection, and only 0.8-dB degradation for both NF and power gain compared with the reference design. Finally, an analog front-end circuit with dual-directional SCR ESD protection is designed and realized for passive UHF-band RFID tag. We propose a symmetrical dual-direction ESD protection technique, which is suitable for large signal swing of RFID tag application. The measured result shows ESD levels of 3.0-kV HBM and 200-V MM, respectively. The proposed ESD protection embedded in RFID tag becomes a must for yield improvement during antenna assembly or testing process.
Jyh, Song Hung y 宋弘智. "ESD Protection Circuit for RF Circuits". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23574758446776708309.
Texto completo大葉大學
電機工程學系碩士班
93
In this thesis, a electrostatic discharge(ESD) protection circuit has been designed for radio frequency(RF) power amplifier of DCS 1800 system. The TSMC 0.18um RF model, and Synopsys technology company's EDA tool have been used to simulation the class E Power Amplifier's RF parameter, and then, utilize HSPICE to simulate the ESD protection circuit. Finally, the ESD protection circuit has been added to class E power amplifier and to obtain the effect of ESD circuit on RF parameter, then adjust ESD protection circuit parameter to have less effect on RF parameters and can pass two thousand voltage of human body model(HBM) ESD stress.
董順萍. "ESD Protection of Handset Video Products". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/44856322892750950042.
Texto completoPlachý, Robert. "Pojem pozitivní opatření v judikatuře ESD". Master's thesis, 2010. http://www.nusl.cz/ntk/nusl-297011.
Texto completoLai, Yu-Hsuan y 賴玉瑄. "ESD Protection Design for Broadband Circuits". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/7ed5x8.
Texto completoren, chagn ming y 張銘仁. "The Optimal Control Strategies of Clean room ESD/ESA Problems by DC Pulsed Ionizer". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/32769254570013426397.
Texto completo南台科技大學
電機工程系
92
When environment fact is set, we demonstrate a set-by-step program, which we used to optimize the performance of a DC pulsed ionizer in a cleanroom environment. By sequentially choosing the appropriate pulsewidth time, magnitude, and (-v/+v) percentage output of emitter supply voltage, one can obtain the optimal voltage swing and decay time. The effectiveness of this strategy is validated through a three-month follow-up monitoring.
Lee, Chien-Ming y 李健銘. "ESD PROTECTION DESIGN FOR RADIO FREQUENCY CIRCUITS". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/52615812726859233645.
Texto completo國立交通大學
電子工程系
90
To reduce the parasitic effect of the ESD protection circuit devoted to RF integrated circuits, there are three major designs proposed in this thesis. In the first part, the two-port GSG measurement setup in the radio-frequency region (~GHz) is used to measure the power gain S21 and noise figure from different ESD devices in 0.25-µm CMOS process. Therefore, we can get the relationship between RF performance and ESD level among different ESD devices. The most suitable ESD device for RF application can be selected from the measured data. The second part presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBM) ESD robustness of 8kV. By including a turn-on efficient power-rails ESD clamp circuit into the RF circuit, the ESD protection devices of the RF input pin can be operated in the forward-biased conduction, rather than the traditional junction breakdown condition. Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in a 0.25-µm CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as 8kV under the HBM ESD test. In the third part, a new structure of ESD protection circuit for RF application is proposed. The series LC-tank is used to block the signal loss and noise figure from the ESD protection devices to the RF input pin. The inductor is made by the top thick metal, which is suitable to conduct ESD current. The experimental results have shown that the RF performance of ESD protection circuit with LC-tank is superior to that of the traditional ESD protection circuit with double diodes. The ESD protection circuit with LC-tank is more suitable for RF application when the operation frequency becomes higher. The research results of this thesis have been applied 3 U.S. patents. Moreover, the contents of this thesis had also published three conference papers. One paper had been presented in the 2002 IEEE RFIC Symposium, the second paper has been accepted by the 2002 VLSI Design/CAD Symposium, and the third paper has been submitted to 2002 Taiwan ESD Conference.
Lee, Wei-Ju y 李維如. "The Research of ESD Consumer’s Purchasing Factors". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/68063121247108393199.
Texto completo國立中山大學
企業管理學系研究所
90
Electronic Software Distribution(ESD) sprung up in the U.S.A. from 1994. The business volume of global ESD market was 2.5 hundred million in 1996 and the growing rate was over 100% every year. ESD attains to maturity in the U.S.A. and Europe, but the concept of ESD is still in the initial stage in Taiwan. There are a few firms offering services in this scope. However, consumers do not understand ESD clearly. Furthermore, there are very few researches about ESD in Taiwan. All the circumstances are unfavorable for popularizing and promoting ESD in Taiwan. For the above mentioned reasons, this study will seek to further our understanding of consumers’ purchasing behavior and purchasing factors through ESD and how important the purchasing factors affect consumers’ behavior. This study got the purchasing factors of ESD by analyzing and generalizing the functions of distribution in the Web, the characteristics of Internet marketing and digital product, and the Internet consumers’ purchasing factors. After that, this study analyzed the importance of these ESD consumers, purchasing factors. A web survey was conducted on one ESD web site, called SoSoft.net. The total valid sample is 95 consisting of 37 ESD patrons and 58 ESD non-patrons. And the main findings of this research are as the following: 1.The purchasing frequency of the ESD patrons is unfixed, the rate of repurchase is high and the average amount of purchasing is medium. 2.The characteristics of the responded majority are young, highly educated, and are students or employees of the IT industries. 3.The ESD consumers had long histories of using Internet. They tend to be frequent and long hour Web surfers. About half of them have Broadband (ADSL) access to the Internet. 4.For the ESD patrons, six factors are extracted from the questions on ESD purchasing factors. The factors are “purchasing process”, “characters of Internet marketing”, “variety of service”, “option of products” and “transaction costs”. As for the ESD non-patrons, six factors are extracted from the questions on ESD purchasing factors as well. The factors are “design of the website content”, “characters of Internet marketing”, “distinctive products and service”, “efficiency of purchasing process” “Web security” and “availability of try-before-you-buy service”. 5.The ESD non-patrons are much more concerned with the security of payment and the privacy of personal data. 6.With ESD purchasing experience or not, the Consumers value all the purchasing factors with the same importance. 7.The ESD patrons’ concerns of “purchasing process”, “variety of service” and “option of products” are influenced by their different age. And their occupations influence their concerns about “variety of service”. As for ESD non-patrons, their gender and education influence their concerns about “distinctive products and service”. “efficiency of purchasing process” is influenced by the difference in monthly income. 8.The area of residence, Internet connection speed, and the period in history of contacting Internet do not influence the ESD consumers’ concerns of purchasing factors.
Lee, Wen-Ming y 李文明. "A Study of ESD Reliability Analysis in". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/62021679566996546225.
Texto completo大葉大學
電機工程研究所
88
The ESD reliability in power MOSFETs will be investigated in this thesis. The testing samples were 100V LD nMOS, 200V LD nMOS, which were designed and developed by ourself, and commercial ICs which were consisted of IRF640, RFW2N06RLE and RLP03N06CLE. From the experimental results, ESD zap pulses at the gate terminal will cause electrons or holes trapped in the gate oxide and lossing the Si-SiO2 interface integrity, especially for the 100V LD nMOS, 200V LD nMOS, and IRF640, in which they do not have any ESD protection circuit. Electrons or holes trapping in SiO2 layer will be caused the threshold voltage increasing or reduction, and even resulted in electron mobility degradation. The RFW2N06RLE and RLP03N06CLE power VDMOS ICs which with different kinds of ESD protection circuit are less influenced by ESD pulses experimentally. Moreover, in some situation the latent damage of electrostatic discharge in a power MOSFET can’t easily find out immediately. Eventually, in order to make sure a good reliability and long lifetime of power MOSFETs, the ESD protection circuit design to prevent ESD damages in a power MOSFET is necessary.
Chen, Ming Hum y 陳銘輝. "The ESD Protection Design of Lateral DMOSFETs". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/33355042408370259206.
Texto completo大葉大學
電機工程學系碩士班
94
In recent years, many electric systems, such as automatic electronics, power switches, power rectifiers, and display drivers, have widely used power MOSFETs . In the future, the electric industry will develop power MOSFETs into high voltage, high current, and high speed switch modules. However, the problems of ESD still exist and are even more serious than intelligent circuit in low voltage process. Because electrical static discharge (ESD) problems are getting more and more serious, design of traditional ESD devices mostly utilizes trial and error, experimental measurements, or equal circuit simulations with SPICE to acquire proper protection devices. This research used computer simulation software TSUPREM-4 and MEDICI to simulate and improve the electrical property of device and to design a set of ESD protection circuits. Besides, this study also used the comparison results of the SCR layout parameters to make the electrical property of device performance meet the Design Window range and to reach the optimum of the ESD protection.
Hsu, Pei-Fung y 徐培峰. "Investigation on ESD Sensor by Liquid Crystal". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/wvkhn6.
Texto completoLee, Zon-Lon y 李宗隆. "ESD Impacts on Low Dropout Voltage Circuit". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/54058928376807814049.
Texto completo國立交通大學
電機學院光電顯示科技產業專班
96
The thesis proposes a low-dropout (LDO) regulator with ESD Impacts. Thus, the content of this thesis contains two parts. The first part discusses the design of a low-dropout regulator. With the exponentially increasing of portable battery-powered electronic equipments, such as mobile phones, digital cameras and so on, power management has becoming more and more important and popular. The design of low dropout regulators is widely used in power management since it has a better load transient response, less output noise, and few off-chip components compared to the design of switch-mode regulators. Stability is an important issue in the design of LDO linear regulators. In the conventional architecture, the key factors affecting the system stability are the wide load current range and the value of the output capacitor. Therefore, there exist many proposed compensation techniques to stabilize and improve the whole system. According to the type of output capacitor, LDO regulators can be simply classified into two groups: LDOs with off-chip or on-chip output capacitor. These LDO linear regulators with off-chip capacitor need a large capacitance at output node to generate a dominant pole at low frequency to achieve the stability. They are mostly used for supplying the system with the characteristic of low quiescent current at light loads owing to the current efficient buffer used in the LDOs. The other LDO regulators use an on-chip small output capacitor based on the Miller-compensated technique. Thus, the capacitor can be integrated into the chip, which has the advantage of the saving the footprint area. This type of capacitor-free LDOs is well suited as a stable dc voltage supply for portable electronic devices. The second part of this thesis discusses how ESD impacts the low-dropout regulators. In some situation, the latent damage of electrostatic discharge in a power MOSFET can't easily find out immediately. Eventually, in order to make sure a good reliability and long lifetime of power MOSFETs, the ESD protection circuit design is needed to prevent ESD damages in a power MOSFET design. This thesis provides the reliability engineers of integrated circuit a most important concept of ESD design of power IC. The improvement of the ESD will enhance the reliability of integrated circuit in power IC designs.
Tsai, Ming-Yuan y 蔡明圜. "An ESD Protection Design of LCD Drivers". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/26217304903479450127.
Texto completo國立聯合大學
電子工程學系碩士班
95
In recent years, industries of LCD (Liquid Crystal Display) be progressed very quickly. When dots per inch (dpi), brightness and responding speed of LCDs are improved in every generation, the LCD driver IC must develop in the trend of high frequency and high voltage. Thus, the LCD driver IC must be met with high speed scanning and fast driving properties. By using the high-voltage property of LDMOS to act as a high-voltage devices in LCD driver ICs, in which it will be protected with an adjusting parameter of SCR device. The process simulator (TSUPRE-4) and device simulator (MEDICI) are used to simulate and evaluate the electrical property of high-voltage power device and to design an ESD protection element in this thesis. Eventually, a suitable trigger voltage and high holding voltage of SCR is used to act as an ESD protector which is very conformable for the request of LCD driver ICs.
Lai, Po-Ching y 賴柏青. "Theoretical Analysis and Measurement for ESD Phenomenon". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/96040789048522761061.
Texto completo國立中山大學
電機工程學系研究所
94
The trends of present design in electronic systems are towards high speed, small size, and lower voltage levels. The noise immunity of high speed digital circuit decreases. ESD problem becomes more and more important for electric products because of the triboelectricity caused by human body with synthetic material. In this thesis we introduce the phenomenon in real life ESD caused by a charged human body source. Then we provide a good measurement method of ESD which enhances the repetition that gives a reliable and accurate result. Finally we try to build the numerical model for the air and contact discharge simulation by FDTD to provide a good measurement validation.
Yeh, Chun-Liang y 葉俊良. "Design and Analysis of ESD Protection Circuit". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74348641225871249510.
Texto completo逢甲大學
電子工程所
93
In this proposal, we would be introducing a biasing circuit, which clamps the gate voltage when threshold reaches the maximum range. On the other hand, we use an N-WELL resistor to increase the resistance between gate and drain to allow ESD current flow to the wide bulk. This can improve the ESD protection level.