Artículos de revistas sobre el tema "Electrical interconnect modeling"
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Dong, Chen, Wei Wang y Maher Rizkalla. "Modeling and Simulation of Carbon Nanotube Interconnect Network". Solid State Phenomena 121-123 (marzo de 2007): 1057–60. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.1057.
Texto completoKumari, B., R. Sharma y M. Sahoo. "Electro-thermal modeling and reliability analysis of Cu–carbon hybrid interconnects for beyond-CMOS computing". Applied Physics Letters 121, n.º 10 (5 de septiembre de 2022): 101901. http://dx.doi.org/10.1063/5.0101329.
Texto completoXu, Yao, Ashok Srivastava y Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance". VLSI Design 2010 (17 de febrero de 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.
Texto completoPoltz, J. "MODELING OF VLSI INTERCONNECT". COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, n.º 1 (enero de 1994): 191–94. http://dx.doi.org/10.1108/eb051872.
Texto completoCarver, Chase, Norman Seastrand y Robert Welte. "PWB Z Interconnect Technology - Electrical Performance". International Symposium on Microelectronics 2014, n.º 1 (1 de octubre de 2014): 000217–21. http://dx.doi.org/10.4071/isom-tp23.
Texto completoHazra, Arnab y Sukumar Basu. "Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review". C 4, n.º 3 (30 de agosto de 2018): 49. http://dx.doi.org/10.3390/c4030049.
Texto completoMyeong-Eun Hwang, Seong-Ook Jung y K. Roy. "Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation". IEEE Transactions on Circuits and Systems I: Regular Papers 56, n.º 7 (julio de 2009): 1428–41. http://dx.doi.org/10.1109/tcsi.2008.2006217.
Texto completoLiao, Weiping y Lei He. "Microarchitecture Level Interconnect Modeling Considering Layout Optimization". Journal of Low Power Electronics 1, n.º 3 (1 de diciembre de 2005): 297–308. http://dx.doi.org/10.1166/jolpe.2005.036.
Texto completoBanan, Behnam, Farhad Shokraneh, Pierre Berini y Odile Liboiron-Ladouceur. "Electrical performance analysis of a CPW capable of transmitting microwave and optical signals". International Journal of Microwave and Wireless Technologies 9, n.º 8 (5 de junio de 2017): 1679–86. http://dx.doi.org/10.1017/s1759078717000575.
Texto completoKurokawa, Atsushi, Takashi Sato, Toshiki Kanamoto y Masanori Hashimoto. "Interconnect Modeling: A Physical Design Perspective". IEEE Transactions on Electron Devices 56, n.º 9 (septiembre de 2009): 1840–51. http://dx.doi.org/10.1109/ted.2009.2026208.
Texto completoYAMADA, K., H. KITAHARA, Y. ASAI, H. SAKAMOTO, N. OKADA, M. YASUDA, N. ODA et al. "Accurate Modeling Method for Cu Interconnect". IEICE Transactions on Electronics E91-C, n.º 6 (1 de junio de 2008): 968–77. http://dx.doi.org/10.1093/ietele/e91-c.6.968.
Texto completoEL-MOURSY, MAGDY A. y HEBA A. SHAWKEY. "INTERCONNECT MODELING WITH THE EXISTENCE OF LINE INDUCTANCE". Journal of Circuits, Systems and Computers 22, n.º 02 (febrero de 2013): 1250082. http://dx.doi.org/10.1142/s021812661250082x.
Texto completoZhang, Yong Hong, Wei Jin y Tao Feng. "Nanometer Interconnect Test Structure for Modeling of Process Variation". Advanced Materials Research 960-961 (junio de 2014): 935–40. http://dx.doi.org/10.4028/www.scientific.net/amr.960-961.935.
Texto completoGuoan Zhong, Cheng-Kok Koh y K. Roy. "On-chip interconnect modeling by wire duplication". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, n.º 11 (noviembre de 2003): 1521–32. http://dx.doi.org/10.1109/tcad.2003.818303.
Texto completoMa, James D. y Rob A. Rutenbar. "Interval-Valued Reduced-Order Statistical Interconnect Modeling". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, n.º 9 (septiembre de 2007): 1602–13. http://dx.doi.org/10.1109/tcad.2007.895577.
Texto completoFarrokhi, Maryam, Rahim Faez, Saeed Haji Nasiri y Bita Davoodi. "Effect of Varying Aspect Ratio on Relative Stability for Graphene Nanoribbon Interconnects". Applied Mechanics and Materials 229-231 (noviembre de 2012): 205–9. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.205.
Texto completoCarloni, Luca P., Andrew B. Kahng, Swamy V. Muddu, Alessandro Pinto, Kambiz Samadi y Puneet Sharma. "Accurate Predictive Interconnect Modeling for System-Level Design". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, n.º 4 (abril de 2010): 679–84. http://dx.doi.org/10.1109/tvlsi.2009.2014772.
Texto completoKhitun, Alexander. "Magnetic Interconnects Based on Composite Multiferroics". Micromachines 13, n.º 11 (17 de noviembre de 2022): 1991. http://dx.doi.org/10.3390/mi13111991.
Texto completoChun, Sunghoon, Yongjoon Kim y Sungho Kang. "MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs". Journal of Electronic Testing 23, n.º 4 (9 de mayo de 2007): 357–62. http://dx.doi.org/10.1007/s10836-006-0630-0.
Texto completoTekleab, Daniel, K. F. Poole, R. Singh, D. L. Carroll y W. R. Harrell. "Modeling early failure in integrated circuit interconnect". Microelectronics Reliability 40, n.º 6 (junio de 2000): 991–96. http://dx.doi.org/10.1016/s0026-2714(99)00339-x.
Texto completoXu, Zhifei, Blaise Ravelo, Olivier Maurice, Sébastien Lalléchère y Fayu Wan. "Kron-Branin modeling of symmetric star tree interconnect". International Journal of Circuit Theory and Applications 47, n.º 3 (15 de octubre de 2018): 391–405. http://dx.doi.org/10.1002/cta.2575.
Texto completoLi, Bing-Jie, Zhen-Song Li, Yan-Ping Zhao, Zheng-Wang Li y Min Miao. "Modeling and Optimization Design of Signal Interconnect Channel Considering Signal Integrity in Three Dimensional Integrated Circuits". Journal of Nanoelectronics and Optoelectronics 16, n.º 5 (1 de mayo de 2021): 773–80. http://dx.doi.org/10.1166/jno.2021.2999.
Texto completoAl-Daloo, Mohammed, Ahmed Soltan y Alex Yakovlev. "Advance Interconnect Circuit Modeling Design Using Fractional-Order Elements". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, n.º 10 (octubre de 2020): 2722–34. http://dx.doi.org/10.1109/tcad.2019.2962779.
Texto completoTravaly, Y., M. Bamal, L. Carbonell, F. Iacopi, M. Stucchi, M. Van Hove y G. P. Beyer. "A novel approach to resistivity and interconnect modeling". Microelectronic Engineering 83, n.º 11-12 (noviembre de 2006): 2417–21. http://dx.doi.org/10.1016/j.mee.2006.10.048.
Texto completoFasig, Jonathan, Gregory Rash, Barbara Randall, Karl Fritz, Steven Currie, Bart McCoy, Paul Riemer, Wendy Wilkins, Barry Gilbert y Erik Daniel. "Interconnect Analysis for 80-Gbps Serial Link Design". Journal of Microelectronics and Electronic Packaging 5, n.º 3 (1 de julio de 2008): 135–39. http://dx.doi.org/10.4071/1551-4897-5.3.135.
Texto completoMi, Ning, Sheldon X. D. Tan y Boyuan Yan. "Multiple block structure-preserving reduced order modeling of interconnect circuits". Integration 42, n.º 2 (febrero de 2009): 158–68. http://dx.doi.org/10.1016/j.vlsi.2008.04.006.
Texto completoIoan, D., G. Ciuprina, M. Radulescu y E. Seebacher. "Compact modeling and fast simulation of on-chip interconnect lines". IEEE Transactions on Magnetics 42, n.º 4 (abril de 2006): 547–50. http://dx.doi.org/10.1109/tmag.2006.871466.
Texto completoXuejue Huang, P. Restle, T. Bucelot, Yu Cao, Tsu-Jae King y Chenming Hu. "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design". IEEE Journal of Solid-State Circuits 38, n.º 3 (marzo de 2003): 457–63. http://dx.doi.org/10.1109/jssc.2002.808313.
Texto completoMa, J. D. y R. A. Rutenbar. "Fast interval-valued statistical modeling of interconnect and effective capacitance". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 4 (abril de 2006): 710–24. http://dx.doi.org/10.1109/tcad.2006.870067.
Texto completoJiang, Lijun, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron y Kaustav Banerjee. "A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures". IEEE Transactions on Advanced Packaging 33, n.º 4 (noviembre de 2010): 777–86. http://dx.doi.org/10.1109/tadvp.2010.2090348.
Texto completoChang, R., Y. Cao y C. J. Spanos. "Modeling the Electrical Effects of Metal Dishing Due to CMP for On-Chip Interconnect Optimization". IEEE Transactions on Electron Devices 51, n.º 10 (octubre de 2004): 1577–83. http://dx.doi.org/10.1109/ted.2004.834898.
Texto completoXia, Lei, Jicheng Meng, Ruimin Xu, Bo Yan y Yunchuan Guo. "Modeling of 3-D Vertical Interconnect Using Support Vector Machine Regression". IEEE Microwave and Wireless Components Letters 16, n.º 12 (diciembre de 2006): 639–41. http://dx.doi.org/10.1109/lmwc.2006.885585.
Texto completoMurugavel, A. K. y N. Ranganathan. "Petri net modeling of gate and interconnect delays for power estimation". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, n.º 5 (octubre de 2003): 921–27. http://dx.doi.org/10.1109/tvlsi.2003.817110.
Texto completoDemeester, Thomas y Daniël De Zutter. "Fields at a Finite Conducting Wedge and Applications in Interconnect Modeling". IEEE Transactions on Microwave Theory and Techniques 58, n.º 8 (agosto de 2010): 2158–65. http://dx.doi.org/10.1109/tmtt.2010.2053061.
Texto completoTANJI, Y. "Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, n.º 9 (1 de septiembre de 2008): 2419–25. http://dx.doi.org/10.1093/ietfec/e91-a.9.2419.
Texto completoZhao, Wei, Xia Li, Sam Gu, Seung H. Kang, Matthew M. Nowak y Yu Cao. "Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect". IEEE Transactions on Electron Devices 56, n.º 9 (septiembre de 2009): 1862–72. http://dx.doi.org/10.1109/ted.2009.2026162.
Texto completoTSENG, W., C. N. J. LIU y C. SU. "Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems". IEICE Transactions on Electronics E89-C, n.º 11 (1 de noviembre de 2006): 1713–18. http://dx.doi.org/10.1093/ietele/e89-c.11.1713.
Texto completoJain, Neeraj, A. K. Aggarwal y P. K. Chaudhary. "Carbon Nanotubes: Good Candidate for VLSI Interconnects". Applied Mechanics and Materials 378 (agosto de 2013): 165–71. http://dx.doi.org/10.4028/www.scientific.net/amm.378.165.
Texto completoElfadel, I. M., A. Deutsch, H. H. Smith, B. J. Rubin y G. V. Kopcsay. "A Multiconductor Transmission Line Methodology for Global On-Chip Interconnect Modeling and Analysis". IEEE Transactions on Advanced Packaging 27, n.º 1 (febrero de 2004): 71–78. http://dx.doi.org/10.1109/tadvp.2004.825478.
Texto completoYan, Zhaowen, Ting Kang, Wei Zhang y Jianwei Wang. "Modeling and Electromagnetic Analysis of Multilayer Through Silicon Via Interconnect for 3D Integration". International Journal of Antennas and Propagation 2015 (2015): 1–14. http://dx.doi.org/10.1155/2015/470952.
Texto completoALAM, MEHBOOB, ARTHUR NIEUWOUDT y YEHIA MASSOUD. "EFFICIENT MULTI-SHIFTED ARNOLDI PROJECTION USING WAVELET TRANSFORM". Journal of Circuits, Systems and Computers 16, n.º 05 (octubre de 2007): 699–709. http://dx.doi.org/10.1142/s0218126607003927.
Texto completoDaugherty, Robin y Dragica Vasileska. "Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (1 de enero de 2017): 1–22. http://dx.doi.org/10.4071/2017dpc-tp3_presentation4.
Texto completoBhopte, Siddharth, Jesse Galloway, Kyung-Rok Park, Hyun-Jin Park, Jeong-Han Choi, Ho-Beob Yu y Sung-Hwan Yang. "Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (1 de enero de 2013): 000441–54. http://dx.doi.org/10.4071/2013dpc-ta22.
Texto completoQinwei Xu y P. Mazumder. "Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, n.º 6 (diciembre de 2003): 1068–79. http://dx.doi.org/10.1109/tvlsi.2003.817522.
Texto completoBuratynski, E. K. "Thermomechanical Modeling of Direct Chip Interconnection Assembly". Journal of Electronic Packaging 115, n.º 4 (1 de diciembre de 1993): 382–91. http://dx.doi.org/10.1115/1.2909347.
Texto completoYu-Lin Shen. "On the Elastic Assumption for Copper Lines in Interconnect Stress Modeling". IEEE Transactions on Device and Materials Reliability 8, n.º 3 (septiembre de 2008): 600–607. http://dx.doi.org/10.1109/tdmr.2008.2002360.
Texto completoTan, Sheldon, Zeyu Sun y Sheriff Sadiqbatcha. "Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip". IPSJ Transactions on System LSI Design Methodology 13 (2020): 42–55. http://dx.doi.org/10.2197/ipsjtsldm.13.42.
Texto completoKacker, K. y S. K. Sitaraman. "Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect". Journal of Microelectromechanical Systems 18, n.º 2 (abril de 2009): 322–31. http://dx.doi.org/10.1109/jmems.2008.2011117.
Texto completoBai, X., R. Chandra, S. Dey y P. V. Srinivas. "Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 8 (agosto de 2004): 1256–63. http://dx.doi.org/10.1109/tcad.2004.831568.
Texto completoHUANG, Z. "Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, n.º 12 (1 de diciembre de 2005): 3367–74. http://dx.doi.org/10.1093/ietfec/e88-a.12.3367.
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