Literatura académica sobre el tema "Electrical interconnect modeling"
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Artículos de revistas sobre el tema "Electrical interconnect modeling"
Dong, Chen, Wei Wang y Maher Rizkalla. "Modeling and Simulation of Carbon Nanotube Interconnect Network". Solid State Phenomena 121-123 (marzo de 2007): 1057–60. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.1057.
Texto completoKumari, B., R. Sharma y M. Sahoo. "Electro-thermal modeling and reliability analysis of Cu–carbon hybrid interconnects for beyond-CMOS computing". Applied Physics Letters 121, n.º 10 (5 de septiembre de 2022): 101901. http://dx.doi.org/10.1063/5.0101329.
Texto completoXu, Yao, Ashok Srivastava y Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance". VLSI Design 2010 (17 de febrero de 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.
Texto completoPoltz, J. "MODELING OF VLSI INTERCONNECT". COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, n.º 1 (enero de 1994): 191–94. http://dx.doi.org/10.1108/eb051872.
Texto completoCarver, Chase, Norman Seastrand y Robert Welte. "PWB Z Interconnect Technology - Electrical Performance". International Symposium on Microelectronics 2014, n.º 1 (1 de octubre de 2014): 000217–21. http://dx.doi.org/10.4071/isom-tp23.
Texto completoHazra, Arnab y Sukumar Basu. "Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review". C 4, n.º 3 (30 de agosto de 2018): 49. http://dx.doi.org/10.3390/c4030049.
Texto completoMyeong-Eun Hwang, Seong-Ook Jung y K. Roy. "Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation". IEEE Transactions on Circuits and Systems I: Regular Papers 56, n.º 7 (julio de 2009): 1428–41. http://dx.doi.org/10.1109/tcsi.2008.2006217.
Texto completoLiao, Weiping y Lei He. "Microarchitecture Level Interconnect Modeling Considering Layout Optimization". Journal of Low Power Electronics 1, n.º 3 (1 de diciembre de 2005): 297–308. http://dx.doi.org/10.1166/jolpe.2005.036.
Texto completoBanan, Behnam, Farhad Shokraneh, Pierre Berini y Odile Liboiron-Ladouceur. "Electrical performance analysis of a CPW capable of transmitting microwave and optical signals". International Journal of Microwave and Wireless Technologies 9, n.º 8 (5 de junio de 2017): 1679–86. http://dx.doi.org/10.1017/s1759078717000575.
Texto completoKurokawa, Atsushi, Takashi Sato, Toshiki Kanamoto y Masanori Hashimoto. "Interconnect Modeling: A Physical Design Perspective". IEEE Transactions on Electron Devices 56, n.º 9 (septiembre de 2009): 1840–51. http://dx.doi.org/10.1109/ted.2009.2026208.
Texto completoTesis sobre el tema "Electrical interconnect modeling"
Kim, Byungsub 1978. "Equalized on-chip interconnect : modeling, analysis, and design". Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58076.
Texto completoCataloged from PDF version of thesis.
Includes bibliographical references (p. 115-118).
This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is demonstrated to search for the optimal link design parameters (wire and circuit) and to generate the optimal performance-power trade-off curve for the equalized interconnects. This thesis also proposes new circuit techniques, which improve the revealed demerits of the conventional circuit topologies. The proposed charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in the conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient nonlinear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10 mm, 2[micro]m pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 2-6 Gb/s/ch.
by Byungsub Kim.
Ph.D.
Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul) 1973. "Interconnect modeling and optimization in deep sub-micron technologies". Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29230.
Texto completoIncludes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.
Vittala, Kavya. "Interconnect Modeling and Lifetime Failure Detection in FPGAs using Delay Faults". University of Toledo / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1404728195.
Texto completoPercey, Andrew K. (Andrew Kenneth). "Analysis and modeling of capacitive coupling along metal interconnect lines". Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/39067.
Texto completoIncludes bibliographical references (leaf 87).
by Andrew K. Percey.
M.Eng.
Kuo, Benjamin S. "Modeling and evaluation of a hierarchical ring interconnect for system-on-chip multiprocessing". Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=81543.
Texto completoChou, Mike Chuan 1969. "Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling". Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46180.
Texto completoIncludes bibliographical references (leaves 131-135).
by Mike Chuan Chou.
Ph.D.
Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms". Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
Texto completoDavid E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
Lee, Laurence H. (Laurence Hongsing). "Modeling and design of superconducting microwave passive devices and interconnects". Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36452.
Texto completoIncludes bibliographical references (p. 157-163).
by Laurence H. Lee.
Ph.D.
Chiun-Shen, Liao. "A network approach for thermo-electrical modelling : from IC interconnects to textile composites". Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/28471.
Texto completoBourduas, Stephan. "Modeling, evaluation, and implementation of ring-based interconnects for network-on-chip". Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19244.
Texto completoCette thèse étudie les propriétés d'une interconnexion hiérarchique composée d'anneaux unidirectionnels. La topologie d'anneaux hiérarchique possède plusieurs caractéristiques souhaitables pour être utilisée comme interconnexion pour réseau-sur-puce (NoC). En premier lieu, la structure unidirectionnelle des anneaux sert à réduire la complexité de routage, ce qui implique une diminution de l'importance des mémoires tampon requises et économise l'énergie consommée par l'interconnexion. En second lieu, les faibles temps de latences et d'horloge système élevé résultent de la simplicité logique de chaque routeur. Finalement, la structure de l'interconnexion facilite une partition où chaque anneau appartient à son propre domaine contrôlé par une horloge individuelle, ce qui rend possible l'application de stratégies dynamiques permettant l'économie d'énergie. L'architecture proposée a été évaluée grâce à des simulations de modèles de hauts niveaux et par une implémentation logique résistance-transistor (RTL). De plus, les anneaux hiérarchiques sont combinés avec l'architecture de maille (« mesh ») bidimensionnelle pour former plusieurs architectures hybrides afin d'améliorer la performance du réseau. La topologie de maille démontre l'augmentation de latences, du nombre de sauts, et de la congestion avec l'agrandissement du réseau. Cependant, les architectures hybrides utilisent les anneaux hiérarchiques pour réduire la congestion au centre du réseau et diminuer le nombre de sauts et les temps de latences associés avec les communications à longue distance. Il en résulte donc une amélioration globale de la performance du système. Les résultats des simulations démontrent que les$
Libros sobre el tema "Electrical interconnect modeling"
Package electrical modeling, thermal modeling, and processing for GaAs wireless applications. Boston: Kluwer Academic, 1999.
Buscar texto completoYazdani, Amirnaser. Voltage-sourced converters in power systems: Modeling, control, and applications. Hoboken, N.J: IEEE Press/John Wiley, 2010.
Buscar texto completoYazdani, Amirnaser. Voltage-sourced converters in power systems: Modeling, control, and applications. Hoboken, N.J: IEEE Press/John Wiley, 2010.
Buscar texto completo1955-, Iravani Reza, ed. Voltage-sourced converters in power systems: Modeling, control, and applications. Hoboken, N.J: Wiley, 2010.
Buscar texto completoZhang, Xiao-Ping. Flexible AC Transmission Systems: Modelling and Control. 2a ed. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012.
Buscar texto completoThomas, Basso, California Energy Commission. Public Interest Energy Research., Northern Power Systems Inc, Virginia Polytechnic Institute and State University. y National Renewable Energy Laboratory (U.S.), eds. Modeling and testing of unbalanced loading and voltage regulation: PIER final project report. [Sacramento, Calif.]: California Energy Commission, 2009.
Buscar texto completoThomas, Basso, California Energy Commission. Public Interest Energy Research., Northern Power Systems Inc, Virginia Polytechnic Institute and State University. y National Renewable Energy Laboratory (U.S.), eds. Modeling and testing of unbalanced loading and voltage regulation: PIER final project report. [Sacramento, Calif.]: California Energy Commission, 2009.
Buscar texto completoFlexible AC Transmission Systems - Modelling and Control. London: Springer, 2012.
Buscar texto completoPal, Bikash, Xiao-Ping Zhang y Christian Rehtanz. Flexible AC Transmission Systems: Modelling and Control (Power Systems). Springer, 2006.
Buscar texto completoPal, Bikash, Xiao-Ping Zhang y Christian Rehtanz. Flexible AC Transmission Systems: Modelling and Control. Springer, 2010.
Buscar texto completoCapítulos de libros sobre el tema "Electrical interconnect modeling"
Moiseev, Konstantin, Avinoam Kolodny y Shmuel Wimer. "Scaling Dependent Electrical Modeling of Interconnects". En Multi-Net Optimization of VLSI Interconnect, 17–34. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-0821-5_3.
Texto completoMaffucci, Antonio, Sergey A. Maksimenko, Giovanni Miano y Gregory Ya Slepyan. "Electrical Conductivity of Carbon Nanotubes: Modeling and Characterization". En Carbon Nanotubes for Interconnects, 101–28. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29746-0_4.
Texto completoGriese, Elmar, Detlef Krabe y Engelbert Strake. "Electrical-Optical Printed Circuit Boards: Technology - Design - Modeling". En Interconnects in VLSI Design, 221–36. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4349-7_18.
Texto completoYi, Guan y Zhao Jiacong. "Reliability Modelling of a Typical Peripheral Component Interconnect (PCI) System with Dynamic Reliability Modelling Diagram". En Lecture Notes in Electrical Engineering, 1569–76. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3648-5_203.
Texto completode Magistris, M., L. De Tommasi, A. Maffucci y G. Miano. "On the Formulation and Lumped Equivalents Extraction Techniques for the Efficient Modeling of Long Interconnects". En Scientific Computing in Electrical Engineering, 81–86. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/978-3-540-32862-9_12.
Texto completoQi, Xiaoning, Sherry Y. Shen, Ze-Kai Hsiau, Zhiping Yu y Robert Dutton. "Layout-Based 3D Solid Modeling of IC Structures and Interconnects Including Electrical Parameter Extraction". En Simulation of Semiconductor Processes and Devices 1998, 61–64. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_18.
Texto completoNakhla, Michel y Ramachandra Achar. "Interconnect Modeling and Simulation". En Electrical Engineering Handbook. CRC Press, 1999. http://dx.doi.org/10.1201/9781420049671.ch17.
Texto completoYoussef, Nadir, Belahrach Hassan, Ghammaz Abdelilah, Naamane Aze-eddine y Radouani Mohammed. "Electrical Transport Modeling of Graphene-Based Interconnects". En Carbon Nanotubes - Recent Advances, New Perspectives and Potential Applications [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.105456.
Texto completoLiberty, Stanley R. "Modeling Interconnected Systems: A Functional Perspective". En The Electrical Engineering Handbook, 1079–84. Elsevier, 2005. http://dx.doi.org/10.1016/b978-012170960-0/50084-0.
Texto completo"Macromodeling of Complex Interconnects in 3D Integration". En Electrical Modeling and Design for 3D System Integration, 16–96. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118166727.ch2.
Texto completoActas de conferencias sobre el tema "Electrical interconnect modeling"
Nosrati, Nooshin, Katayoon Basharkhah, Rezgar Sadeghi y Zainalabedin Navabi. "An ESL Environment for Modeling Electrical Interconnect Faults". En 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2019. http://dx.doi.org/10.1109/isvlsi.2019.00024.
Texto completoVinson, J. E. "Aluminum Interconnect Response to Electrical Overstress". En ISTFA 1998. ASM International, 1998. http://dx.doi.org/10.31399/asm.cp.istfa1998p0203.
Texto completoChen, Xiaohe, James Drewniak, Jianmin Zhang, Michael Cracraft, Bruce Archambeault y Samuel Connor. "Large Scale Signal and Interconnect FDTD Modeling for BGA Package". En 2006 IEEE Electrical Performane of Electronic Packaging. IEEE, 2006. http://dx.doi.org/10.1109/epep.2006.321160.
Texto completoCadix, L., M. Rousseau, C. Fuchs, P. Leduc, A. Thuaire, R. El Farhane, H. Chaabouni et al. "Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs". En 2010 IEEE International Interconnect Technology Conference - IITC. IEEE, 2010. http://dx.doi.org/10.1109/iitc.2010.5510728.
Texto completoBeyene, Wendemagegnehu. "Modeling and Analysis Techniques of Jitter Enhancement Across High-Speed Interconnect Systems". En 2007 IEEE Electrical Performance of Electronic Packaging. IEEE, 2007. http://dx.doi.org/10.1109/epep.2007.4387115.
Texto completoBarker, Donald B., Brent M. Mager y Michael D. Osterman. "Analytic Characterization of Area Array Interconnect Shear Force Behavior". En ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-39494.
Texto completoChen, Wen Jie y Mei Song Tong. "Electromagnetic modeling for lossy interconnect structures based on hybrid surface integral equations". En 2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS). IEEE, 2016. http://dx.doi.org/10.1109/edaps.2016.7893154.
Texto completoBekmambetova, Fadime, Xinyue Zhang y Piero Triverio. "A passivity approach to FDTD stability with application to interconnect modeling". En 2016 IEEE 25th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2016. http://dx.doi.org/10.1109/epeps.2016.7835451.
Texto completoNaik, Bhattu HariPrasad, Md Misbahuddin y Chandra Sekhar Paidimarry. "S-Parameter Modeling and Analysis of RGLC Interconnect for Signal Integrity". En 2017 International Conference on Recent Trends in Electrical, Electronics and Computing Technologies (ICRTEECT). IEEE, 2017. http://dx.doi.org/10.1109/icrteect.2017.41.
Texto completoBosman, Dries, Martijn Huynen, Daniel De Zutter, Xiao Sun, Nicolas Pantano, Geert Van der Plas, Eric Beyne y Dries Vande Ginste. "Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method". En 2022 IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). IEEE, 2022. http://dx.doi.org/10.1109/epeps53828.2022.9947108.
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