Bibliografías temáticas / Effacement bit à bit

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Literatura académica sobre el tema "Effacement bit à bit"

Autor: Grafiati
Publicado: 25 de mayo de 2024

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Artículos de revistas sobre el tema "Effacement bit à bit"

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Jacks, Philip J. "The Composition of Giorgio Vasari'sRicordanze: Evidence from an Unknown Draft". Renaissance Quarterly 45, n.º 4 (1992): 739–84. http://dx.doi.org/10.2307/2862635.

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The fame of Giorgio Vasari'sVite de’ eccellcnti pittori satltori ed architettori,both as a masterpiece of Italian literature and the model of modern biography, has perhaps slighted our awareness of the degree to which this author was also a publicist of his own artistic persona. Actually the documentation Vasari left of his professional and domestic affairs is probably more copious than the research he compiled for the lives of his fellow artists. Yet Vasari must have come to the idea of an autobiography relatively late in life. At the end of the second edition of theVitepublished in 1568, he devoted “alcune cose degli artefici della nostra Accademia di Firenze,” followed by a “descrizione” of his own career up to the present. Rather than an expression of self-effacement, here the distinction between description and biography seems to be a question of genre. Why Vasari found the scheme of thevitasuitable for some contemporaries and not for others is difficult to explain. As for his own life, the prospect of writing the definitive version at this stage no doubt would have seemed a bit premature.
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Thompson, Seth. "Bit by Bit". Afterimage 33, n.º 3 (noviembre de 2005): 43–44. http://dx.doi.org/10.1525/aft.2005.33.3.43.

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Jaye, Nathan. "Bit by Bit". CFA Institute Magazine 25, n.º 2 (marzo de 2014): 34–37. http://dx.doi.org/10.2469/cfm.v25.n2.11.

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Valantin, Robert y David Balson. "Bit by Bit". Media Asia 14, n.º 1 (enero de 1987): 19–20. http://dx.doi.org/10.1080/01296612.1987.11727009.

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Carnie, Jamie. "Bit by bit". New Scientist 218, n.º 2923 (junio de 2013): 31. http://dx.doi.org/10.1016/s0262-4079(13)61618-8.

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Humphreys, Olivia. "Mourning Bit by Bit". British Journal of Psychotherapy 35, n.º 1 (29 de enero de 2019): 127–30. http://dx.doi.org/10.1111/bjp.12439.

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Cave, Richard C. "Graphing, Bit by Bit". Mathematics Teacher 88, n.º 5 (mayo de 1995): 372–431. http://dx.doi.org/10.5951/mt.88.5.0372.

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One topic area where technology can have an immediate impact in the mathematics classroom is graphing. Because of a variety of readily available software packages, graphs have become a universal method of representing mathematical relationships. From the charts in USA Today to the many diagrams of Ross Perot, the general public sees more graphs than ever before, and they need to have a better understanding of what graphs really represent. In the past, a graph could only be created by hand; therefore, most curricula emphasized the actual graphing of equations. With the help of technology, teachers can now concentrate on teaching students how to investigate what the graphs represent as well as how to interpret the graphs.
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Lucky, R. W. "A bit is a bit is a bit? [Reflections]". IEEE Spectrum 31, n.º 7 (julio de 1994): 15. http://dx.doi.org/10.1109/6.294930.

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Lyngstad, Torkild Hovde. "Matthew Salganik: Bit by bit". Norsk sosiologisk tidsskrift 3, n.º 03 (3 de junio de 2019): 231–34. http://dx.doi.org/10.18261/issn.2535-2512-2019-03-06.

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Georgescu, Iulia. "A bit on the bit". Nature Physics 12, n.º 9 (septiembre de 2016): 888. http://dx.doi.org/10.1038/nphys3878.

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Tesis sobre el tema "Effacement bit à bit"

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Knight, Michael K. "Bit by bit". Claremont Graduate University, 2010. http://ccdl.libraries.claremont.edu/u?/stc,82.

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Melul, Franck. "Développement d'une nouvelle génération de point mémoire de type EEPROM pour les applications à forte densité d'intégration". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0266.

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L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle architecture mémoire a été proposée : la cellule BitErasable. Elle a montré une excellente fiabilité et a permis d’apporter des éléments de compréhension sur les mécanismes de dégradation présents dans ces dispositifs mémoires à transistor de sélection enterré. Cette nouvelle architecture offre de plus la possibilité d’effacer les cellules d’un plan mémoire de façon individuelle : bit à bit. Conscient du grand intérêt que présente l’effacement bit à bit, un nouveau mécanisme d’effacement pour injection de trous chauds a été proposé pour la cellule eSTM. Il a montré des performances et un niveau de fiabilité parfaitement compatible avec les exigences industrielles des applications Flash-NOR
The objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications
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Malm, Martin. "Beckholmen bit för bit". Thesis, KTH, Arkitektur, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-150351.

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På Beckholmen ligger stockholmsregionens enda aktiva reparationsvarv med kapacitet att ta emot såväl större fartyg samt skärgårdstrafikens fartyg. För att kunna bedriva verksamheten på ett säkert och miljövänligt sätt krävs infrastrukturella investeringar i form av byggnader och anläggningar. Stockholms stad har påbörjat ett programarbete och  presenterat ett förslag till detaljplan som möjliggör dessa investeringar.  Då det handlar om stora investeringar och förändringar i stadsbilden är den nya detaljplanen ett känsligt projekt, särskilt om varvsverksamheten skulle hamna i ekonomiska svårigheter. I det förslag till detaljplan som presenterats hösten 2012 har varsverksamhetens funktioner lagts inom en och samma byggnadsvolym, som till en följd blir väldigt stor.   Frågeställningen i ”Beckholmen bit för bit” är om en detaljplan som låter verksamheten växa mer inkrementellt fördelat på fler byggnader kan göra projektet mer flexibelt.   Efter studier av varvsverksamhetens program samt volym och planstudier, blir slutsatsen att det finns fördelar med att fördela varvsfunktionerna på fler byggnadsvolymer. Särskilt om byggnaderna gestaltas på ett sätt så att kompositionen är öppen för förändring. Ett förslag på en gestaltning som uppfyller dessa egenskaper presenteras även.
The only active shipyard in the Stockholm region  with capacity for large ships and the archipelago fleet is situated at Beckholmen. Large investments in infrastructure and buildings are needed in order to secure the enviroment and worker safety. The city has presented a proposal for new planning enabeling these investments. As the investment are large and the site is sensitive the project has many potential risks, especially if the shipyard should encounter economic difficulties in the future. In the citys planning proposal presented in 2012 the whole program for the shipyard is contained within one single volume.   The question at issue in ”Beckholmen bit by bit” thus is if planning that splits the program into separate buildings and permits incremental growth is prefarable.   After program studies, volume and plan studies the conclusion is that there are many advantages with planning that encourages incremental growth of the shipyard at Beckholmen, especially if the building design is open to change from the beginning. A proposal of a planning and design fulfilling these qualities is also presented.
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Hoesel, Stan van. "De constructie van de informatiesnelweg "bit by bit" /". [Maastricht : Maastricht : Universiteit Maastricht] ; University Library, Maastricht University [Host], 2001. http://arno.unimaas.nl/show.cgi?fid=13064.

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Karaer, Arzu. "Optimum bit-by-bit power allocation for minimum distortion transmission". Texas A&M University, 2005. http://hdl.handle.net/1969.1/4760.

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In this thesis, bit-by-bit power allocation in order to minimize mean-squared error (MSE) distortion of a basic communication system is studied. This communication system consists of a quantizer. There may or may not be a channel encoder and a Binary Phase Shift Keying (BPSK) modulator. In the quantizer, natural binary mapping is made. First, the case where there is no channel coding is considered. In the uncoded case, hard decision decoding is done at the receiver. It is seen that errors that occur in the more significant information bits contribute more to the distortion than less significant bits. For the uncoded case, the optimum power profile for each bit is determined analytically and through computer-based optimization methods like differential evolution. For low signal-to-noise ratio (SNR), the less significant bits are allocated negligible power compared to the more significant bits. For high SNRs, it is seen that the optimum bit-by-bit power allocation gives constant MSE gain in dB over the uniform power allocation. Second, the coded case is considered. Linear block codes like (3,2), (4,3) and (5,4) single parity check codes and (7,4) Hamming codes are used and soft-decision decoding is done at the receiver. Approximate expressions for the MSE are considered in order to find a near-optimum power profile for the coded case. The optimization is done through a computer-based optimization method (differential evolution). For a simple code like (7,4) Hamming code simulations show that up to 3 dB MSE gain can be obtained by changing the power allocation on the information and parity bits. A systematic method to find the power profile for linear block codes is also introduced given the knowledge of input-output weight enumerating function of the code. The information bits have the same power, and parity bits have the same power, and the two power levels can be different.
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Sandvik, Jørgen Moe. "En variabel bit lengde 9-bit 50MS/S SAR ADC". Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-20654.

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A 9-bit 50MS/s SAR ADC with a simulated power consumption of 24.5 µW was designed for this thesis. Specifications were made for application with in-probe electronic as part of an ultrasound system. A novel switching-scheme - employing variable bit length encoding – was introduced in order to simplify successive approximation. Pre-layout results reported a FoM of just 1.37 fJ/conversion step, which is favorable to all published designs to date. Recent technology advancements has seen the ultrasound field expanding into handheld markets [33]. More power efficient solutions, in addition to existing enhanced resolution 3-D technology both place strict requirements for analog/mixed-signal design. Composite electronics within the probe casing - allowing close-to-source signal processing - is believed to be the future of ultrasound devices. ADC designs suitable for in-probe technology require ultra low power and noise characteristics towards supporting multiple channels on a single SoC. Excellent performance of recent SAR ADCs make them a viable alternative for in-probe technology [2,7,12,4]. Work in this thesis show the flexibility of the SAR algorithm. The relatively simple implementation/decoding of the VBL approach, complimented by the accuracy dependency of the level detection range makes the ADC reconfigurable by digital signal processing. Recent published design has reported relatively low power consumption for the comparator [15,7]. A motivation for the thesis was to see whether multiple operated comparators could reduce power in remaining circuitry. Implementation of a level-detector - supporting the VBL switching-scheme - has lead to improvements in: Power efficiency, speed and metastability-induced errors. The device consists of two comparators operated in parallel, with a relative DC-offset generated by difference in the capacitive load. Decision points of the comparators shift with DC-offset, and are atoned for a range desired by the modified SAR algorithm. An extensive literary search of recent methodologies and results was conducted, and a summery presenting state-of-the-art designs is included with the work. An approach using no external references where chosen as a basis for the DAC design. Emphasize was made on constant common-mode voltage suitably for comparator design eliminating pre-amplifiers or buffers. Digital logic consisting of serial connected bitslices using a novel differential approach is proposed. Level detector outputs are connected to the digital logic switching only a portion of transistors in the bitslice during conversion. Trade-off between switching activity and circuit area proves effective, with only 12.5% of overall power consumed in the digital part. Power simulations reported the level-detector as the dominant source of consumption, thereby being subject to further optimization with regards to power. Nonetheless a proof-of-concept 8-bit ADC implementation - operated with the novel switching-scheme - produced 8.96 ENOB while dissipating less power.
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James, Calvin L. "ENHANCE BIT SYNCHRONIZER BIT ERROR PERFORMANCE WITH A SINGLE ROM". International Foundation for Telemetering, 1990. http://hdl.handle.net/10150/613417.

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International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, Nevada
Although prefiltering prevents the aliasing phenomenon with discrete signal processing, degradation in bit error performance results even when the prefilter implementation is ideal. Degradation occurs when decisions are based on statistics derived from correlated samples, processed by a sample mean estimator. i.e., a discrete linear filter. However, an orthonormal transformation can be employed to eliminate prefiltered sample statistical dependencies, thus permitting the sample mean estimator to provide near optimum performance. This paper will present mathematical justification for elements which adversely affect the bit synchronizer’s decision process and suggest an orthonormal transform alternative. The suggested transform can be implemented in most digital bit synchronizer designs with the addition of a Read Only Memory (ROM).
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Fontana, Giulia <1993&gt. "BIT or no BIT? La tutela degli investimenti italiani all’estero". Master's Degree Thesis, Università Ca' Foscari Venezia, 2018. http://hdl.handle.net/10579/12317.

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Gli accordi bilaterali per la promozione e protezione degli investimenti esteri sono stati, dall'inizio del XX secolo,oggetto di una grande attenzione da parte di tutti coloro i quali volessero espandere i propri orizzonti commerciali al di fuori dei confini nazionali di appartenenza. Nel presente lavoro di tesi si intende innanzitutto dare una visione d’insieme (fare una panoramica) sul processo storico che ha portato gli Stati a stipulare questi accordi, sul perfezionamento del diritto commerciale internazionale in materia di investimenti e sui cambiamenti che ha apportato l’entrata in vigore del trattato di Lisbona e l’inzio della competenza esclusiva dell’Unione Europea in tale materia. Verrà in seguito analizzato un accordo bilaterale in tutte le sue parti e infine verranno esaminate due controversie, dal quale confronto si rifletterà sulla rilevanza degli accordi bilaterali in materia di tutela degli investimenti italiani all’estero.
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Segars, Tara. "8-Bit Hunger". Kent State University / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=kent1619176909244462.

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Näslund, Mats. "Bit extraction, hard-core predicates and the bit security of RSA". Doctoral thesis, KTH, Numerical Analysis and Computer Science, NADA, 1998. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2687.

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Libros sobre el tema "Effacement bit à bit"

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Kammer, Manfred. Bit um Bit. Stuttgart: J.B. Metzler, 1997. http://dx.doi.org/10.1007/978-3-476-03996-5.

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Sanfield, Steve. Bit by bit. New York: Philomel Books, 1995.

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Arnold, Virginia A. Bit by bit. New York: Macmillan Pub. Co., 1987.

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Leonard, Stock Lois, ed. Bit by bit. New York: Macmillan/McGraw-Hill School Publishing Company, 1993.

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Kalicharan, Noel. Julia - Bit by Bit. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-73936-2.

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Creasey, D. J. Progress bit by bit. Birmingham: University of Birmingham, 1988.

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Hayes, Leatha B. Blossom bit by bit. Flushing, MI: Autarkee Press, 1998.

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Omland, Ib. Arkitektur--bit for bit. [Oslo]: Kolofon Forlag, 2021.

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1949-, Cave John, Technology Enhancement Programme y Engineering Council, eds. TEP bit by bit controller. London: Engineering Council, 1995.

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Hiroyuki, Tango, ed. Mega-bit memory technology: From mega-bit to giga-bit. Amsterdam: Gordon and Breach, 1998.

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Capítulos de libros sobre el tema "Effacement bit à bit"

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Kammer, Manfred. "Einleitung". En Bit um Bit, 1–7. Stuttgart: J.B. Metzler, 1997. http://dx.doi.org/10.1007/978-3-476-03996-5_1.

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Kammer, Manfred. "Materialsammlung und -ordnung". En Bit um Bit, 8–23. Stuttgart: J.B. Metzler, 1997. http://dx.doi.org/10.1007/978-3-476-03996-5_2.

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Kammer, Manfred. "Die Gestaltung des Manuskripts". En Bit um Bit, 24–104. Stuttgart: J.B. Metzler, 1997. http://dx.doi.org/10.1007/978-3-476-03996-5_3.

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Kammer, Manfred. "Hilfen bei der Erstellung von Manuskripten". En Bit um Bit, 105–28. Stuttgart: J.B. Metzler, 1997. http://dx.doi.org/10.1007/978-3-476-03996-5_4.

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Kammer, Manfred. "Elektronische Suchhilfen". En Bit um Bit, 129–43. Stuttgart: J.B. Metzler, 1997. http://dx.doi.org/10.1007/978-3-476-03996-5_5.

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Akins, Kathleen y Martin Hahn. "Colour bit-by-bit". En Conscious and Unconscious Mentality, 274–310. London: Routledge, 2023. http://dx.doi.org/10.4324/9781003409526-19.

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Weik, Martin H. "bit". En Computer Science and Communications Dictionary, 124. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1595.

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Weik, Martin H. "bit-by-bit asynchronous operation". En Computer Science and Communications Dictionary, 125. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1596.

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Kroening, Daniel y Ofer Strichman. "Bit Vectors". En Decision Procedures, 135–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2016. http://dx.doi.org/10.1007/978-3-662-50497-0_6.

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Van Hoey, Jo. "Bit Operations". En Beginning x64 Assembly Programming, 133–45. Berkeley, CA: Apress, 2019. http://dx.doi.org/10.1007/978-1-4842-5076-1_16.

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Actas de conferencias sobre el tema "Effacement bit à bit"

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Cho, Christopher J. y Timothy J. Norman. "Bit by bit". En ICAIF'21: 2nd ACM International Conference on AI in Finance. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3490354.3494380.

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Chen, Junwei, Yangbo Zhang, Xiao Kang y Huaying Shu. "Bit and Bit Product Thinking". En 2013 International Conference on Advanced Computer Science and Electronics Information. Paris, France: Atlantis Press, 2013. http://dx.doi.org/10.2991/icacsei.2013.170.

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Fryklund, Bob. "Changing the Game Bit by Bit". En Offshore Technology Conference. Offshore Technology Conference, 2010. http://dx.doi.org/10.4043/21076-ms.

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Liu, Bo, Yuhao Sun y Bo Liu. "Translational Bit-by-Bit Multi-bit Quantization for CRNN on Keyword Spotting". En 2019 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC). IEEE, 2019. http://dx.doi.org/10.1109/cyberc.2019.00082.

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Tang, Guang-Ming, Kazuyoshi Takagi y Naofumi Takagi. "A 4-Bit Bit-Slice Multiplier for a 32-Bit RSFQ Microprocessor". En 2015 15th International Superconductive Electronics Conference (ISEC). IEEE, 2015. http://dx.doi.org/10.1109/isec.2015.7383428.

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Wells, Michael, Tim Marvel y Chad Beuershausen. "Bit Balling Mitigation in PDC Bit Design". En IADC/SPE Asia Pacific Drilling Technology Conference and Exhibition. Society of Petroleum Engineers, 2008. http://dx.doi.org/10.2118/114673-ms.

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Ulichney, Robert A. y Shiufun Cheung. "Pixel bit-depth increase by bit replication". En Photonics West '98 Electronic Imaging, editado por Giordano B. Beretta y Reiner Eschbach. SPIE, 1998. http://dx.doi.org/10.1117/12.298285.

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Macini, Paolo, Matteo Magagni y Pietro Valente. "Drill-Bit Catalog and Bit Index: a New Method for Bit Performance Evaluation". En SPE Latin American and Caribbean Petroleum Engineering Conference. Society of Petroleum Engineers, 2005. http://dx.doi.org/10.2118/94798-ms.

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Lo, Yun-Chen y Ren-Shuo Liu. "Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference". En 2023 60th ACM/IEEE Design Automation Conference (DAC). IEEE, 2023. http://dx.doi.org/10.1109/dac56929.2023.10247749.

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Matsumoto, Takashi, Tony Dunnigan y Maribeth Back. "Post-bit". En the 13th annual ACM international conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1101149.1101197.

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Informes sobre el tema "Effacement bit à bit"

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Stokke, Knut Bjørn y Eli Havnen. "Bit for bit" utbygging i kystsonen. Oslo: By- og regionforskningsinstituttet NIBR, 2009. http://dx.doi.org/10.7577/nibr/samarbeidsrapport/2009/1.

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Herrero Gutiérrez, FJ. Del verbo al bit. Revista Latina de Comunicación Social, diciembre de 2016. http://dx.doi.org/10.4185/cac115.

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Herrero Gutiérrez, FJ y C. Mateos Martín. Del verbo al bit. Revista Latina de Comunicación Social, diciembre de 2016. http://dx.doi.org/10.4185/cac116.

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Thomson, M. Greasing the QUIC Bit. RFC Editor, agosto de 2022. http://dx.doi.org/10.17487/rfc9287.

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Katagi, M. y S. Moriai. The 128-Bit Blockcipher CLEFIA. RFC Editor, marzo de 2011. http://dx.doi.org/10.17487/rfc6114.

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Muley, P. y M. Aissaoui, eds. Pseudowire Preferential Forwarding Status Bit. RFC Editor, febrero de 2013. http://dx.doi.org/10.17487/rfc6870.

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Bergman, O. y C. B. Thorn. String bit models for superstring. Office of Scientific and Technical Information (OSTI), diciembre de 1995. http://dx.doi.org/10.2172/179289.

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Mumm, R. H. y S. A. Parker. BMD/ADA Bit-Oriented Message Definer: A Tool to Define Bit-Oriented Messages in Ada. Fort Belvoir, VA: Defense Technical Information Center, diciembre de 1990. http://dx.doi.org/10.21236/ada233576.

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Herrero Gutiérrez, FJ, C. Mateos Martín, S. Toledano Buendía, A. Ardèvol Abreu y M. Trenta. Del verbo al bit. Segunda edición. Revista Latina de Comunicación Social, febrero de 2017. http://dx.doi.org/10.4185/cac116edicion2.

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Andersen, S., A. Duric, H. Astrom, R. Hagen, W. Kleijn y J. Linden. Internet Low Bit Rate Codec (iLBC). RFC Editor, diciembre de 2004. http://dx.doi.org/10.17487/rfc3951.

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