Tesis sobre el tema "EBCOT"
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Kordik, Andrew Michael. "Hardware Implementation of Post-Compression Rate-Distortion Optimization for EBCOT in JPEG2000". University of Dayton / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1313791202.
Texto completoDamecharla, Hima Bindu. "FPGA IMPLEMENTATION OF A PARALLEL EBCOT TIER-1 ENCODER THAT PRESERVES ENCODING EFFICIENCY". University of Akron / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=akron1149703842.
Texto completoVarma, Krishnaraj M. "Fast Split Arithmetic Encoder Architectures and Perceptual Coding Methods for Enhanced JPEG2000 Performance". Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/26519.
Texto completoPh. D.
Lucking, David Joseph. "FPGA Implementation of the JPEG2000 MQ Decoder". University of Dayton / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1272050082.
Texto completoBradáč, Václav. "Komprese obrazu pomocí vlnkové transformace". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363886.
Texto completoLeung, Raymond Electrical Engineering & Telecommunications Faculty of Engineering UNSW. "Scalable video compression with optimized visual performance and random accessibility". Awarded by:University of New South Wales. Electrical Engineering and Telecommunications, 2006. http://handle.unsw.edu.au/1959.4/24192.
Texto completoUrbánek, Pavel. "Komprese obrazu pomocí vlnkové transformace". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236385.
Texto completoSchirmer, Anke [Verfasser]. "Einfluss einer hoch dosierten Simvastatin-Therapie auf den Progress einer koronaren Herzkrankheit gemessen als Zunahme des Calcium-Scores mittels EBCT bei Patienten mit Diabetes mellitus Typ 2 / Anke Schirmer". Berlin : Medizinische Fakultät Charité - Universitätsmedizin Berlin, 2010. http://d-nb.info/1024006263/34.
Texto completoBäckström, Nilsson Wilma. "Carbon Filters for Drinking Water Treatment – How Flow Rate and Empty Bed Contact Time Influence the Performance". Thesis, KTH, Kemiteknik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-298356.
Texto completoDrinking water is an essential part of a sustainable society. In the future, the demand for drinking water will increase and contaminants in the water sources are also predicted to increase. Therefore, it is essential to ensure safe drinking water through functioning drinking water treatment plants (DWTPs). One important contaminant to treat is natural organic matter (NOM), which is harmless in itself but can produce harmful products. One technique to use for treating NOM is carbon filters (CFs). The effect of increased flow rate and increased empty bed contact time (EBCT) on the CF efficiency was investigated at a DWTP. The investigated parameters were particles, ultraviolet absorbance at 254 nm, turbidity, conductivity, cultivable microorganisms, fluorescent dissolved organic matter, total organic carbon, chemical oxygen demand, and odour. Three CFs were studied at different flow rates; 190, 220, 250, and 280 L/s for 24 hours each. Additionally, two filters had increased EBCT of 60 and 76 %, while one filter continued with the regular flow rate of 190 L/s for six weeks. Outgoing water from the filters was analysed to see if the change had any effect on the DWTP. This preliminary study did not find any significant effect on the CF treatment caused by increased flow rate or EBCT. This could be an indication that the CFs can handle a future increase in flow rate and thus be an essential part of a future expansion of the DWTP. The indications of CFs being affected by the increase in flow rates for some of the parameters could be explained by fluctuations in incoming water or differences between the separate filters. In the future, a more thorough analysis of both incoming and outgoing water to the CFs should be done, where sampling occurs more frequently to better understand the fluctuations in incoming contaminant concentrations. The measurements should also be repeated to see how the treatment differs from day to day. How the CFs handle increased flow rates over longer time periods should also be investigated further.
林建佑. "High Performance EBCOT Design of JPEG2000". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/55262093547634266659.
Texto completo國立清華大學
資訊工程學系
90
The current state of JPEG 2000 Part 1 is an international standard. Although it provides unprecedented features not available in other standards, lots of the technical bottlenecks are still unsolved in its image processing algorithms, especially in the novel embedded block encoding operations. In this thesis, bit-level we propose a new architecture for ECBOT. The architecture can perform parallel processing coding to increase the throughput of context formation. Column skipping can skip columns which have four no-operation bits. In addition, in the memory structure, we separate data and allocate into 9 memories. In the arithmetic encoder, a 4-stage pipeline is used to reduce the clock cycle time. Besides, a data-forward technique is used in 4-stage pipeline architecture to process two identical contexts continuously inputted. The proposed architecture is shown to have high throughput. We have average 22% improvement in throughput by comparing [2]. It needs 0.385 second to encode an image with 2400x1800 image size. This design can support further applications such as Motion-JPEG2000.
CHYAN, CHUN-AN y 簡崇安. "Design and Implementation of JPEG2000 EBCOT coder". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/44684953777007916715.
Texto completo國立臺灣大學
電機工程學研究所
90
JPEG2000 system is the newest standard for still image compression. In this Thesis, we discuss the basic architecture of JPEG2000 system, which could be viewed as an evolution of image compression techniques during recent years. However, the key component, which is called “EBCOT,” contains many bit-level computation and multiple scan, it makes JPEG2000 too slow to fit some applications if we use general purpose CPU to execute JPEG2000. We design and implement an ASIC to accrete EBCOT, the cycles needed are reduced to about 45% of the original algorithm, and the clock rate can reach 133MHz in our simulation.
Wang, Sung-Yang y 王崧仰. "VLSI Design and Implementation of EBCOT CODEC". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/75152495408474280806.
Texto completo國立中山大學
資訊工程學系研究所
89
This thesis proposes several hardware implementation approaches for the EBCOT (Embedded Block Coding with Optimized Truncation) algorithm, one of the key operations in the emerging JPEG 2000 standard. We also modify the EBCOT algorithm in order to reduce the memory requirement and to improve the speed performance. The modified EBCOT encoder saves 40% memory area with triple speed performance compared to the original design.
cheng, tain-zuo y 陳天佐. "Analysis of High Performance and Low Cost EBCOT". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/09075827833262721922.
Texto completo國立中正大學
電機工程所
94
In the thesis, we propose a new EBCOT-tier1 encoder architecture,which includes two parts:1)Constant output rate CF,2)Input interleaving AE . we can speed up the operation frequency of AE-the bottleneck of EBCOT-tier1 encoder , and can improve the performance of EBCOT-tier1 encoder . Our proposed EBCOT-tier1 encoder employs one encoder so we can achieve much more area saving and maintain good performance in comparison with those encoders presented in related high performance works . 93.1M samples/sec can be realized by using two independent constant-output rate CFs operating at 200MHz and one input-interleaving AE operating at 400MHz.
Huang, Fong-Wei y 黃奉偉. "The VLSI Design of Parallel-passing predict EBCOT". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/15578696679962549095.
Texto completo中華技術學院
電子工程研究所碩士班
97
Abstract In the JPEG2000 coding system, the most important two elements are bit-plane coding and arithmetic coding. Among them, the bottleneck of the system is EBCOT tire-1 text generator (Context Formation) due to the complexity of encoding operations. Therefore, this paper focuses on the implementation and discussion of the text generator hardware architecture design. In order to speed up the operations within the text of the speed of generator, we apply parallel programming (Parallel Pass Predict) method as the basis to realize the entire IC design. When conducting the parallel programming part of the procedure, we can perform all the bits of the expected action procedures to a column at once, and in the coding procedure, each clock cycle can produce a Context (CX) and Decision (D) value. This structure which has now been compared to other encoding architectures,each bit plane is scanned three times can save three times the encoding time in order to achieve fast code performance. In arithmetic coding, it is reduced to the best design of the clock. Finally, we design it in Verilog HDL code, and Synopsys Design Compiler Tools for logic synthesis. With the Synopsys Astro Layout Tools and the TSMC 0.18 ㎛ process technology, the chip is automatically synthesized. After comparing the pre-synthesis simulation (simulated in FPGA) and the post-synthesis simulation, the same results were found, which confirmed that the design is a correct and feasible framework. Key Word:Cell_based,EBCOT,FPGA, Aarithmetic code
Chang, Chung-Hau y 張駿浩. "The High Throughput Rate EBCOT Architecture for JPEG2000". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/84830681742266930434.
Texto completo淡江大學
電機工程學系
92
In recent years, the development of communication and multimedia are more and more popular, therefore a variety of digital media is around our modern life such as digital image, VCD, DVD, and music CD. But the storage of these information is always large. It might be too large to transmit or store directly without processing. The technic of compression is getting important nowadays. In this thesis, we discuss the algorithm and the hardware design of still image compression. JPEG2000 is the newest standard for still image compression. The low-bit rate compression of this standard is better than JPEG, and it also provides many new useful function such as loosy and lossless compression, progression by resolution and quality, region of interest encoding and good error resilience. However, JPEG2000 needs more complicated computation than JPEG, especially the algorithm of EBCOT in the encoding flow. In EBCOT block coder, a fractional bit-plane coding method is adopted. Every bit-plane is encoded by three procedure. Due to this reason, this part occupies most of the encoding time. Therefore it must be implemented by ASIC design to promote the real time computation. As mention before, the object of this thesis is to design a high performance hardware architecture for EBCOT coding algorithm. There are one context-modeling and one arithmetic encoder in our design. For context-modeling, we merge the three coding passes of fractional bit-plane into a single pass to reduce the encoding time. In order to increase the throughput rate further, we also proposed a parallel coding architecture to encode two samples currently. The experimental result shows the execution time is reduced by more than 25% compared with the architecture without parallel design. For the interleaved data produced by the context-modeling, we proposed a low hardware cost arithmetic encoder and divide it into four stage. Simulation results show that the maximum operation frequency is 180Mz. The proposed VLSI architectures are described in Verilog HDL, and synthesized by the Synopsys Design Compiler. Finally, the layout of the design is generated automatically by Avant! Apollo Layout Tools in a 0.35μm 1P4M CMOS technology.
Chen, Kuan-Fu y 陳冠夫. "EFFICIENT ARCHITECTURE DESIGN OF EBCOT FOR JPEG-2000". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/76214593485370109133.
Texto completo國立臺灣大學
電機工程學研究所
89
As the rapid increase of Internet demanding and the use of digital still camera (DSC), still image is broadly used as a storage and transmission media. JPEG-2000 is a new still image compression standard. It has better compression performance than conventional JPEG standard, and it provides many useful features. The hardware implementation of JPEG-2000, therefore, becomes essential technique of digital still camera. In this thesis, a high performance hardware architecture design of EBCOT block coder for JPEG-2000 is proposed. Speedup methods and pipelining technique are adopted according to the characteristic of EBCOT block coding algorithm. By using this architecture, process time can be reduced to about 40% of previous work. There are two major parts in this block coder: context formation (CF) and arithmetic encoder (AE). The main idea to improve the process speed of context formation is to skip no-operation samples. We achieve this by column-based coding architecture and two speedup methods. In arithmetic encoder, a four-stage pipeline is used to reduce the clock cycle time. Besides, a look-ahead technique is used in probability table look up to process two identical contexts continuously inputted. A prototyping chip is implemented to verify the proposed architecture. The technology used is CMOS 0.35um 1P4M technology. The area of this chip is 3.67x3.67 mm2. The clock frequency is 50 MHz. It can encode 4.6 million pixels image within 1 second, corresponding to 2400x1800 image size, or 452x340 video sequence with 30 frames per second. Therefore, this chip is compliant with the upcoming motion JPEG-2000 standard.
Hsu, Ying-Chieh y 徐膺傑. "High Performance and Low Cost EBCOT-Tier-1 encoder". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/78282926931311143808.
Texto completo國立中正大學
電機工程研究所
93
In this thesis, we propose an EBCOT-tier-1 encoder with high performance and low cost, which includes two parts: 1)Constant output rate CF, 2)Input interleaving AE. The constant-output rate CF can process a code block with the minimal number of clock cycles. The AE exploited the input-interleaving technique is the fast arithmetic encoder among all proposed literatures. Our proposed EBCOT-tier1 encoder employs one encoder so we can achieve much more area saving and maintain good performance in comparison with those encoders presented in related high performance works. 74.4M samples/sec can be realized by using two independent constant-output rate CFs operating at 200MHz and one input-interleaving AE operating at 400MHz. The sampling rate can be applied on the HDTV 720p RGB(4:2:0) application.
Lai, Chih-Hung y 賴智宏. "The Study of VLSI Architecture Design for JPEG2000 EBCOT". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/26387272487208581311.
Texto completo國立臺灣海洋大學
資訊工程學系
96
The Context Formation of EBCOT tire-1 in the JPEG2000 system contains high complexity computation and also becomes the bottleneck in this system. In this thesis, we focus on the VLSI hardware architecture design of Context Formation. In order to improve the Context Formation computation speed, we propose the parallel VLSI architecture for computing the parallel pass predict and pass coding of Context Formation. In the pass predict part, it can predict all need-encode bits of one column at one clock period. In the pass coding part, it can generate the Context (CX) and Decision (D) at every clock period. Compared with existing proposed coding method, such as GOCS、CUPS and PP coding architecture, this architecture can reduce 3 times clock of pass coding to achieve the requirement for fast coding. The hardware architecture was coded in VerilogHDL, implemented in a FPGA, and verified by the platform of Quartus-II enviorenment.
Chang, Chi-Chin y 張其勤. "Efficient Design of JPEG2000 EBCOT TIER-I Context Formation Encoder". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/82514225034333603693.
Texto completo國立交通大學
電機資訊學院碩士在職專班
94
JPEG2000 is a new still image compression standard. The most attractive feature of this new standard is that it can reduce the bit rate significantly while the image quality is also preserved. However, this feature requires more complex computations and hardware cost in comparison to other standards. Moreover, most of the computation time is in EBCOT. There are many design techniques have been proposed for its efficient realization. The Pass-Parallel architecture is one of the most efficient methods. In this thesis, we propose some methods to improve the computation efficiency, hardware utilization, and reduce hardware area for the Pass-Parallel EBCOT context formation (CF) engine. The Sample-Parallel Pass-Type Detection (SPPD) method is proposed to improve the performance in deciding the pass types of all four samples in the same column. The Column-Based Pass-Parallel Coding (CBPC) method is proposed to code all four samples in the same column concurrently. We design a CF encoder to verify both new methods. We use two steps to process the input samples to CF and optimize each steps. In step one we use SPPD to shorten the time for determining pass types, and thus improve the whole computation performance. In step two we use CBPC to code all four samples in the same column according to the pass types determined in step one, and thus reduce the hardware cost and improve the hardware utilization. Our design is synthesized by Synopsys® Design Compiler using TSMC CMOS 0.15μm process. The pre-layout synthesized area is 18127.31 μm2. In our simulation, the operation clock frequency can be up to 600 MHz in the WCCOM worst_case_tree environment. With this clock frequency, it needs 0.0116 second to encode an image with 2304 x 1728 image size. Both proposed methods can reduce 13.83% of the encoding time, 18.28% of the hardware cost, and 34.78% of the hardware utilization, in comparison to the original Pass-Parallel CF.
黃志強. "JPEG2000之EBCOT硬體架構設計研究". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/86078133989451387656.
Texto completo南台科技大學
電子工程系
93
Embedded Block Coding with Optimized Truncation (EBCOT) is the key technique to the powerfulness of JPEG-2000 image standard. In this paper, an efficient Binary Arithmetic Encoding (BAE) algorithm suitable for EBCOT is proposed. EBCOT has shown its advantage of high compression rate, yet at the cost of considerable computation time. The computation time is mostly spent for BAE. This is especially true while handling high-resolution images. To attack this problem, we use a look-ahead strategy to reduce the operations needed during BAE based on input bit stream patterns. It can be proved that the proposed algorithm can effectively minimize the number of operations needed to carry out the BAE used in EBCOT. We propose an efficient architecture composed of pass-parallel context modeling scheme and arithmetic encoder ( for EBCOT entropy encoder used in JPEG2000. The pass-parallel context modeling scheme merges the three coding passes of bit-plane coding process into a single pass to improve the system performance. Instead of using three arithmetic encoders. The proposed architecture can have fast computation time and low internal memory accesses. Compared with the conventional architectures it reduces 8K bits of internal memories. Based on the pass-parallel context modeling scheme, an experimental FPGA was designed and simulated. The experimental results show that the proposed architecture reduces the processing time by more than 45% compared with the previous methods.
Chen, Kuan-Chung y 陳冠中. "A Study of EBCOT Coding for Wavelet-based ECG Data Compression". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/50866309573767458712.
Texto completo國立高雄第一科技大學
電腦與通訊工程研究所
102
Embedded Block Coding with Optimized Truncation (EBCOT) is a codeing strategy of conditional probability formula, which has been widely used in the codec of wavelet transform coefficients, and is the same codec strategy to Set Partitioning In Hierarchical Trees (SPIHT), Both deal with the encoding object of bit-plane. Both coding system were include in JPEG2000 standard due to the excellent coding efficiency. SPIHT strategy was first applied to wavelet transform ECG data compression in novel 2000 and get very good compression performance. This article was to apply the EBCOT to wavelet transform ECG data compression for the exploration of the compression performance. This paper adopted a non-recursive rounding reversible integer wavelet transform discrete periodic wavelet transform coefficients that obtained the one-dimensional bit-plane signals into 12 classes. Take MIT arrhythmia database as the simulation objects, through the EBCOT coding, we get the average entropy = 2.0742, The storaged raw data is 12bits/pixel, the compression ratio is about 6:1, zero percent of distortion rate. Compared with the strategy of SPIHT, the distortion rate is 1.58% under the compression ratio of 6:1. It is obviously that there is a great potential to apply this coding strategy to the ECG data compression.
Su, Chun-Yi y 蘇俊義. "A Study of Data Hiding Scheme for Magnitude Refinement Pass of EBCOT". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/23718396009296305674.
Texto completo國立高雄第一科技大學
電腦與通訊工程所
98
Accompanying the expansion of bandwidth and internet space is a higher demand on the part of users for enhanced image quality for image storage or internet transmission. Meanwhile, technology that uses images for data hiding also requires improved image quality. This paper uses magnitude refinement pass of the JPEG2000 EBCOT encoder for data hiding that replaces high-bit-rate pulse compression to embed the data range of continuous wavelet coefficient after quantification. Because human vision is unable to identify detail changes in each piece of an image, this study conducts data hiding from low to high bit according to the continuous wavelet coefficient in the magnitude refinement pass of the EBCOT Tier 1 encoder. After the experiment, images with less hidden high-frequency information were found to have higher image quality after compression than those with more hidden high-frequency information. Even for two pieces of an image that human vision cannot recognize the discrepancy before and after information has been hidden, the high quality of the image is undeniably guaranteed.
Hsieh, Tien-Wei y 謝天威. "A Low Power and High Performance AHB-compliant EBCOT Architecture for JPEG2000 Encoding". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/77873215341404733223.
Texto completo國立清華大學
資訊工程學系
92
We propose a low power and high performance Tier-1 architecture of Embedded Block Coding with Optimized Truncation (EBCOT) in the JPEG2000 encoder. In the context formation, we use a parallel structure for low power consumption, a memory-saving algorithm to decrease memory access, a memory arrangement to utilize bandwidth efficiently, and a stripe-skipping method for performance benefit. In the arithmetic encoder, we adopt a modified probability estimation table and a forwarding method to implement pipelined architecture. We present a renormalization strategy that can save cycles during the coding process. Our design is easily integrated into the AMBA-based system as an accelerator. Compared with the best-known column-based method, we reduce the cycle count by 17%. Let the number of context-decision (CX, D) pairs be the lower bound on the cycle count, we have achieved 5% within the optimum.
Chiou, Tzau-min y 邱肇民. "Memory Analysis and Throughput Enhancement for Cost Effective EBCOT Tier-1 Architecture in JPEG2000 Applications". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/22112050433282235111.
Texto completo國立中興大學
電機工程學系
93
JPEG2000 Tier-1 coder is the most important technology in the latest still image compression standard , JPEG2000. According to the analysis for JPEG2000 ,JPEG2000 Tier-1 coder is the bottleneck of the system because the operations are bit-level processing and occupy more than half of the computation time of the whole compression process. A general purpose processor is ,therefore, very inefficient to process these operation. In this thesis, a low cost and memory efficient bit-plane coder with throughput enhancement in JPEG2000 applications is proposed. Many literatures and the results of the chip implementation show that the memory requirements and the three coding passes dominate the hardware cost and the throughput rate of the EBOCT architecture respectively. In order to reduce the memory size, the memory-free algorithm is proposed to eliminate state variable memories by calculating three coding state variables (γp+1[n], σp+1[n], and πp[n]) on the fly. We also propose the stripe-column-based pass-parallel operation to perform three coding passes and four samples within the stripe-column concurrently. Moreover, the state variables are predictable as a result of our memory-free algorithm. Therefore, the proposed architecture is also a configurable architecture to exploit the parallelism of the bit-planes level to increase the throughput and to diminish the memory bandwidth. The experimental results show that the hardware cost and memory size of the proposed architecture is smaller than other existing architectures, and the proposed architecture has 3 times greater throughput than other familiar architectures.
Chang, Tso-Hsuan y 張倬炫. "Design of High-performance, Low-power and Memory-efficient EBCOT and MQ Coder for JPEG2000". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/46956123277307387380.
Texto completo國立中山大學
資訊工程學系研究所
91
JPEG2000 is an emerging state-of-the-art standard for still image compression. The standard not only offers superior rate-distortion performance, but also provides a wide range of features and functionality compared to JPEG. However, advantages of JPEG2000 come at the expense of computational complexity and memory requirement in bit-plane coding. So the low cost ASIC design for JPEG2000 hardware implementation remains a challenge. Therefore, a dedicated hardware implementation for EBCOT block coder is necessary. In this thesis a high-throughput EBCOT block coder is proposed. There are two main parts in the EBCOT block coder: context modeling and MQ-coder. For context modeling a novel pass-parallel module based on vertical causal mode is proposed. Pass-parallel modeling which reduces the cycles to check the sample to be coded processes three original sequential passes in a single pass and generates one or two context labels every cycle. It is fast and saves 8K bits internal memory. Since context modeling will generate one or two context labels in one cycle, multi-bit MQ-coder which could avoid the buffer between context modeling and MQ-coder overflows is needed. For MQ-coder three approaches which process one or two context labels in one cycle are proposed. Furthermore, we modified the architecture of MQ-coder and proposed two low-power implementation concepts : reduction of memory access and disabling unused block.
Xiong, Ziyou. "Exploration on integration of Set Partitioning in Hierarchy Tree(SPIHT) with Embedded Block Coding with Optimized Trunction(EBCOT)". 1999. http://catalog.hathitrust.org/api/volumes/oclc/44570960.html.
Texto completoTypescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 46).
Stühmer, Franziska Johanna Bernise [Verfasser]. "Verlaufsuntersuchung zur Koronarsklerose nach Herztransplantation mittels EBCT / von Franziska Johanna Bernise Stühmer". 2007. http://d-nb.info/989208001/34.
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