Tesis sobre el tema "Digital logic circuits"
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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.
Texto completoIn this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
Gaubatz, Donald Almo. "Logic programming analysis of asynchronous digital circuits". Thesis, University of Cambridge, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386062.
Texto completoLiu, Tai-hung. "Logic synthesis for high-performance digital circuits /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Texto completoXia, Yinshui. "Low power design techniques for digital logic circuits". Thesis, Edinburgh Napier University, 2003. http://researchrepository.napier.ac.uk/Output/6887.
Texto completoDuncan, Austin H. "Logic Gates Using the Digilent Basys3". Digital Commons @ East Tennessee State University, 2015. https://dc.etsu.edu/honors/311.
Texto completoHacker, Charles Hilton y n/a. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Griffith University. School of Engineering, 2001. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20050915.172404.
Texto completoHacker, Charles. "WinLogiLab - A Computer-Based Teaching Suite for Digital Logic Design". Thesis, Griffith University, 2001. http://hdl.handle.net/10072/367209.
Texto completoThesis (Masters)
Master of Philosophy (MPhil)
School of Engineering
Science, Environment, Engineering and Technology
Full Text
Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits". Ottawa, 1999.
Buscar texto completoKeeble, Clifford George. "The synthesis of self-timed circuits by formal methods". Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239920.
Texto completoSah, Puja. "Implementing Digital Logic Design Concepts Using Paper Electronics". Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1157633/.
Texto completoMachado, Lucas. "Logic decomposition and adaptive clocking for the optimization of digital circuits". Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/665978.
Texto completoA lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.
Bataineh, Abdulla. "Parallel logic and interconnection simulation algorithms for high-speed digital circuits /". The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu148775943632878.
Texto completoTaber, Caleb N. "Conversion of Digital Circuits Labs". Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.
Texto completoHerbert, J. M. J. "Application of formal methods to digital system design". Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233985.
Texto completoChenard, Jean-Samuel. "Hardware-based temporal logic checkers for the debugging of digital integrated circuits". Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106282.
Texto completoLa complexité des circuits intégrés augmente sans cesse et à un tel point que le procéssus de déboggage pose de nombreux problèmes techniques et engendre des retards dans la production. Une approche d'ensemble de conception pour le déboggage (Design-for-Debug) devient donc rapidement une nécessité. Cette thèse propose une approche détaillée de niveau système, intégrant des circuits de surveillance sur puce. L'approche proposée s'appuie sur la réutilisation de déclarations écrites en language de logique temporelle afin de les transformer en circuits digitaux efficaces. Ces derniers seront intégrés à la puce à travers son interface d'image mémoire afin qu'ils puissent servir au processus de déboggage ainsi qu'à une utilisation dans le système lorsque la puce est intégrée dans son environement. Cette thèse présente une série d'ajout au procéssus de transformation d'instructions de logique temporelle de manière à faciliter le procéssus de déboggage. Une méthode qui automatise l'intégration des sorties et du contrôle des circuits de surveillance est présentée ainsi que la manière dont une utilisation de ces circuits peut être accomplie dans le contexte d'un système d'exploitation moderne (Linux). Finalement, une méthode globale d'intégration des circuits de vérification dans le contexte de systèmes basés sur les réseaux-sur-puce est présentée, accompagnée de la chaine d'outils requise pour supporter ce nouveau processus de conception. Cette méthode propose l'utilisation de facteurs de qualité de test, de surveillance et de déboggage (Test, Monitoring and Debug) permettant une meilleure sélection des circuits ainsi qu'une intégration plus efficace au niveau des resources matérielles.
Nguyen, Loc Bao. "Logic design using programmable logic devices". PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
Texto completoHenry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits". Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.
Texto completoPh. D.
Lammert, Adam Crawford. "Searching for Better Logic Circuits: Using Artificial Intelligence Techniques to Automate Digital Design". NCSU, 2006. http://www.lib.ncsu.edu/theses/available/etd-06072006-140938/.
Texto completoElliot, Ralph. "Some issues in the design of digital circuits using Occam and temperal logic". Thesis, University of East Anglia, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.253629.
Texto completoHassoune, Ilham. "Design and optimization of digital circuits for low power and security applications". Université catholique de Louvain, 2006. http://edoc.bib.ucl.ac.be:81/ETD-db/collection/available/BelnUcetd-06292006-113241/.
Texto completoHolst, Stefan [Verfasser] y Hans-Joachim [Akademischer Betreuer] Wunderlich. "Efficient location-based logic diagnosis of digital circuits / Stefan Holst. Betreuer: Hans-Joachim Wunderlich". Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2012. http://d-nb.info/1028799373/34.
Texto completoBattina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design". Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.
Texto completoDavis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications". Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.
Texto completoRoumeliotis, Emmanuel. "Multi-processor logic simulation at the chip level". Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71180.
Texto completoPh. D.
Silva, Jose Carlos da. "Conversor digital quaternario para analogico". [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260604.
Texto completoTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Neste trabalho é apresentada a lógica múltiplo valor como opção para substituir ou ser usada como interface com a lógica binária. A lógica múltiplo valor difere da lógica binária clássica devido ao fato que os seus dígitos estão além de zeros e uns. Utilizando a lógica múltiplo valor consegue-se comunicação em entre blocos ou com o mundo externo a um chip com menor número de interconexões, o que acarretará a diminuição da área do circuito integrado e redução de custos. Pesquisadores e industria caminham para a pesquisa e desenvolvimento de circuitos múltiplos valores, que podem substituir ou ser utilizados como interface com os circuitos de dois valores (binários). Este trabalh o apresenta o desenvolvido do projeto de um conversor digital quaternário para analógico que tem quatro entradas e resolução equivalente a um conversor digital binário para analógico de oito entradas. Este conversor foi confeccionado totalmente em tecnologia CMOS 0.35µm, tendo como resultado um protótipo de um circuito integrado múltiplo valor que contém todas as células de um conversor digital binário para analógico. Este conversor apresenta consumo de potência abaixo de 1mW, alimentação simples de 5V e compactação (900µm x 235µm)
Abstract: In this work is presented the multiple value logic as option to substitute or to be used as interface with the binary logic. The multiple value logic differs of the classic binary logic to the fact that its digits are beyond zeros and ones. Using the multiple logic value obtains communication in between blocks or with the external world to one chip with lesser number of interconnections, what it will cause the reduction of the area of the integrated circuit and reduction of costs. Researchers and industry walk for the research and development of multiple values circuits, that can substitute or be used as interface with the circuits of two values (binary). This work presents the developed one of the project of a quaternary digital to analog converter that it has four inputs and resolution equivalent to a binary digital to analog converter of eight inputs. This converter was confectioned totally in technology CMOS 0.35µm, having as resulted an prototype of an integrated circuit multiple value that contains all the cells of a binary digital to analog converter. This converter presents consumption of power below of 1mW, simple voltage of 5V and compacting (900µm x 235µm)
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
Chakrapani, Lakshmi Narasimhan. "Probabilistic boolean logic, arithmetic and architectures". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26706.
Texto completoCommittee Chair: Palem, Krishna V.; Committee Member: Lim, Sung Kyu; Committee Member: Loh, Gabriel H.; Committee Member: Mudge, Trevor; Committee Member: Yalamanchili, Sudhakar. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Mozaffari, Mojaveri Seyed Nima. "DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES". OpenSIUC, 2018. https://opensiuc.lib.siu.edu/dissertations/1526.
Texto completoBreitkreutz-von, Gamm Stephan Verfasser], Doris [Akademischer Betreuer] [Schmitt-Landsiedel y György [Akademischer Betreuer] Csaba. "Perpendicular Nanomagnetic Logic: Digital Logic Circuits from Field-coupled Magnets / Stephan Breitkreutz-von Gamm. Gutachter: György Csaba ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel". München : Universitätsbibliothek der TU München, 2015. http://d-nb.info/1075596009/34.
Texto completoTing, Darwin Ta-Yueh. "Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs". Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.
Texto completoTeixeira, Marco Antonio. "Técnicas de reconfigurabilidade dos FPGAs da família APEX 20K - Altera". Universidade de São Paulo, 2002. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-11092002-164901/.
Texto completoThe APEX 20K programmable logic devices family, are configured at system power-up with data stored in a specific serial configuration device. This family of FPGAs contain an optimized interface that permits microprocessors to configure APEX 20K devices serially or in parallel, and synchronously or asynchronously. After configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes lead to innovative reconfigurable computing applications. The commercial available configuration devices limit to configure the APEX 20K devices only on the system power-up and always with the same configuration data file. This work shows a configuration controller implementation that can manage the configuration and reconfiguration of several FPGAs from multiple configuration files. The entire project is developed, tested and validated through the EDA tool Quartus II, that provide a integrated package with HDL and schematic design entry, compilation and logic synthesis, full simulation and worst-case timing analysis.
Heim, Marcus Edwin Allan. "ANALYSIS OF MOS CURRENT MODE LOGIC (MCML) AND IMPLEMENTATION OF MCML STANDARD CELL LIBRARY FOR LOW-NOISE DIGITAL CIRCUIT DESIGN". DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1422.
Texto completoTang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors". 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.
Texto completoMachado, Lucas. "KL-cut based remapping". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/116138.
Texto completoThis work introduces the concept of k-cuts and kl-cuts on top of a mapped circuit in a netlist representation. Such new approach is derived from the concept of k-cuts and klcuts on top of AIGs (and inverter graphs), respecting the differences between these two circuit representations. The main differences are: (1) the number of allowed inputs for a logic node, and (2) the presence of explicit inverters and buffers in the netlist. Algorithms for enumerating k-cuts and kl-cuts on top of a mapped circuit are proposed and implemented. The main motivation to use kl-cuts on top mapped circuits is to perform local optimization in digital circuit logic synthesis. The main contribution of this work is a novel iterative remapping approach using klcuts, reducing area while keeping the timing constraints attained. The use of complex gates can potentially reduce the circuit area, but they have to be chosen wisely to preserve timing constraints. Logic synthesis commercial design tools work better with simple cells and are not capable of taking full advantage of complex cells. The proposed iterative remapping approach can exploit a larger amount of logic gates, reducing circuit area, and respecting global timing constraints by performing an STA (static timing analysis) check. Experimental results show that this approach is able to reduce up to 38% in area of the combinational portion of circuits for a subset of IWLS 2005 benchmarks, when compared to results obtained from logic synthesis commercial tools. Another contribution of this work is a novel yield model for digital integrated circuits (IC) manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the lithography, but it results in a significant area overhead by introducing regularity. This is the first approach that considers the tradeoff of cells with different level of regularity and different area overhead during the logic synthesis, in order to improve overall design yield. The technology remapping tool based on kl-cuts developed was modified in order to use such yield model as cost function, improving the number of good dies per wafer, with promising interesting results.
Bhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits". Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
Texto completoSutton, Akil Khamisi. "Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29778.
Texto completoCommittee Chair: Cressler, John; Committee Member: Deo, Chaitanya; Committee Member: Doolittle, Alan; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Tran, Duc Anh. "Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques". Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20132/document.
Texto completoEvolution of CMOS technology consists in continuous downscaling of transistor features sizes, which allows the production of smaller and cheaper integrated circuits with higher performance and lower power consumption. However, each new CMOS technology node is facing reliability problems due to increasing rate of faults and errors. Consequently, fault-tolerance techniques, which employ redundant resources to guarantee correct operations of digital circuits and systems despite the presence of faults, have become essential in digital design. This thesis studies a novel hybrid fault-tolerant architecture for robustness improvement of digital circuits and systems. It targets all kinds of error in combinational part of logic circuits, i.e. hard, SETs and timing errors. Combining information redundancy for error detection, timing redundancy for transient error correction and hardware redundancy for permanent error corrections, the proposed architecture allows significant power consumption saving, while having similar silicon area compared to existing solutions. Furthermore, it can also be used in other applications, such as dealing with aging phenomenon, tolerating faults in pipeline architecture, and being combined with advanced SEUs protection scheme for sequential parts of logic circuits
Ho, Philip. "Investigation of Solution Space of Trees and DAGs for Realization of Combinational Logic in AT 6000 series FPGAs". PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4586.
Texto completoLee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers". DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
Texto completoInampudi, Sivateja. "Teaching Fundamentals of Digital Logic Design and VLSI Design Using Computational Textiles". Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699874/.
Texto completoDal, Bem Vinícius. "CMOS digital integrated circuit design faced to NBTI and other nanometric effects". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/37180.
Texto completoThis thesis explores the challenges worsened by the technology miniaturization in fabrication and design of digital integrated circuits. The physical effects of nanometric regime reduce the production yield and shorten the devices lifetime, restricting the usefulness of standard design flows and threatening the evolution of CMOS technologies. This thesis exposes a consistent bibliographic review about the main aggressive physical effects of nanometric regime. NBTI has received special attention in reliability literature, so this text follows the same strategy, deeply exploring this aging effect. A broad set of NBTI evaluation and mitigation techniques are explained, including developed works in each one of these categories. The proposed circuit as NBTI evaluation technique allows the use of electrical simulation for circuit degradation analysis. The analysis of the transistors arrangement restructuring as a technique for NBTI degradation reduction shows satisfactory results, while does not restrict the use of other combined techniques.
Воргуль, О. В., І. В. Свид, О. В. Зубков y В. В. Семенець. "Teaching microcontrollers and FPGAs in Quarantine from Coronavirus: Challenges and Prospects". Thesis, MC&FPGA, 2020. https://mcfpga.nure.ua/conf/2020-mcfpga/10-35598-mcfpga-2020-005.
Texto completoZaghloul, Yasser A. "Polarization based digital optical representation, gates, and processor". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43675.
Texto completoFigueiró, Thiago Rosa. "Multiple objective technology independent logic synthesis for multiple output functions through AIG functional composition". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/27663.
Texto completoThe use of design automation tools has allowed complex projects to reach feasible time-to-market and cost parameters. In this context, logic synthesis is a critical procedure in the design flow. The technology independent step (part of the logic synthesis which is performed regardless any physical property) is traditionally performed over equations. The development of new multi-level optimization algorithms has recently shifted towards the use of And-Inverter-Graphs (AIGs). The number of nodes and the graphs depth in AIGs present better correlation with resulting circuit area and delay than any characteristic of other representations. In this work, a technology independent synthesis algorithm that works on top of an AIG data structure is proposed. A novel approach for AIG construction, based on a new synthesis paradigm called functional composition, is introduced. This approach consists in building the final AIG by associating simpler AIGs, in a bottom-up approach. The method controls, during the graphs construction, the characteristics of final and intermediate graphs by applying a cost function as a way to evaluate the quality of those AIGs. The goal is to minimize the number of nodes and the depth of the final AIG. This multi-objective synthesis algorithm has presented interesting features and advantages when compared to traditional approaches. Moreover, this work presents a method for AIGs construction for multiple output functions, which enhances structural sharing, improving the resulting circuit. Results have shown an improvement of around 5% in number of nodes when compared to ABC tool.
Guardia, Filho Luiz Eduardo. "Sistema para controle de maquinas robotizadas utilizando dispositivos logicos programaveis". [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259017.
Texto completoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais
Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions
Mestrado
Automação
Mestre em Engenharia Elétrica
Marusiak, David. "MOS CURRENT MODE LOGIC (MCML) ANALYSIS FOR QUIET DIGITAL CIRCUITRY AND CREATION OF A STANDARD CELL LIBRARY FOR REDUCING THE DEVELOPMENT TIME OF MIXED-SIGNAL CHIPS". DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1363.
Texto completoBortolon, Felipe Todeschini. "Static noise margin analysis for CMOS logic cells in near-threshold". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/178664.
Texto completoThe advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).
Wan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping". PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.
Texto completoZhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement". Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
Texto completoWebb, Robert L. "ASYNCHRONOUS MIPS PROCESSORS: EDUCATIONAL SIMULATIONS". DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/381.
Texto completoBenhaddou, Mohamed. "Définition d'une méthodologie de conception de circuits intégrés numériques indépendante de la technologie : application à la conception d'un processeur flou". Vandoeuvre-les-Nancy, INPL, 1995. http://www.theses.fr/1995INPL067N.
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