Artículos de revistas: "Coefficients programmables"

1

Reuver, D. y H. Klar. "A configurable convolution chip with programmable coefficients". IEEE Journal of Solid-State Circuits 27, n.º 7 (julio de 1992): 1121–23. http://dx.doi.org/10.1109/4.142613.

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Karvonen, S., T. A. D. Riley y J. Kostamovaara. "Charge-domain FIR sampler with programmable filtering coefficients". IEEE Transactions on Circuits and Systems II: Express Briefs 53, n.º 3 (marzo de 2006): 192–96. http://dx.doi.org/10.1109/tcsii.2005.858752.

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3

Niksan, K., M. A. Sid-Ahmed y A. Shah. "Hardware implementation of programmable coefficients recursive digital filter". Canadian Journal of Electrical and Computer Engineering 13, n.º 2 (1988): 85–88. http://dx.doi.org/10.1109/cjece.1988.6592781.

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4

Kei-Yong Khoo, A. Kwentus y A. N. Willson. "A programmable FIR digital filter using CSD coefficients". IEEE Journal of Solid-State Circuits 31, n.º 6 (junio de 1996): 869–74. http://dx.doi.org/10.1109/4.509877.

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5

Zhangwen Tang, Jie Zhang y Hao Min. "A high-speed, programmable, CSD coefficient FIR filter". IEEE Transactions on Consumer Electronics 48, n.º 4 (noviembre de 2003): 834–37. http://dx.doi.org/10.1109/tce.2003.1196409.

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6

KIM, Yong-Eun, Kyung-Ju CHO, Jin-Gyun CHUNG y Xinming HUANG. "CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E93-A, n.º 1 (2010): 324–26. http://dx.doi.org/10.1587/transfun.e93.a.324.

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7

Woo Jin Oh y Yong Hoon Lee. "Implementation of programmable multiplierless FIR filters with powers-of-two coefficients". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42, n.º 8 (1995): 553–56. http://dx.doi.org/10.1109/82.404090.

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8

Yi, Xiaoke, Thomas X. H. Huang y Robert A. Minasian. "Tunable and Reconfigurable Photonic Signal Processor With Programmable All-Optical Complex Coefficients". IEEE Transactions on Microwave Theory and Techniques 58, n.º 11 (noviembre de 2010): 3088–93. http://dx.doi.org/10.1109/tmtt.2010.2076931.

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9

Rosado, A., M. Bataller, J. F. Guerrero, J. Calpe, J. V. Francés y J. R. Magdalena. "High performance hardware correlation coefficient assessment using programmable logic for ECG signals". Microprocessors and Microsystems 27, n.º 1 (febrero de 2003): 33–39. http://dx.doi.org/10.1016/s0141-9331(02)00083-2.

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10

Harrison, Kevin W., Eduardo Hernández-Pacheco, Michael Mann y Hossein Salehfar. "Semiempirical Model for Determining PEM Electrolyzer Stack Characteristics". Journal of Fuel Cell Science and Technology 3, n.º 2 (18 de noviembre de 2005): 220–23. http://dx.doi.org/10.1115/1.2174072.

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A semiempirical equation was used to represent the performance characteristics of a 20-cell proton exchange membrane electrolyzer stack. The coefficients of the equation are the exchange current densities and membrane conductivity. These coefficients were determined using experimental data and a nonlinear curve fitting method. The anode exchange current density was found to be 1.65×10−8Acm−2, the cathode exchange current density 0.09Acm−2, and the membrane conductivity 0.075Scm−1. External programmable power supplies were used to obtain the (I‐V) characteristic curve of a commercial proton exchange membrane electrolyzer. Stack current, voltage, and system temperature were monitored while 1A current steps were applied to the electrolyzer stack.

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11

Chervyakov, Nikolay, Pavel Lyakhov, Dmitry Kaplun, Denis Butusov y Nikolay Nagornov. "Analysis of the Quantization Noise in Discrete Wavelet Transform Filters for Image Processing". Electronics 7, n.º 8 (2 de agosto de 2018): 135. http://dx.doi.org/10.3390/electronics7080135.

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In this paper, we analyze the noise quantization effects in coefficients of discrete wavelet transform (DWT) filter banks for image processing. We propose the implementation of the DWT method, making it possible to determine the effective bit-width of the filter banks coefficients at which the quantization noise does not significantly affect the image processing results according to the peak signal-to-noise ratio (PSNR). The dependence between the PSNR of the DWT image quality on the wavelet and the bit-width of the wavelet filter coefficients is analyzed. The formulas for determining the minimal bit-width of the filter coefficients at which the processed image achieves high quality (PSNR ≥ 40 dB) are given. The obtained theoretical results were confirmed through the simulation of DWT for a test image using the calculated bit-width values. All considered algorithms operate with fixed-point numbers, which simplifies their hardware implementation on modern devices: field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.

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12

Carbajal-Gomez, Victor, Esteban Tlelo-Cuautle, Carlos Sanchez-Lopez y Francisco Fernandez-Fernandez. "PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors". Electronics 7, n.º 10 (16 de octubre de 2018): 252. http://dx.doi.org/10.3390/electronics7100252.

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Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

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13

De Man, E., M. Schulz y W. Haberecht. "A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency". IEEE Journal of Solid-State Circuits 26, n.º 3 (marzo de 1991): 435–39. http://dx.doi.org/10.1109/4.75032.

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14

Huang, T. X. H., X. Yi y R. A. Minasian. "Microwave photonic filters with programmable bipolar coefficients based on -phase inversion of DSB sidebands". Electronics Letters 46, n.º 24 (2010): 1609. http://dx.doi.org/10.1049/el.2010.2242.

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15

Wei, Kai, Xiaoyujie Xiao, Wentao Xu, Zhengtong Han, Yazhuo Wu y Zhonggang Wang. "Large programmable coefficient of thermal expansion in additively manufactured bi-material mechanical metamaterial". Virtual and Physical Prototyping 16, sup1 (26 de abril de 2021): S53—S65. http://dx.doi.org/10.1080/17452759.2021.1917295.

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16

Sharma, Anshuman, Abdul Hafeez Syed, Midhun M y M. R. Raghavendra. "Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing". International Journal of Reconfigurable and Embedded Systems (IJRES) 3, n.º 1 (1 de marzo de 2014): 18. http://dx.doi.org/10.11591/ijres.v3.i1.pp18-24.

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This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and were implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for a data rate from 1kbps to 8kbps was implemented.

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17

Jovanovic Dolecek, Gordana y Gabriel Alejandro Martinez Novelo. "Design and FPGA Implementation of Compensator for Sharpening CIC Filter". IOP Conference Series: Materials Science and Engineering 1298, n.º 1 (1 de diciembre de 2023): 012017. http://dx.doi.org/10.1088/1757-899x/1298/1/012017.

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Abstract This paper presents a novel compensator design for sharpened CIC (cascade-integrator-comb) proposed in the literature. Sharpened CIC provides higher aliasing attenuation than the CIC filter. However, its passband droop is higher than the corresponding CIC filter and must be compensated. Our motivation was to design a decimator with better compensation than the one proposed in the literature. The proposed decimation filter has two coefficients and six adders. The coefficients are determined using particle swarm optimization (PSO) in MATLAB. Two designs are presented. The first one has two multipliers and six adders. The second is a multiplierless design obtained by presenting optimal coefficients in the signed power-of-two (SPT) form. The proposed design is compared with the design from the literature. The designed compensator is implemented in a field-programmable gate array (FPGA). Details of the implementation are described in the paper.

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18

Bradfield, C. D., J. B. Roberts y S. Karunendiran. "A Programmable Electromagnetic Bearing for Vibration Control of a Flexible Shaft". Journal of Vibration and Acoustics 113, n.º 2 (1 de abril de 1991): 160–66. http://dx.doi.org/10.1115/1.2930164.

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The transverse vibrations of flexible rotors can be reduced to safe levels by radial control forces at an intermediate span position, applied by a suitable actuator. One versatile control strategy applies forces proportional to displacement and velocity, with coefficients dependent on the rotational speed. This control can be realized with an electromagnetic bearing under microprocessor control. Suitable microprocessor software is described, to implement the required real-time computation of the control forces. Experimental results obtained from a test rig are compared with theoretical predictions. There are advantages in allowing the stiffness coefficient to become negative, provided that positive damping is simultaneously applied.

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19

Vallancourt, D. y Y. P. Tsividis. "A fully programmable sampled-data analog CMOS filter with transfer-function coefficients determined by timing". IEEE Journal of Solid-State Circuits 22, n.º 6 (diciembre de 1987): 1022–30. http://dx.doi.org/10.1109/jssc.1987.1052851.

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20

Wang, Yanping, Xiaogang Sun, Jianting Zhao, Kunli Zhou, Yunfeng Lu, Jifeng Qu, Pengcheng Hu y Qing He. "Simulation Analysis of Phase Jitter in Differential Sampling of AC Waveforms Based on the Programmable Josephson Voltage Standard". Electronics 13, n.º 10 (11 de mayo de 2024): 1890. http://dx.doi.org/10.3390/electronics13101890.

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The effect of phase jitter on differential sampling using the programmable Josephson voltage standard (PJVS) system is studied in this paper. A phase jitter model is established for the measured signal, and compensation coefficients for phase jitter removal are derived for three different post-processing methods based on the discrete Fourier transform algorithm (DFT). Based on our analysis, the phase jitter compensation coefficients are determined by the phase jitter angle distribution and harmonic order. Furthermore, after analyzing and simulating various common distributions, the phase jitter compensation coefficients have been verified. The simulation shows that when the standard deviation of the phase jitter angle is 20 ns, and the frequency of the measuring waveform is 3.46 kHz, the influence of the phase jitter is 1 × 10−7. The results of the simulation indicate that, in the differential sampling of AC waveforms using a PJVS system, phase jitter is one of the error terms for an uncertainty budget that cannot be neglected, particularly as the frequency of the measured waveforms increases.

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21

Nickols, F. "A Tabular Format for Computing Inverse Kinematic Equations for a 3DOF Robot Leg". International Journal of Advanced Robotic Systems 6, n.º 3 (1 de enero de 2009): 26. http://dx.doi.org/10.5772/7234.

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A method is presented for accurately computing the three servomechanism angles that place the leg tip of a 3DOF robot leg in cylindrical coordinate space, R, θ, Z. The method is characterized by (i) a multivariable integer power series for each degree of freedom that can be used to replace traditional trigonometrical functions, and, (ii) only integer numbers are used. A technique is shown that derives the coefficients, Ci j k, of each of the terms in the series that represents a servomechanism angle, S. This power series method has the advantage of; (i) satisfying accuracy requirements, (ii) producing a unique solution, (iii) high speed realtime computation, (iv) low memory requirement and (v) implementation into a generic algorithm or hardware such as a field programmable gate array. The series can represent many continuous kinematic systems just by changing the values of the coefficients. The coefficients are rapidly computed via a spreadsheet. The method can be extended to more than three degrees of freedom and also mapped into other coordinate frames such as a Cartesian or spherical.

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22

Chen, Jing, Chang Yin Liu y Xue Ping Li. "The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB". Advanced Materials Research 791-793 (septiembre de 2013): 2122–26. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.2122.

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Polyphase FIR filters are applied in many practical Digital Signal Processing applications where the sampling rate needs to be changed. This paper focuses on the implementation of polyphase square root raised cosine (SRRC) FIR filter based on Field Programmable Gate Array (FPGA). The filter employs methods like filter's multiphase structure, symmetrical coefficients, I/Q channel multiplexing, pipeline addition and so on to design the SRRC filter. Compared with the traditional method, the designed FIR filter exhibits the advantages of high response speed and low hardware resource s consumption.

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23

Zhao, Yuyin, Yu Fang, Jiajun Yang, Weixuan Zhang, Xiaoxing Ge, Songyin Cao y Xiaonan Xia. "An Implementation Method for an Inductive Proximity Sensor with an Attenuation Coefficient of 1". Energies 13, n.º 24 (8 de diciembre de 2020): 6482. http://dx.doi.org/10.3390/en13246482.

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In order to achieve long-distance measurement, a bridge differential inductance detection circuit is employed; on this basis, an automatic zero adjustment technique for sensors using an integral–proportional-integral controller is proposed in this work to achieve consistent product production and efficient installation and debugging, and the mathematical model of the bridge differential inductance detection circuit is established to effectively design the controller parameters. Furthermore, an implementation method for an inductive proximity sensor with an attenuation coefficient of 1 is also proposed based on the bridge differential inductance detection circuit by querying the proximity distance table in the field-programmable gate array (FPGA) to detect multiple target metal objects at the same inductive distance. Simulation and experimental results show that the proposed method is correct and effective.

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24

Aparna, A. y T. Vigneswaran. "DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS". Asian Journal of Pharmaceutical and Clinical Research 10, n.º 13 (1 de abril de 2017): 66. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19564.

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This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.

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25

Ou, Chien Min, Wen Jyi Hwang y Ssu Min Yang. "Efficient Hardware Architecture for Kernel Fuzzy C-Means Algorithm". Applied Mechanics and Materials 284-287 (enero de 2013): 3079–86. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.3079.

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A novel VLSI architecture for kernel fuzzy c-means algorithm is presented in this paper. The architecture consists of efficient circuits for the computation of kernel functions, membership coefficients and cluster centers. In addition, the usual iterative operations for updating the membership matrix and cluster centers are merged into one single updating process to evade the large storage requirement. The circuit is used as a hardware accelerator of a softcore processor in a system-on-programmable chip for physical performance measurement. Experimental results show that the proposed solution is an effective alternative for cluster analysis with low computational cost and high performance.

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Shanmuga sundari, M., S. Loganathan y C. M. Sujatha. "Hardware Implementation Of ECG Signal Compression Using SPIHT". Journal of Physics: Conference Series 2318, n.º 1 (1 de agosto de 2022): 012017. http://dx.doi.org/10.1088/1742-6596/2318/1/012017.

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Abstract Cardiovascular disorder is a primary cause of mortality throughout the world in both developed and underdeveloped countries. Continuous cardiac monitoring enables clinicians to identify arrhythmias and other heart conditions. Tele-cardiology introduces remote monitoring devices for tracking the cardiac activity of the patients. The large volume of Electrocardiogram (ECG) data needs to be stored, processed and transmitted by these portable health care devices. The implementation of ECG compression in hardware platform is crucial for continuous health monitoring applications. The aim of this work is to implement field programmable gate array based set partitioning in hierarchical trees-based electrocardiogram compression. Discrete wavelet transform method is employed to break up the signal into sub bands. The transformed coefficients after discrete wavelet transform are passed through dead zone quantization which rejects low magnitude values of transformed coefficients lying around zero. These quantized coefficients are then encoded by lossless set partitioning used in hierarchical trees compression approach. The introduction of dead zone quantization in the proposed technique is found to be effective and yields an increased compression ratio of 10.33 with decreased distortion value of 1.04 percent for ECG record 117 of MIT-BIH arrhythmia database.

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Liu, Zi Ran, Cai Xia Ren y Xian Guo Yan. "Surface Heat Transfer Coefficient’s Calculation of W9Mo3Cr4V during Cryogenic Treatment". Applied Mechanics and Materials 43 (diciembre de 2010): 424–29. http://dx.doi.org/10.4028/www.scientific.net/amm.43.424.

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In the process of the finite element analogy of the Cryogenic Treatment of the high speed steel cutter with respect to the material of W9Mo3Cr4V, the surface heat transfer coefficient is a crucial parameter. In order to get this parameter, this paper employed the method of inverse heat conduction to process the temperature curve generated through the cryogenic treatment of the tested work piece with the material of W9Mo0Cr4V, thereby obtaining the surface heat transfer coefficient of the tested work piece. This coefficient can be considered the surface heat transfer coefficient of cryogenic treatment of the cutter with the same material. The principle of the inverse heat conduction is as follows: firstly, according to the boundary condition and the initial value in the tri-dimensional space, the equation of the sensitivity coefficient and the temperature field can be deduced. Second, the coupling of two equations is carried out, and the heat flux density is calculated based on above result. The heat flux density will be revise to get the reasonable value . Lastly, the surface heat transfer coefficient can be obtained by the heat flux density. In this paper, all the work is automatically accomplished with the aid of FEPG soft ware and Visual C++ programmable language.

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Burova, Adeliya Yu, Anatoly V. Ryapukhin y Alexandra R. Muntyan. "Reduced hardware costs with software and hardware implementation of digital methods multistage discrete Fourier transform on programmable logic devices". Revista Amazonia Investiga 9, n.º 27 (21 de marzo de 2020): 227–33. http://dx.doi.org/10.34069/ai/2020.27.03.24.

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Let us consider questions, which are connected to the research of terms of hardware and software implementation digital signal processing (DSP) methods. Theoretical basis of this research are methods of non-recursive difference of digital filtration with integer difference coefficients different orders of difference and methods of multistage discrete Fourier transform (DFT) based on such digital filtration. The purpose of the study is the research and formalization of necessary and sufficient condition of lowering hardware costs in hardware and software implementation of methods multistage DFT of digital signals on programmable logic devices (PLD). For reaching the research goal there are used methods of direct search and comparative analysis of results of such realization of methods of multi-stage DFT of digital multi-band signals, while filtering these signals, which are based on their non-recursive difference digital filtering with integer difference values coefficients and different orders of magnitude of difference. There are described abilities and specialties of PLD, which are built using architecture of a coarse-grained or fine-grained architecture or using combined architecture, which connects the convenience of implementing digital processing algorithms signals on the basis of tables of code conversion and reconfigurable memory modules. It is clear that a necessary and sufficient condition of lowering hardware costs in terms of hardware and software realization of methods for multi-stage DFT of digital signals on PLD is the triviality of meanings of integer difference coefficients of a non-recursive difference digital high difference orders’ filtration, which ensure this information. There is mentioned a formula, which allows making such condition. The practical significance of the research results consists of defining the necessary and sufficient condition of lowering hardware costs in terms of hardware and software implementation on PLD methods of multi-stage DFT signals based on their non-recursive digital difference filtering with integer values differential coefficients of various orders of magnitude difference. The novelty of research results lies in formalization of this condition. The reliability of the research results confirms their compliance with the results of well-known developments of DSP methods.

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Chervyakov, Nikolay, Pavel Lyakhov y Nikolay Nagornov. "Analysis of the Quantization Noise in Discrete Wavelet Transform Filters for 3D Medical Imaging". Applied Sciences 10, n.º 4 (11 de febrero de 2020): 1223. http://dx.doi.org/10.3390/app10041223.

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Denoising and compression of 2D and 3D images are important problems in modern medical imaging systems. Discrete wavelet transform (DWT) is used to solve them in practice. We analyze the quantization noise effect in coefficients of DWT filters for 3D medical imaging in this paper. The method for wavelet filters coefficients quantizing is proposed, which allows minimizing resources in hardware implementation by simplifying rounding operations. We develop the method for estimating the maximum error of 3D grayscale and color images DWT with various bits per color (BPC). The dependence of the peak signal-to-noise ratio (PSNR) of the images processing result on wavelet used, the effective bit-width of filters coefficients and BPC is revealed. We derive formulas for determining the minimum bit-width of wavelet filters coefficients that provide a high (PSNR ≥ 40 dB for images with 8 BPC, for example) and maximum (PSNR = ∞ dB) quality of 3D medical imaging by DWT depending on wavelet used. The experiments of 3D tomographic images processing confirmed the accuracy of theoretical analysis. All data are presented in the fixed-point format in the proposed method of 3D medical images DWT. It is making possible efficient, from the point of view of hardware and time resources, the implementation for image denoising and compression on modern devices such as field-programmable gate arrays and application-specific integrated circuits.

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Sajjad, Muhammad, Mohd Zuki Yusoff y Muhammad Ahmed. "A Customized Floating-point Processor Design for FPGA and ASIC based Thermal Compensation in High-precision Sensing". Annals of Emerging Technologies in Computing 5, n.º 1 (1 de enero de 2021): 40–50. http://dx.doi.org/10.33166/aetic.2021.01.004.

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There are many types of sensors which require large dynamic range as well as high accuracy at the same time. Barometric altimeter is an example of such sensors. The signal processing techniques in the sensors are normally implemented using Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). The sensing variable in such type of the sensors is unwantedly environment dependent. So, for ensuring accuracy of the sensors this environmental dependency is minimized using the modeling and compensation techniques. In this work we have proposed a digital architecture for a programmable high precision computational unit which can be implemented in the FPGA or ASIC running the sensing algorithm of the sensors. This architecture can be used to implement polynomial compensation and it also supports reading and writing of the corresponding calibration coefficients even after the development of the sensors. Moreover, the architecture is platform independent. The architecture have been simulated for different FPGAs and ASIC and it has fulfilled the speed, accuracy and programmability requirements of the type of the sensors. The architecture has also been implemented and verified in a prototype of the barometric pressure sensor on Spartan-6 FPGA.

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Yang, Qiangqiang, Yufeng Chen, Zhiyu Huang, Hongwen Yu y Yong Fang. "Low-Resolution Optimization for an Unmanned Aerial Vehicle Communication Network under a Passive Reconfigurable Intelligent Surface and Active Reconfigurable Intelligent Surface". Electronics 13, n.º 10 (8 de mayo de 2024): 1826. http://dx.doi.org/10.3390/electronics13101826.

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This paper investigates the optimization of an unmanned aerial vehicle (UAV) network serving multiple downlink users equipped with single antennas. The network is enhanced by the deployment of either a passive reconfigurable intelligent surface (RIS) or an active RIS. The objective is to jointly design the UAV’s trajectory and the low-bit, quantized, RIS-programmable coefficients to maximize the minimum user rate in a multi-user scenario. To address this optimization challenge, an alternating optimization framework is employed, leveraging the successive convex approximation (SCA) method. Specifically, for the UAV trajectory design, the original non-convex optimization problem is reformulated into an equivalent convex problem through the introduction of slack variables and appropriate approximations. On the other hand, for the RIS-programmable coefficient design, an efficient algorithm is developed using a penalty-based approximation approach. To solve the problems with the proposed optimization, high-performance optimization tools such as CVX are utilized, despite their associated high time complexity. To mitigate this complexity, a low-complexity algorithm is specifically tailored for the optimization of passive RIS-programmable reflecting elements. This algorithm relies solely on closed-form expressions to generate improved feasible points, thereby reducing the computational burden while maintaining reasonable performance. Extensive simulations are created to validate the performance of the proposed algorithms. The results demonstrate that the active RIS-based approach outperforms the passive RIS-based approach. Additionally, for the passive RIS-based algorithms, the low-complexity variant achieves a reduced time complexity with a moderate loss in performance.

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32

Nagornov, N. N. "Defining of the Minimum Wavelet Filter Coefficients Bit-Width for 3D Medical Imaging". INFORMACIONNYE TEHNOLOGII 27, n.º 8 (11 de agosto de 2021): 425–34. http://dx.doi.org/10.17587/it.27.425-434.

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Medical imaging uses a variety of modalities to provide visual information about a patient. Various methods are used to process this data. Many of them are based on discrete wavelet transform (DWT). Its use will allow effective denoising and compression of 2D and 3D images. This paper proposes a new approach to linear time-invariant wavelet filtering using quantized filter coefficients when using which the computational errors have different signs and allow to partially compensate each other as a result of which the processed image is of high quality. The analysis of the quantization noise of the direct multilevel DWT filter coefficients is carried out. The derived formulas demonstrate the relationship between the quantization accuracy of these coefficients and the processing quality of digital 3D images. The derived formulas for calculating the minimum accuracy of the wavelet filter coefficients representation in the computing devices memory allow minimizing the effect of quantization noise on the result of 3D images processing. Modelling of 3D medical tomographic images DWT processing showed that a decrease in the ratio of the average voxel brightness to the maximum allowable value with increasing color depth of images leads to faster achievement of high quality compared to the results of theoretical analysis with an increase in the value of the scaling degree of the wavelet filter coefficients. The obtained theoretical and practical results open up the possibility for reducing the computational complexity of software and hardware implementation of wavelet processing of 3D medical visual data on modern microelectronic devices (field-programmable gate arrays, application-specific integrated circuits, etc.).

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33

Charaabi, Lotfi y Ibtihel Jaziri. "A Simplified Speed Control of Induction Motor based on a Low Cost FPGA". International Journal of Electrical and Computer Engineering (IJECE) 7, n.º 4 (1 de agosto de 2017): 1760. http://dx.doi.org/10.11591/ijece.v7i4.pp1760-1769.

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This paper investigates the development of a simplified speed control of induction motor based on indirect field oriented control (FOC). An original PI-P controller is designed to obtain good performances for speed tracking. Controller coefficients are carried out with analytic approach. The algorithm is implemented using a low cost Field Programmable Gate Array (FPGA). The implementation is followed by an efficient design methodology that offers considerable design advantages. The main advantage is the design of reusable and reconfigurable hardware modules for the control of electrical systems. Experimental results carried on a prototyping platform are given to illustrate the efficiency and the benefits of the proposed approach.

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Guo, Yuanyuan, Dongsheng Wang, Longsheng Wang, Zhiwei Jia, Tong Zhao, Pengfa Chang, Yuncai Wang y Anbang Wang. "Key Space Enhancement of Chaos Communication Using Semiconductor Lasers with Spectrum-Programmable Optoelectronic Feedback". Photonics 10, n.º 4 (26 de marzo de 2023): 370. http://dx.doi.org/10.3390/photonics10040370.

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We propose a scheme for key-space-enhanced chaos secure communication using semiconductor lasers with spectrum-programmable optoelectronic feedback. This feedback consists of multiple parallel optoelectronic feedback loops composed of bandpass filters and radio-frequency amplifiers. The centre frequencies of the filters and gain coefficients of the amplifiers increase the key space. We use 12 parallel filtered feedback loops to analyse the effects of parameter mismatch on the synchronization quality. The simulation result indicates that the key space reaches approximately 2100 at a data rate of 10 Gbit/s, and it can be further enhanced by increasing the number of feedback loops. These results suggest an alternative approach for security-enhanced optical chaos communication.

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35

Meironke, Heiko, Thomas Panten, Martin Hayduk y Frieder Strubel. "Development of a Test Rig for the Measurement of Small Wind Turbines in a Wind Tunnel". Acta Mechanica et Automatica 17, n.º 3 (11 de julio de 2023): 390–94. http://dx.doi.org/10.2478/ama-2023-0044.

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Abstract This paper describes the development, design and function of a test rig for the measurement of small wind turbines in a wind tunnel and presents the first exemplary measurements of the performance characteristics of various horizontal and vertical rotors. A central part of this test rig is the developed control system with an electronic load, which enables an automated recording of the measured values for the evaluation of the power coefficients (cp) and tip-speed ratio (λ) values. Another challenge emerges owing to the known differences in the power spectrum, because the power coefficients of drag rotors (<20%) are different from those of buoyancy rotors (<40%). The system was adapted to the different ranges by means of a stepless switching using various resistors. The entire control and regulation unit was compactly implemented using a programmable logic controller (PLC) and dynamically linked to the operating parameters of the wind tunnel. This enables an automated operation of the wind tunnel during the determination of the performance parameters of the investigated wind turbines.

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36

Augoestien, Nia Gella y Ryan Aditya. "Implementasi Rangkaian CRC (Cyclic Redundancy Check) Generator pada FPGA (Field Programmable Gate Array)". IJEIS (Indonesian Journal of Electronics and Instrumentation Systems) 9, n.º 1 (30 de abril de 2019): 65. http://dx.doi.org/10.22146/ijeis.43906.

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Data integrity in high speed data transmission process is a major requerment that can not be ignored. High speed data transmission is prone to data errors. CRC (Cyclic Redundancy Check) is a mechanism that is often used as a detector errors in data transmission and storage process. When CRC is implemented using embedded software or processor, CRC requires many clock cycles. If CRC Generator implemented in special dedicated hardware, computational time reduced so that it can be met the high speed system communication requirement. This paper propose the design and implementation of CRC generator on FPGA that capable to minimaze computational time. The method is to reduce calculation latency by separating the coefficients of certain digits and calculating directly the result of polinomial key modulo. CRC Generator in this paper was implemented on Xilinx Spartan®-6 Series (XC6LX16-CS324). The modeling results have succeeded to finish computation on 1 clock cycle. Hardware eficiency is achieved 0.38 Gbps/Slice, while the throughput is 3,758 Gbps.

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37

Garg, Rachit, Gaurav Mishra, Neetesh Purohit y Vishal Kesari. "Beam-steering in a three-element circular antenna-array". International Journal of Microwave and Wireless Technologies 7, n.º 1 (14 de marzo de 2014): 45–51. http://dx.doi.org/10.1017/s1759078714000312.

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A simple and volume efficient circular antenna-array design with a low profile programmable beam rotation mechanism was presented. The proper selections of the rotation vector and the excitation coefficients of rectangular array-elements were made for rotation of the beam. The proposed rotation mechanism was capable to rotate the radiation pattern at any desired speed and to transmit in any desired direction, and the design included the ease of construction. Although simulating the radiation pattern using FEKO EM simulator, two basic functions, the power splitter and the introduction of phase difference, were included in feed network of microstrip circuit to divide the power and then individually feeding the each patch after introducing the desired phase difference.

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38

Mirzaei, Shahnam, Ryan Kastner y Anup Hosangadi. "Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs". International Journal of Reconfigurable Computing 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/697625.

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We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.

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39

Marguč, Jaka, Mitja Truntič, Miran Rodič y Miro Milanovič. "FPGA Based Real-Time Emulation System for Power Electronics Converters". Energies 12, n.º 6 (13 de marzo de 2019): 969. http://dx.doi.org/10.3390/en12060969.

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This paper deals with an emulation system for Power Electronics Converters (PEC). The emulation of PECs is performed on a Field-Programmable Gate Array (FPGA) capable of hard real-time operation. To obtain such a system, the converter operation is described using a differential equations-based model designed with the graph theory. Differential equation coefficients are changed according to the type of converter and pulse-width modulation (PWM) signals. The tie-set and incidence matrix approach for the converter modelling is performed to describe the converter operation in a general way. Such approach enables that any type of PECs can be described appropriately. The emulator was verified experimentally by synchronous operation with a real DC-AC converter built for this purposes.

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40

GAO, YA, GUANGQUAN ZHANG, JIE LU, THARAM DILLON y XIANYI ZENG. "A λ-CUT APPROXIMATE ALGORITHM FOR GOAL-BASED BILEVEL RISK MANAGEMENT SYSTEMS". International Journal of Information Technology & Decision Making 07, n.º 04 (diciembre de 2008): 589–610. http://dx.doi.org/10.1142/s0219622008003113.

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Bilevel programming techniques are developed for decentralized decision problems with decision makers located in two levels. Both upper and lower decision makers, termed as leader and follower, try to optimize their own objectives in solution procedure but are affected by those of the other levels. When a bilevel decision model is built with fuzzy coefficients and the leader and/or follower have goals for their objectives, we call it fuzzy goal bilevel (FGBL) decision problem. This paper first proposes a λ-cut set based FGBL model. A programmable λ-cut approximate algorithm is then presented in detail. Based on this algorithm, a FGBL software system is developed to reach solutions for FGBL decision problems. Finally, two examples are given to illustrate the application of the proposed algorithm.

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41

Lee, Shuenn-Yuh, Po-Han Su, Kuan-Lin Huang, Yi-Wen Hung y Ju-Yi Chen. "High-Pass Sigma–Delta Modulator With Techniques of Operational Amplifier Sharing and Programmable Feedforward Coefficients for ECG Signal Acquisition". IEEE Transactions on Biomedical Circuits and Systems 15, n.º 3 (junio de 2021): 443–53. http://dx.doi.org/10.1109/tbcas.2021.3082545.

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42

Rajapaksha, Nilanka, Amila Edirisuriya, Arjuna Madanayake, Renato J. Cintra, Dennis Onen, Ihab Amer y Vassil S. Dimitrov. "Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA". Journal of Electrical and Computer Engineering 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/834793.

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Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.

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43

Poornima, Y. y M. Kamalanathan. "Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications". International Journal of Advance Research and Innovation 7, n.º 2 (2019): 57–60. http://dx.doi.org/10.51976/ijari.721908.

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Recent advances in mobile computing and multimedia applications demand high - performance and low - power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high - performance applications. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high performance applications. The FIR filter performs the weighted summations of input sequences and is widely used in video convolution functions, signal preconditioning, and various communication applications. Recently, due to the high - performance requirement and increasing complexity of DSP and multimedia communication application. In this work, , FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime.

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44

Li, Kewu, Shuang Wang, Xie Han y Zhibin Wang. "Dispersion Measurement of Electro-Optic Coefficient γ22 of Lithium Niobate Based on Photoelastic Modulation". Applied Sciences 10, n.º 1 (4 de enero de 2020): 395. http://dx.doi.org/10.3390/app10010395.

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A novel method for determining the electro-optic (EO) coefficient γ 22 of lithium niobate and its dispersion using photoelastic modulation is presented. A spectroscopic polarimetry was constructed with the photoelastic modulator (PEM), and a monochromator was selected to automatically scan the wavelength of a light source. Phase retardation induced by an EO sample was loaded into the modulation signals to demodulate the EO coefficients. The PEM and data processing were controlled in the same field programmable gate array (FPGA), and the DC and harmonic terms were extracted simultaneously by employing digital phase-locked technology. An experimental system was built to analyze the principle of this scheme in detail. After the modulation phase retardation amplitude of the PEM was precisely calibrated, the EO coefficient γ 22 of a Y-cut lithium niobate crystal plate was measured in the spectral range from 0.42 to 0.8 µm. The experimental results demonstrated that the measurement sensitivity of the system was 1.1 × 10 − 14 m / V for a sampling time of 198.9 ms. Plotting the measured results against the light wavelength, the dispersion of the EO coefficients was obtained similar to the Cauchy dispersion formula γ 22 = 5.31 × 10 − 12 + 4.071 × 10 − 13 λ 2 + 7.184 × 10 − 14 λ 4 in the visible light range. This method is suitable for studying dispersion of the EO coefficients of crystals as well as of thin films and two-dimensional materials.

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45

Korkmaz, Nimet, İsmail Öztürk, Adem Kalinli y Recai Kiliç. "A Comparative Study on Determining Nonlinear Function Parameters of the Izhikevich Neuron Model". Journal of Circuits, Systems and Computers 27, n.º 10 (24 de mayo de 2018): 1850164. http://dx.doi.org/10.1142/s0218126618501645.

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In the literature, the parabolic function of the Izhikevich Neuron Model (IzNM) is transformed to the Piecewise Linear (PWL) functions in order to make digital hardware implementations easier. The coefficients in this PWL functions are identified by utilizing the error-prone classical step size method. In this paper, it is aimed to determine the coefficients of the PWL functions in the modified IzNM by using the stochastic optimization methods. In order to obtain more accurate results, Genetic Algorithm and Artificial Bee Colony Algorithm (GA and ABC) are used as alternative estimation methods, and amplitude and phase errors between the original and the modified IzNMs are specified with a newly introduced error minimization algorithm, which is based on the exponential forms of the complex numbers. In accordance with this purpose, GA and ABC algorithms are run 30 times for each of the 20 behaviors of a neuron. The statistical results of these runs are given in the tables in order to compare the performance of three parameter-search methods and especially to see the effectiveness of the newly introduced error minimization algorithm. Additionally, two basic dynamical neuronal behaviors of the original and the modified IzNMs are realized with a digital programmable device, namely FPGA, by using new coefficients identified by GA and ABC algorithms. Thus, the efficiency of the GA and ABC algorithm for determining the nonlinear function parameters of the modified IzNM are also verified experimentally.

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46

Song, Minhyup, Victor Torres-Company, Rui Wu, Andrew J. Metcalf y Andrew M. Weiner. "Compression of ultra-long microwave pulses using programmable microwave photonic phase filtering with > 100 complex-coefficient taps". Optics Express 22, n.º 6 (11 de marzo de 2014): 6329. http://dx.doi.org/10.1364/oe.22.006329.

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47

Golubičić, Zoran, Slobodan Simić y Aleksa J. Zejak. "Design and EPGA Implementation of Digital Pulse Compression for Band–Pass Radar Signals". Journal of Electrical Engineering 64, n.º 3 (1 de mayo de 2013): 191–95. http://dx.doi.org/10.2478/jee-2013-0028.

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The paper presents fully digitized approach for band-pass discrete coded radar signals. The emphasis is to use one generalized reconfigurable compressor for several different types of signals and different types of receivers. It fits for direct radio frequency receiver (RF) as well as for intermediate frequency (IF) receiver. The system implementation on field programmable gate area (FPGA) let us eliminate special chips previously needed. From the experimental results it is known that this approach appears to work well for matched and mismatched pulse compression and it outstands when timebandwidth product (TB) is of order 1000. A precision of 14 bits has been considered in the input signal and 16 bits in the filter coefficients. It gives the dynamic range of 78 dB and the quantification error less than 0.012%.

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48

Sayed, Alhassan, Tamer Badran, Marie-Minerve Louerat y Hassan Aboushady. "A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay". IEEE Transactions on Circuits and Systems II: Express Briefs 67, n.º 9 (septiembre de 2020): 1559–63. http://dx.doi.org/10.1109/tcsii.2020.3013821.

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49

Rokeakh, A. I. y M. Yu Artyomov. "Precision Hall Effect magnetometer". Review of Scientific Instruments 94, n.º 3 (1 de marzo de 2023): 034702. http://dx.doi.org/10.1063/5.0131896.

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The article presents a Hall effect magnetometer for use in a desktop Electron Paramagnetic Resonance spectrometer with a permanent magnet system and scanning coils. High accuracy and long-term stability at a small size and low cost are achieved through the use of digital signal processing, sequential data filtering in the time and frequency domains, as well as digital correction of raw data based on calibration information. The exciting current of the Hall sensor has the form of an alternating-sign square wave formed by a high-speed H-bridge powered by a stable direct current. Generation of control signals, time selection of data, and their accumulation are performed using Xilinx Field-Programmable Gate Array Artix-7. MicroBlaze embedded 32-bit processor is used to control the magnetometer and interface with adjacent levels of the control system. Taking into account the individual characteristics of the sensor, including the offset voltage, the nonlinearity of the magnetic sensitivity, and their temperature dependences, is carried out by correcting the data obtained by calculating a polynomial depending on the raw magnitude of the field induction and the temperature of the sensor. The polynomial coefficients are individual for each sensor, are determined once during the calibration process, and are stored in the dedicated Electrically Erasable Programmable Read-Only Memory. The magnetometer has a high resolution of 0.1 µT and an absolute measurement error of not exceeding 6 µT.

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50

Chervyakov, N. I., P. A. Lyakhov, N. N. Nagornov, M. V. Valueva y G. V. Valuev. "Hardware implementation of a convolutional neural network using calculations in the residue number system". Computer Optics 43, n.º 5 (octubre de 2019): 857–68. http://dx.doi.org/10.18287/2412-6179-2019-43-5-857-868.

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Modern convolutional neural networks architectures are very resource intensive which limits the possibilities for their wide practical application. We propose a convolutional neural network architecture in which the neural network is divided into hardware and software parts to increase performance and reduce the cost of implementation resources. We also propose to use the residue number system in the hardware part to implement the convolutional layer of the neural network for resource costs reducing. A numerical method for quantizing the filters coefficients of a convolutional network layer is proposed to minimize the influence of quantization noise on the calculation result in the residue number system and determine the bit-width of the filters coefficients. This method is based on scaling the coefficients by a fixed number of bits and rounding up and down. The operations used make it possible to reduce resources in hardware implementation due to the simplifying of their execution. All calculations in the convolutional layer are performed on numbers in a fixed-point format. Software simulations using Matlab 2017b showed that convolutional neural network with a minimum number of layers can be quickly and successfully trained. Hardware implementation using the field-programmable gate array Kintex7 xc7k70tfbg484-2 showed that the use of residue number system in the convolutional layer of the neural network reduces the hardware costs by 32.6% compared with the traditional approach based on the two’s complement representation. The research results can be applied to create effective video surveillance systems, for recognizing handwriting, individuals, objects and terrain.

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