Artículos de revistas sobre el tema "Coarse Grained Reconfigurable arrays"
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Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis y Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays". Microprocessors and Microsystems 33, n.º 2 (marzo de 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.
Texto completoTheocharis, Panagiotis y Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays". ACM Transactions on Architecture and Code Optimization 13, n.º 2 (27 de junio de 2016): 1–26. http://dx.doi.org/10.1145/2893475.
Texto completoAnsaloni, Giovanni, Kazuyuki Tanimura, Laura Pozzi y Nikil Dutt. "Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, n.º 12 (diciembre de 2012): 1803–16. http://dx.doi.org/10.1109/tcad.2012.2209886.
Texto completoEgger, Bernhard, Eunjin Song, Hochan Lee y Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs". ACM SIGPLAN Notices 53, n.º 6 (7 de diciembre de 2018): 76–88. http://dx.doi.org/10.1145/3299710.3211342.
Texto completoFilho, J. O., S. Masekowsky, T. Schweizer y W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, n.º 9 (septiembre de 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.
Texto completoDimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis y Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays". Journal of Supercomputing 48, n.º 2 (16 de mayo de 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.
Texto completoQu, Tongzhou, Zibin Dai, Yanjiang Liu y Lin Chen. "A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays". Electronics 11, n.º 19 (30 de septiembre de 2022): 3144. http://dx.doi.org/10.3390/electronics11193144.
Texto completoLopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto y José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10, n.º 6 (12 de marzo de 2021): 669. http://dx.doi.org/10.3390/electronics10060669.
Texto completoDe Sutter, Bjorn, Paul Coene, Tom Vander Aa y Bingfeng Mei. "Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays". ACM SIGPLAN Notices 43, n.º 7 (27 de junio de 2008): 151–60. http://dx.doi.org/10.1145/1379023.1375678.
Texto completoKissler, Dmitrij, Daniel Gran, Zoran Salcic, Frank Hannig y Jürgen Teich. "Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays". IEEE Embedded Systems Letters 3, n.º 2 (junio de 2011): 58–61. http://dx.doi.org/10.1109/les.2011.2124438.
Texto completoYang, Chen, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao y Shaojun Wei. "Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array". Journal of Circuits, Systems and Computers 24, n.º 03 (10 de febrero de 2015): 1550043. http://dx.doi.org/10.1142/s0218126615500437.
Texto completoChoi, Kiyoung. "Coarse-Grained Reconfigurable Array: Architecture and Application Mapping". IPSJ Transactions on System LSI Design Methodology 4 (2011): 31–46. http://dx.doi.org/10.2197/ipsjtsldm.4.31.
Texto completoDöbrich, Stefan y Christian Hochberger. "Low-Complexity Online Synthesis for AMIDAR Processors". International Journal of Reconfigurable Computing 2010 (2010): 1–15. http://dx.doi.org/10.1155/2010/953693.
Texto completoHartmann, Matthias, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic y Christian Hochberger. "Still Image Processing on Coarse-Grained Reconfigurable Array Architectures". Journal of Signal Processing Systems 60, n.º 2 (11 de diciembre de 2008): 225–37. http://dx.doi.org/10.1007/s11265-008-0309-0.
Texto completoFerreira, Ricardo S., João M. P. Cardoso, Alex Damiany, Julio Vendramini y Tiago Teixeira. "Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks". Journal of Systems Architecture 57, n.º 8 (septiembre de 2011): 761–77. http://dx.doi.org/10.1016/j.sysarc.2011.03.006.
Texto completoZhou, Li, Dongpei Liu, Jianfeng Zhang y Hengzhu Liu. "Application-specific coarse-grained reconfigurable array: architecture and design methodology". International Journal of Electronics 102, n.º 6 (8 de agosto de 2014): 897–910. http://dx.doi.org/10.1080/00207217.2014.942885.
Texto completoBae, Inpyo, Barend Harris, Hyemi Min y Bernhard Egger. "Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, n.º 11 (noviembre de 2018): 2301–10. http://dx.doi.org/10.1109/tcad.2018.2857278.
Texto completoVranjković, Vuk S., Rastislav J. R. Struharik y Ladislav A. Novak. "Reconfigurable Hardware for Machine Learning Applications". Journal of Circuits, Systems and Computers 24, n.º 05 (8 de abril de 2015): 1550064. http://dx.doi.org/10.1142/s0218126615500644.
Texto completoMunaf, S., Dr A. Bharathi y Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture". International Journal of Electrical and Electronics Research 4, n.º 1 (31 de marzo de 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.
Texto completoHannig, Frank, Hritam Dutta y Jurgen Teich. "Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology". International Journal of Embedded Systems 2, n.º 1/2 (2006): 114. http://dx.doi.org/10.1504/ijes.2006.010170.
Texto completoKissler, Dmitrij, Frank Hannig y Jürgen Teich. "Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays". Journal of Low Power Electronics 7, n.º 1 (1 de febrero de 2011): 29–40. http://dx.doi.org/10.1166/jolpe.2011.1114.
Texto completoKIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE". Journal of Circuits, Systems and Computers 22, n.º 03 (marzo de 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.
Texto completoPatel, Kunjan, Séamas McGettrick y C. J. Bleakley. "Rapid functional modelling and simulation of coarse grained reconfigurable array architectures". Journal of Systems Architecture 57, n.º 4 (abril de 2011): 383–91. http://dx.doi.org/10.1016/j.sysarc.2011.02.006.
Texto completoQu, Tongzhou, Zibin Dai, Chen Lin y Anqi Yin. "Adaptive loop pipeline control mechanism for Coarse-Grained Reconfigurable Block Cipher Array". Journal of Physics: Conference Series 1971, n.º 1 (1 de julio de 2021): 012051. http://dx.doi.org/10.1088/1742-6596/1971/1/012051.
Texto completoYang, Chen, LeiBo Liu, ShouYi Yin y ShaoJun Wei. "Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays". Science China Physics, Mechanics & Astronomy 57, n.º 12 (21 de octubre de 2014): 2214–27. http://dx.doi.org/10.1007/s11433-014-5610-2.
Texto completoRouson, Damian W. I. y Yi Xiong. "Design Metrics in Quantum Turbulence Simulations: How Physics Influences Software Architecture". Scientific Programming 12, n.º 3 (2004): 185–96. http://dx.doi.org/10.1155/2004/910505.
Texto completoPatel, Kunjan y Chris J. Bleakley. "Coarse Grained Reconfigurable Array Based Architecture for Low Power Real-Time Seizure Detection". Journal of Signal Processing Systems 82, n.º 1 (7 de marzo de 2015): 55–68. http://dx.doi.org/10.1007/s11265-015-0981-9.
Texto completoLiu, Leibo, Chen Yang, Shouyi Yin y Shaojun Wei. "CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, n.º 6 (junio de 2018): 1171–84. http://dx.doi.org/10.1109/tcad.2017.2748026.
Texto completoYang, Chen, Leibo Liu, Kai Luo, Shouyi Yin y Shaojun Wei. "CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays". IEEE Transactions on Parallel and Distributed Systems 28, n.º 1 (1 de enero de 2017): 29–43. http://dx.doi.org/10.1109/tpds.2016.2554278.
Texto completoWeinhardt, Markus, Mohamed Messelka y Philipp Käsgen. "CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor". Electronics 10, n.º 21 (23 de octubre de 2021): 2590. http://dx.doi.org/10.3390/electronics10212590.
Texto completoLu, Yanan, Leibo Liu, Yangdong Deng, Jian Weng, Shouyi Yin, Yiyu Shi y Shaojun Wei. "Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays". IEEE Transactions on Parallel and Distributed Systems 29, n.º 10 (1 de octubre de 2018): 2360–72. http://dx.doi.org/10.1109/tpds.2018.2822708.
Texto completoLi, Zeyu, Junjie Wang, Zhao Huang, Nan Luo y Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware". Applied Sciences 12, n.º 13 (29 de junio de 2022): 6601. http://dx.doi.org/10.3390/app12136601.
Texto completoMehta, Dinesh P., Carl Shetters y Donald W. Bouldin. "Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs". VLSI Design 2013 (25 de diciembre de 2013): 1–13. http://dx.doi.org/10.1155/2013/249592.
Texto completoLiu, LeiBo, YanSheng Wang, ShouYi Yin, Min Zhu, Xing Wang y ShaoJun Wei. "Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture". Science China Information Sciences 57, n.º 10 (6 de septiembre de 2014): 1–18. http://dx.doi.org/10.1007/s11432-013-4973-8.
Texto completoMudza, Zbigniew y Rafał Kiełbik. "Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions". Electronics 11, n.º 8 (16 de abril de 2022): 1261. http://dx.doi.org/10.3390/electronics11081261.
Texto completoHo, H., V. Szwarc y T. Kwasniewski. "A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications". International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/529512.
Texto completoZhao, Zhongyuan, Weiguang Sheng, Jinchao Li, Pengfei Ye, Qin Wang y Zhigang Mao. "Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA". Electronics 10, n.º 18 (9 de septiembre de 2021): 2210. http://dx.doi.org/10.3390/electronics10182210.
Texto completoTehre, Vaishali y Ravindra Kshirsagar. "Survey on Coarse Grained Reconfigurable Architectures". International Journal of Computer Applications 48, n.º 16 (30 de junio de 2012): 1–7. http://dx.doi.org/10.5120/7429-0104.
Texto completoJong-eun Lee, Kiyoung Choi y N. D. Dutt. "Compilation approach for coarse-grained reconfigurable architectures". IEEE Design & Test of Computers 20, n.º 1 (enero de 2003): 26–33. http://dx.doi.org/10.1109/mdt.2003.1173050.
Texto completoPaek, Jong Kyung, Kiyoung Choi y Jongeun Lee. "Binary acceleration using coarse-grained reconfigurable architecture". ACM SIGARCH Computer Architecture News 38, n.º 4 (14 de septiembre de 2010): 33–39. http://dx.doi.org/10.1145/1926367.1926374.
Texto completoAnsaloni, Giovanni, Paolo Bonzini y Laura Pozzi. "EGRA: A Coarse Grained Reconfigurable Architectural Template". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, n.º 6 (junio de 2011): 1062–74. http://dx.doi.org/10.1109/tvlsi.2010.2044667.
Texto completoWang, Xing, Lei Bo Liu, Shou Yi Yin, Min Zhu y Shao Jun Wei. "H.264/AVC Intra Predictor on a Coarse-Grained Reconfigurable Multi-Media System". Advanced Materials Research 546-547 (julio de 2012): 469–74. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.469.
Texto completoYIN, Shouyi, Chongyong YIN, Leibo LIU, Min ZHU y Shaojun WEI. "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture". IEICE Transactions on Information and Systems E95-D, n.º 2 (2012): 335–44. http://dx.doi.org/10.1587/transinf.e95.d.335.
Texto completoWang, Chao, Peng Cao y Jun Yang. "Efficient AES cipher on coarse-grained reconfigurable architecture". IEICE Electronics Express 14, n.º 11 (2017): 20170449. http://dx.doi.org/10.1587/elex.14.20170449.
Texto completoHussain, Shaik Rizwan y Jahangir Badashah Syed. "Design and Applications of Coarse-Grained Reconfigurable Architectures". International Journal of Scientific Research 2, n.º 12 (1 de junio de 2012): 198–201. http://dx.doi.org/10.15373/22778179/dec2013/61.
Texto completoAtak, Oguzhan y Abdullah Atalar. "BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, n.º 7 (julio de 2013): 1285–98. http://dx.doi.org/10.1109/tvlsi.2012.2207748.
Texto completoAkbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram y Muhammad Shafique. "Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures". IEEE Micro 38, n.º 6 (1 de noviembre de 2018): 63–72. http://dx.doi.org/10.1109/mm.2018.2873951.
Texto completoSim, Hyeonuk, Hongsik Lee, Seongseok Seo y Jongeun Lee. "Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, n.º 7 (julio de 2016): 1092–104. http://dx.doi.org/10.1109/tcad.2015.2504918.
Texto completoSeveso, Luigi, Dardo Goyeneche y Karol Życzkowski. "Coarse-grained entanglement classification through orthogonal arrays". Journal of Mathematical Physics 59, n.º 7 (julio de 2018): 072203. http://dx.doi.org/10.1063/1.5006890.
Texto completoKOJIMA, Takuya y Hideharu AMANO. "A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures". IEICE Transactions on Information and Systems E102.D, n.º 7 (1 de julio de 2019): 1247–56. http://dx.doi.org/10.1587/transinf.2018edp7336.
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