Literatura académica sobre el tema "Coarse Grained Reconfigurable arrays"
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Artículos de revistas sobre el tema "Coarse Grained Reconfigurable arrays"
Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis y Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays". Microprocessors and Microsystems 33, n.º 2 (marzo de 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.
Texto completoTheocharis, Panagiotis y Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays". ACM Transactions on Architecture and Code Optimization 13, n.º 2 (27 de junio de 2016): 1–26. http://dx.doi.org/10.1145/2893475.
Texto completoAnsaloni, Giovanni, Kazuyuki Tanimura, Laura Pozzi y Nikil Dutt. "Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, n.º 12 (diciembre de 2012): 1803–16. http://dx.doi.org/10.1109/tcad.2012.2209886.
Texto completoEgger, Bernhard, Eunjin Song, Hochan Lee y Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs". ACM SIGPLAN Notices 53, n.º 6 (7 de diciembre de 2018): 76–88. http://dx.doi.org/10.1145/3299710.3211342.
Texto completoFilho, J. O., S. Masekowsky, T. Schweizer y W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, n.º 9 (septiembre de 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.
Texto completoDimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis y Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays". Journal of Supercomputing 48, n.º 2 (16 de mayo de 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.
Texto completoQu, Tongzhou, Zibin Dai, Yanjiang Liu y Lin Chen. "A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays". Electronics 11, n.º 19 (30 de septiembre de 2022): 3144. http://dx.doi.org/10.3390/electronics11193144.
Texto completoLopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto y José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10, n.º 6 (12 de marzo de 2021): 669. http://dx.doi.org/10.3390/electronics10060669.
Texto completoDe Sutter, Bjorn, Paul Coene, Tom Vander Aa y Bingfeng Mei. "Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays". ACM SIGPLAN Notices 43, n.º 7 (27 de junio de 2008): 151–60. http://dx.doi.org/10.1145/1379023.1375678.
Texto completoKissler, Dmitrij, Daniel Gran, Zoran Salcic, Frank Hannig y Jürgen Teich. "Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays". IEEE Embedded Systems Letters 3, n.º 2 (junio de 2011): 58–61. http://dx.doi.org/10.1109/les.2011.2124438.
Texto completoTesis sobre el tema "Coarse Grained Reconfigurable arrays"
Lee, Jong-Suk Mark. "FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications". Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/77094.
Texto completoPh. D.
Saraswat, Rohit. "A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures". DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/689.
Texto completoDas, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems". Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.
Texto completoEmerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
Dogan, Rabia. "System Level Exploration of RRAM for SRAM Replacement". Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.
Texto completoZain-ul-Abdin. "Programming of coarse-grained reconfigurable architectures". Doctoral thesis, Örebro universitet, Akademin för naturvetenskap och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-15246.
Texto completoUl-Abdin, Zain. "Programming of Coarse-Grained Reconfigurable Architectures". Doctoral thesis, Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-15050.
Texto completoGuo, Yuanqing. "Mapping applications to a coarse-grained reconfigurable architecture". Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/57121.
Texto completoBag, Zeki Ozan. "Energy-Aware Coarse Grained Reconfigurable Architectures Using Dynamically Reconfigurable Isolation Cells". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-108217.
Texto completoPlessl, Christian [Verfasser]. "Hardware Virtualization on a Coarse-Grained Reconfigurable Processor / Christian Plessl". Aachen : Shaker, 2006. http://d-nb.info/1166513963/34.
Texto completoYadav, Anil. "Exploration Of Energy And Area Efficient Techniques For Coarse-grained Reconfigurable Fabrics". Thesis, University of North Texas, 2011. https://digital.library.unt.edu/ark:/67531/metadc103413/.
Texto completoLibros sobre el tema "Coarse Grained Reconfigurable arrays"
1964-, Soudris Dimitrios y Vassiliadis Stamatis, eds. Fine- and coarse-grain reconfigurable computing. [New York?]: Springer, 2007.
Buscar texto completoPlessl, Christian. Hardware virtualization on a coarse-grained reconfigurable processor. Aachen: Shaker, 2006.
Buscar texto completoWijtvliet, Mark, Henk Corporaal y Akash Kumar. Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79774-4.
Texto completoN, Mahapatra Rabi, ed. Design of low-power coarse-grained reconfigurable architectures. Boca Raton, FL: CRC Press, 2011.
Buscar texto completo(Foreword), Y. Patt, J. Smith (Foreword), M. Valero (Foreword), Stamatis Vassiliadis (Editor) y Dimitrios Soudris (Editor), eds. Fine- and Coarse-Grain Reconfigurable Computing. Springer, 2007.
Buscar texto completoPatt, Y., J. Smith, M. Valero, Dimitrios Soudris y Stamatis Vassiliadis. Fine- and Coarse-Grain Reconfigurable Computing. Springer London, Limited, 2007.
Buscar texto completoPatt, Y., J. Smith, M. Valero, Dimitrios Soudris y Stamatis Vassiliadis. Fine- and Coarse-Grain Reconfigurable Computing. Springer Netherlands, 2014.
Buscar texto completoMahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.
Buscar texto completoMahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2017.
Buscar texto completoMahapatra, Rabi N. y Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.
Buscar texto completoCapítulos de libros sobre el tema "Coarse Grained Reconfigurable arrays"
Sousa, Éricles, Frank Hannig y Jürgen Teich. "Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays". En System Level Design from HW/SW to Memory for Embedded Systems, 218–29. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-90023-0_18.
Texto completoDe Sutter, Bjorn, Praveen Raghavan y Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures". En Handbook of Signal Processing Systems, 553–92. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6859-2_18.
Texto completoDe Sutter, Bjorn, Praveen Raghavan y Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures". En Handbook of Signal Processing Systems, 449–84. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6345-1_17.
Texto completoSutter, Bjorn De, Praveen Raghavan y Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures". En Handbook of Signal Processing Systems, 427–72. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91734-4_12.
Texto completoKim, Yongjoo, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon y Yunheung Paek. "Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays". En High Performance Embedded Architectures and Compilers, 171–85. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11515-8_14.
Texto completoNiedermeier, A., Jan Kuper y Gerard J. M. Smit. "A Dataflow Inspired Programming Paradigm for Coarse-Grained Reconfigurable Arrays". En Lecture Notes in Computer Science, 275–82. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05960-0_29.
Texto completoMiyasaka, Yukio, Masahiro Fujita, Alan Mishchenko y John Wawrzynek. "SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays". En VLSI-SoC: Design Trends, 113–31. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81641-4_6.
Texto completoPatel, Kunjan y C. J. Bleakley. "Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures". En Lecture Notes in Computer Science, 351–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12133-3_33.
Texto completoRistimäki, T. y J. Nurmi. "Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array". En Field Programmable Logic and Application, 1130–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_146.
Texto completoBouwens, Frank, Mladen Berekovic, Bjorn De Sutter y Georgi Gaydadjiev. "Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array". En High Performance Embedded Architectures and Compilers, 66–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-77560-7_6.
Texto completoActas de conferencias sobre el tema "Coarse Grained Reconfigurable arrays"
Tan, Cheng, Nicolas Bohm Agostini, Jeff Zhang, Marco Minutoli, Vito Giovanni Castellana, Chenhao Xie, Tong Geng, Ang Li, Kevin Barker y Antonino Tumeo. "OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays". En 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2021. http://dx.doi.org/10.1109/asap52443.2021.00029.
Texto completoAnsaloni, G., L. Pozzi, K. Tanimura y N. Dutt. "Slack-aware scheduling on Coarse Grained Reconfigurable Arrays". En 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763323.
Texto completoDimitroulakos, Gregory, Nikos Kostaras, Michalis D. Galanis y Costas E. Goutis. "Compiler assisted architectural exploration for coarse grained reconfigurable arrays". En the 17th great lakes symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1228784.1228827.
Texto completoVan Essen, Brian, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling y Scott Hauck. "Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays". En 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272293.
Texto completoSousa, Ericles, Alexandru Tanase, Frank Hannig y Jurgen Teich. "A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays". En 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2017. http://dx.doi.org/10.1109/reconfig.2017.8279768.
Texto completoJian, Liu, Leibo Liu, Yanan Lu, Jianfeng Zhu y Shaojun Wei. "Comparing Branch Predictors for Distributed-Controlled Coarse-Grained Reconfigurable Arrays". En 2019 IEEE 11th International Conference on Communication Software and Networks (ICCSN). IEEE, 2019. http://dx.doi.org/10.1109/iccsn.2019.8905283.
Texto completoEgger, Bernhard, Eunjin Song, Hochan Lee y Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs". En LCTES '18: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2018. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3211332.3211342.
Texto completoStock, Florian y Andreas Koch. "Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays". En 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311194.
Texto completoHeyse, Karel, Tom Davidson, Elias Vansteenkiste, Karel Bruneel y Dirk Stroobandt. "Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS". En 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2013. http://dx.doi.org/10.1109/fpl.2013.6645516.
Texto completoKim, Hee-Seok, Minwook Ahn, John A. Stratton y Wen-mei W. Hwu. "Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays". En 2012 International Conference on Field-Programmable Technology (FPT). IEEE, 2012. http://dx.doi.org/10.1109/fpt.2012.6412155.
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