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Literatura académica sobre el tema "Co-Conception Matérielle"
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Artículos de revistas sobre el tema "Co-Conception Matérielle"
Impedovo, Marie Antonietta y Seng Chee Tan. "Conception d'apprentissage pour la co-agence enseignant-élève dans les espaces hybrides". Revue internationale du CRIRES : innover dans la tradition de Vygotsky 7, n.º 1 (19 de junio de 2023): 24–38. http://dx.doi.org/10.51657/ric.v7i1.51883.
Texto completoFrick, V. y B. Boyer. "Conception de système embarqué sur cible FPGA : une approche par compétences". J3eA 21 (2022): 1022. http://dx.doi.org/10.1051/j3ea/20221022.
Texto completoDorsa, Mariana, Tiffany Lacamoire, Marie Duvivier, Alexia Zucchello, Michel Naiditch, Thomas Sannié, Andréa Limbourg y Pierre Yves Traynard. "Co-construction et « perspective patient » : la démarche d’intervention du Pôle de ressources en éducation thérapeutique du patient d’Île-de-France". Education Thérapeutique du Patient - Therapeutic Patient Education 14, n.º 2 (2022): 20402. http://dx.doi.org/10.1051/tpe/2023004.
Texto completoDeschênes, Marie-France y Johanne Goudreau. "L’apprentissage du raisonnement clinique infirmier dans le cadre d’un dispositif éducatif numérique basé sur la concordance de scripts". Pédagogie Médicale 21, n.º 3 (2020): 143–57. http://dx.doi.org/10.1051/pmed/2020041.
Texto completoAuclair, Isabelle. "Féminismes". Anthropen, 2019. http://dx.doi.org/10.17184/eac.anthropen.096.
Texto completoFougeyrollas, Patrick. "Handicap". Anthropen, 2016. http://dx.doi.org/10.17184/eac.anthropen.013.
Texto completoTesis sobre el tema "Co-Conception Matérielle"
Mao, Yuxiao. "Détection dynamique d'attaques logicielles et matérielles basée sur l'analyse de signaux microarchitecturaux". Thesis, Toulouse, INSA, 2022. http://www.theses.fr/2022ISAT0015.
Texto completoIn recent years, computer systems have evolved quickly. This evolution concerns different layers of the system, both software (operating systems and user programs) and hardware (microarchitecture design and chip technology). While this evolution allows to enrich the functionalities and improve the performance, it has also increased the complexity of the systems. It is difficult, if not impossible, to fully understand a particular modern computer system, and a greater complexity also stands for a larger attack surface for hackers. While most of the attacks target software vulnerabilities, over the past two decades, attacks exploiting hardware vulnerabilities have emerged and demonstrated their serious impact. For example, in 2018, the Spectre and Meltdown attacks have been disclosed, that exploited vulnerabilities in the microarchitecture layer to allow powerful arbitrary reads, and highlighted the security issues that can arise from certain optimizations of system microarchitecture. Detecting and preventing such attacks is not intuitive and there are many challenges to deal with: (1) the great difficulty in identifying sources of vulnerability implied by the high level of complexity and variability of different microarchitectures; (2) the significant impact of countermeasures on overall performance and on modifications to the system's hardware microarchitecture generally not desired; and (3) the necessity to design countermeasures able to adapt to the evolution of the attack after deployment of the system. To face these challenges, this thesis focuses on the use of information available at the microarchitecture level to build efficient attack detection methods.In particular, we describe a framework allowing the dynamic detection of attacks that leave fingerprints at the system's microarchitecture layer. This framework proposes: (1) the use microarchitectural information for attack detection, which can effectively cover attacks targeting microarchitectural vulnerabilities; (2) a methodology that assists designers in selecting relevant microarchitectural information to extract; (3) the use of dedicated connections for the transmission of information extracted, in order to ensure high transmission bandwidth and prevent data loss; and (4) the use of reconfigurable hardware in conjunction with software to implement attack detection logic. This combination (composing to the so-called detection module) reduces the performance overhead through hardware acceleration, and allows updating detection logic during the system lifetime with reconfiguration in order to adapt to the evolution of attacks. We present in detail the proposed architecture and modification needed on the operating system, the methodology for selecting appropriate microarchitectural information and for integrating this framework into a specific computer system, and we describe how the final system integrating our detection module is able to detect attacks and adapt to attack evolution. This thesis also provides two use-case studies implemented on a prototype (based on a RISC-V core with a Linux operating system) on an FPGA. It shows that, thanks to the analysis of microarchitectural information, relatively simple logic implemented in the detection module is sufficient to detect different classes of attacks (cache side-channel attack and ROP attack)
Cornevaux-Juignet, Franck. "Hardware and software co-design toward flexible terabits per second traffic processing". Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2018. http://www.theses.fr/2018IMTA0081/document.
Texto completoThe reliability and the security of communication networks require efficient components to finely analyze the traffic of data. Service diversification and through put increase force network operators to constantly improve analysis systems in order to handle through puts of hundreds,even thousands of Gigabits per second. Commonly used solutions are software oriented solutions that offer a flexibility and an accessibility welcome for network operators, but they can no more answer these strong constraints in many critical cases.This thesis studies architectural solutions based on programmable chips like Field-Programmable Gate Arrays (FPGAs) combining computation power and processing flexibility. Boards equipped with such chips are integrated into a common software/hardware processing flow in order to balance short comings of each element. Network components developed with this innovative approach ensure an exhaustive processing of packets transmitted on physical links while keeping the flexibility of usual software solutions, which was never encountered in the previous state of theart.This approach is validated by the design and the implementation of a flexible packet processing architecture on FPGA. It is able to process any packet type at the cost of slight resources over consumption. It is moreover fully customizable from the software part. With the proposed solution, network engineers can transparently use the processing power of an hardware accelerator without the need of prior knowledge in digital circuit design
Porquet, Joël. "Architecture de sécurité dynamique pour systèmes multiprocesseurs intégrés sur puce". Phd thesis, Université Pierre et Marie Curie - Paris VI, 2010. http://tel.archives-ouvertes.fr/tel-00574088.
Texto completoGourlet, Pauline. "Montrer le faire, construire l’agir : une approche développementale de la conception mise en œuvre à l’école primaire". Thesis, Paris 8, 2018. http://www.theses.fr/2018PA080023/document.
Texto completo- Why do you like making videos?- Mmmh, because… I can be seen, and it feels good to see people.- Me, it is because I would like to be a movie star. In a first graders classroom, a teacher and his pupils experiment the use of a smartphone to efficiently enhance the way pupils learn to write. I meet with him in November 2015 and I introduce a digital system in the classroom, aiming at mediating pupils’ production of digital content. This dissertation focuses on the design and evaluation of digital tools and addresses the following issue: how to design in order to develop educational activities in a sustainable way? And what roles do the artifacts play in this development?I propose a developmental approach to design, that envisions a change of object: instead of focusing on artifacts, I suggest that designing in a developmental perspective is concerns by the configurations of new forms of collective action. In this study, I apply this perspective in an elementary classroom in a public school in Paris. Aligned with this approach to design, I draw a methodology that helps me transform as much as study situated ways of acting. This methodology, closely related to action research, borrows from Participatory Design practices and values combined with a Cultural-Historical Activity Theory framework (CHAT). This study investigates the developmental processes of both artifacts and people in this first graders classroom, by tracking how artifacts are used and redesigned through the classroom’s practices, as much as they transform them. I conclude by discussing the benefit of adopting such a design approach, considering design as a situated, continuous and distributed process
Dauphin, Benjamin. "Liveness analysis techniques and run-time environment for memory management of dataflow applications". Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT004.
Texto completoThis thesis has been realized at Télécom Paris and it has been financed by Nokia Bell Labs France. It studies different techniques to handle the issue of deadlocks and memory shortages in computing systems. Its work is motivated by the rise over the past decades of heterogeneous and Non-Uniform Memory Access (NUMA) architectures in all varieties computing systems, from embedded systems running on Multi-Processor Systems on a Chip (MPSoCs) to distributed High-Performance Computing (HPC) systems. We focus more specifically on the issue of memory shortages in embedded systems used for Digital Signal Processing, but our contributions could be applied to different applications and platforms.The contributions of this thesis are threefold:(1) we present a deadlock prevention technique based on the analysis of cliques in Memory Exclusion Graphs, which are graphs representing buffers allocated in memory and whether they might get simultaneously allocated;(2) we present an optimization on the conventional liveness analysis for memory shortages, allowing to execute the liveness analysis in reasonable time for larger systems than previously supported;(3) we developed a deadlock avoidance strategy using results from the liveness analysis, and integrated it into an experimental run-time environment.We evaluate our first and second contributions in comparison to an existing state-of-the-art tool.Finally we propose multiple leads to improve on the contributions of the thesis
Mba, Mathieu Leonel. "Génération automatique de plate-forme matérielles distribuées pour des applications de traitement du signal". Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS341.
Texto completoLocal languages or mother tongues of individuals play an essential role in their fulfillment in their various socio-economic activities. African languages and specifically Cameroonian languages are exposed to disappearance in favor of foreign languages adopted as official languages after independence. This is why it is essential to digitalize and integrate them into the majority of dematerialized services for their sustainability. Speech recognition, widely used as a human-machine interface, can be not only a tool for integrating local languages into applications but also a tool for collecting and digitizing corpora. Embedded systems are the preferred environment for deploying applications that use this human-machine interface. This implies that it is necessary to take measures (through the reduction of the reaction time) to satisfy the real-time constraint very often met in this type of application. Two approaches exist for the reduction of the application's response time, namely parallelization and the use of efficient hardware architectures. In this thesis, we exploit a hybrid approach to reduce the response time of an application. We do this by parallelizing this application and implementing it on a reconfigurable architecture. An architecture whose implementation languages are known to be low-level. Moreover, given the multitude of problems posed by the implementation of parallel systems on reconfigurable architecture, there is a problem with design productivity for the engineer. In this thesis, to implement a real-time speech recognition system on an embedded system, we propose an approach for the productive implementation of parallel applications on reconfigurable architecture. Our approach exploits MATIP, a platform-based design tool, as an FPGA Overlay based on high-level synthesis. We exploit this approach to implement a parallel model of a feature extraction algorithm for the recognition of tonal languages (characteristic of the majority of Cameroonian languages). The experimentation of this implementation on isolated words of the Kóló language, in comparison to other implementations (software version and hardware IP), shows that our approach is not only productive in implementation time but also the obtained parallel application is efficient in processing time. This is the reason why we implemented XMATIP an extension of MATIP to make this approach compatible with hardware-software co-design and co-synthesis
Héneault, Yannick. "Picasso, un outil de co-design matériel/logiciel pour la conception de systèmes embarqués". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ65582.pdf.
Texto completoRomdhani, Mohamed. "Ingénierie des systèmes complexes avec la méthode de conception concurrente co-design matériel/logiciel : application aux calculateurs embarqués". Grenoble INPG, 1996. http://www.theses.fr/1996INPG0211.
Texto completoTaha, Safouan. "Modélisation conjointe logiciel/matériel de systèmes temps réel". Thesis, Lille 1, 2008. http://www.theses.fr/2008LIL10016/document.
Texto completoThis PhD work focuses on the hardware support when modeling real-time systems. To improve the development of hardware and to communicate architectural intends to the software flow, we adopted the model driven engineering for design, simulation and implementation of hardware platforms. We have first defined a modeling language HRM (Hardware Resource Model) that describes hardware platforms with different views and at different levels of detail. Then, we developed a methodology based on HRM to help users in the construction of their platforms models. We have also developed automated tools for the simulation of these hardware models. Finally, we provide an efficient process of unification between HRM and the recent standard of hardware implementation IP-XACT. As our purpose is to take into consideration the hardware properties during the system design, we have specified rules and constraints that govem allocation of software entities onto hardware resources. After that, we proposed mechanisms to adapt inadequate configurations. Finally, we illustrate all these contributions within the same case study, which is a robots chain. It is realtime, embedded, multi-tasking, distributed, repetitive and configurable system
Aljer, Ammar. "Co-design et raffinement en B : BHDL tool, plateforme pourr la conception de composants numériques". Lille 1, 2004. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/2004/50376-2004-Aljer.pdf.
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