Tesis sobre el tema "CMOS interface"
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Berber, Feyza. "CMOS temperature sensor utilizing interface-trap charge pumping". Texas A&M University, 2005. http://hdl.handle.net/1969.1/4157.
Texto completoZhao, Dongning. "A low-noise CMOS interface for capacitive microaccelerometers". Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31715.
Texto completoHafizović, Sadik. "Neural interface and atomic-force microscope in CMOS technology /". Zürich : Physical Electronics Laboratory, ETH Zürich, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16806.
Texto completoSilay, Kanber Mithat. "High Performance Cmos Capacitive Interface Circuits For Mems Gyroscopes". Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/2/12607518/index.pdf.
Texto completom CMOS process. Fabricated interfaces are characterized by measuring their ac responses, noise response and transient characteristics for a sinusoidal input. It is observed that, biasing impedances up to 60 gigaohms can be obtained with subthreshold transistors. Self biasing architecture eliminates the need for biasing the source of the subthreshold transistor to set the output dc point to 0 V. Single ended SOG gyroscopes are characterized with the single ended capacitive interfaces, and a 45 dB gain improvement is observed with the addition of capacitive interface to the drive mode. Minimum resolvable capacitance change and displacement that can be measured are found to be 58.31 zF and 38.87 Fermi, respectively. The scale factor of the gyroscope is found to be 1.97 mV/(°
/sec) with a nonlinearity of only 0.001% in ±
100 °
/sec measurement range. The bias instability and angle random walk of the gyroscope are determined using Allan variance method as 2.158 °
/&
#8730
hr and 124.7 °
/hr, respectively.
Cho, Taeg Sang. "An energy efficient CMOS interface to carbon nanotube sensor arrays". Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40519.
Texto completoIncludes bibliographical references (p. 95-98).
A carbon nanotube is considered as a candidate for a next-generation chemical sensor. CNT sensors are attractive as they allow room-temperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major sources of power dissipation in other types of sensor systems. Nevertheless, a poor control of the CNT resistance poses a constraint on the attainable energy efficiency of the sensor platform. An investigation on the CNT sensors shows that the dynamic range of the interface should be 17 bits, while the resolution at each base resistance should be 7 bits. The proposed CMOS interface extends upon the previously published work to optimize the energy performance through both the architecture and circuit level innovations. The 17-bit dynamic range is attained by distributing the requirement into a 10-bit Analog-to-Digital Converter (ADC) and a 8-bit Digital-to-Analog Converter (DAC). An extra 1-bit leaves room for any unaccounted subblock performance error. Several system-level all-digital calibration schemes are proposed to account for DAC nonlinearity, ADC offset voltage, and a large variation in CNT base resistance. Circuit level techniques are employed to decrease the leakage current in the sensitive frontend node, to decrease the energy consumption of the ADC, and to efficiently control the DAC. The interface circuit is fabricated in 0.18 /m CMOS technology, and can operate at 1.83 kS/s sampling rate at 32 pW worst case power. The resistance measurement error across the whole dynamic range is less than 1.34% after calibration. A functionality of the full chemical sensor system has been demonstrated to validate the concepts introduced in this thesis.
by Taeg Sang Cho.
S.M.
Zhang, Tan Tan. "Nano-watt class CMOS interface circuits for wireless sensor nodes". Thesis, University of Macau, 2018. http://umaclib3.umac.mo/record=b3952097.
Texto completoHehn, Thorsten [Verfasser] y Yiannos [Akademischer Betreuer] Manoli. "A CMOS Integrated Interface Circuit for Piezoelectric Energy Harvesters = Eine CMOS-Integrierte Schnittstellenschaltung für Piezoelektrische Energy Harvester". Freiburg : Universität, 2014. http://d-nb.info/1123479119/34.
Texto completoFrey, Urs. "High-density neural interface and microhotplate gas sensor in CMOS technology /". Zürich : Physical Electronics Laboratory, ETH Zürich, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=17460.
Texto completoLeung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface". Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.
Texto completoBARTESELLI, EDOARDO. "Accurate Voltage Reference Generator for Audio Interface in 65/55nm CMOS Technology". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/364988.
Texto completoIn recent years, mobile devices are very complex and feature-rich that consume a lot of energy. For this reason, the electronics industry is pushing towards reducing power and current consumption in electronic devices to increase battery life. Everything has to be done while maintaining the same performance or improving it. This thesis presents an accurate voltage reference generator for audio interface in CMOS technology at 65/55nm and particular attention has been paid to current consumption. The reference is made up of a Bandgap voltage reference and a Low Dropout regulator. The topology chosen for the bandgap is a current mode bandgap with adjustable output resistor. This guarantees a reference voltage of less than 1.2V thanks to the sum of two currents instead of two voltages. A double loop was chosen for the LDO regulator to ensure rapid transient response. First, the voltage reference generator was simulated in CMOS technology at 65nm. In the 65nm simulations all targeted specifications were successfully achieved. For BG, power consumption is less than 5uA, DC PSR lower than -60dB and a temperature coefficient around 5ppm/°C. The LDO has a fast settling time lower 150ns, a PSR of less than -70dB in the audio band ([20, 20K]Hz) and a power consumption of less than 10uA. Then, it was simulated and measured with 55nm CMOS technology and three different prototypes were developed and tested. The results are not as good as the 65 nm results because this was the first time the technology was used. Then, the three developed test chips were used to understand the behavior of the technology and to compare simulations with measurements, but each test chip is an improvement on the previous one. The latest test chip features PSR very close to specifications for BG and LDO and power consumption of 5uA for the BG, 10uA for the LDO NM and 5uA for the LDO LP.
Leicht, Joachim [Verfasser] y Yiannos [Akademischer Betreuer] Manoli. "CMOS circuits for electromagnetic vibration energy harvesters : : system modeling, interface design and implementation". Freiburg : Universität, 2019. http://d-nb.info/1193423090/34.
Texto completoXia, Hongxia Carleton University Dissertation Engineering Electronics. "Transistor placement algorithm for automatic layout synthesis of CMOS/BiCMOS logic and interface circuits". Ottawa, 1993.
Buscar texto completoSonmez, Ugur. "Capacitive Cmos Readouts For High Performance Mems Accelerometers". Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613068/index.pdf.
Texto completo&Delta
accelerometer systems to navigation grade performance levels. This goal will be achieved by reducing accelerometer noise level through significant changes in the system architecture and implementation of a new electronic interface readout ASIC. A flexible fourth order &Sigma
&Delta
modulator was chosen as the implementation of the electro-mechanical closed loop system, and the burden of noise shaping in the modulator was shifted from the mechanical sensor to the programmable electronic readout. A novel operational transconductance amplifier (OTA) was also designed for circuit implementation of the electronic interface readout. Design and fabrication of the readout was done in a standard 0.35 µ
m CMOS technology. With the newly designed and fabricated readout, single-axis accelerometers were implemented and tested for performance levels in 1g range. The implemented system achieves 5.95 µ
g/sqrt Hz, 6.4 µ
g bias drift, 131.7 dB dynamic range and up to 37.2 g full scale range with previously fabricated dissolved epitaxial wafer process (DEWP) accelerometers in METU MEMS facilities. Compared to a previous implementation with the same accelerometer element reporting 153 µ
g/sqrtHz, 50 µ
g bias drift, 106.8 dB dynamic range and 33.5 g full scale range
this research reports a 25 fold improvement in noise, 24 dB improvement in dynamic range and removal of the deadzone region.
Cortes, Fernando da Rocha Paixao. "Analysis, design and implementation of analog/RF blocks suitable for a multi-band analog interface for CMOS SOCs". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/13132.
Texto completoThe development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.
Murray, Andrew A. "Interface & support hardware for CMOS image sensors using minimum hardware and low bandwidth radio transmission". Thesis, University of Edinburgh, 1997. http://hdl.handle.net/1842/15466.
Texto completoGallorini, Romuald. "Conception en technologie CMOS standard d'une interface pour capteurs capacitifs dédiée à la mesure d'humidité relative". Lyon, INSA, 2002. http://www.theses.fr/2002ISAL0021.
Texto completoThe continous improvement of performences, secutity and power efficiency lead to the growth of sensors interaction in many applications. This thesis reports on a capacitive sensor interaction for automotive and public applications. It is based on a two-points calibration by PROM while the linear behaviour of the sensor characteristics is achieved thanks to a modular multibits technology to build a relative humidity probe from a commercial discret sensor
Berois, Javier Andrés Osinaga. "Interface de controle e monitoramento para circuitos alimentados em alta tensão variável". Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05092017-090653/.
Texto completoThis work presents the design of an interface that allow to control and monitoring high voltage loads in the range of 8,5V to 35V. The interface provides two main features, the first one is to allow low voltage circuits supplied with 5V to control the switching of power PMOS transistors with a gate voltage 5V bellow the supply voltage. The second one is monitoring overcurrents on the high voltage load alerting with a low voltage signal these occurences. The interface was designed and fabricated on the CMOS XC06 - 0,6µm process from XFAB with the inclusion of modules that allow the use of high voltage transistors. As part of the proposed solution it was analyzed, implemented and measured a floating voltage regulator wich provides an output voltage 5V bellow the supply voltage. The area of the regulator is 599µm x 330µm and the measures of the output voltage presents variations under the 10%. Also it was designed and integrates in the same integrated circuit a sensor to measure the output level of the floating regulator and communicate the state of this output with a 5V signal, this block occupies an area of 599µm x 579µm. This sensor presented a 7% standard desviation on the measured voltage threashold. The interface was integrated on an inductive proximity sensor allowing the switching of a 430pF load at 1,2kHz for the entire all supply range.
Kepenek, Reha. "Capacitive Cmos Readout Circuits For High Performance Mems Accelerometers". Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609310/index.pdf.
Texto completom CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 µ
g/&
#61654
Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed ±
18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 µ
g/&
#61654
Hz of noise level and 74 µ
g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/º
C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.
Wienke, James Patrick. "The impact of interface states on sub-threshold leakage and power management in CMOS devices and circuits". College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7235.
Texto completoThesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
BONANNO, ALBERTO. "Micro-for-Nano: A Low-Power Platform for Nanomaterial Integration and Nanosensors Interface on 0.13μm CMOS Technology". Doctoral thesis, Politecnico di Torino, 2014. http://hdl.handle.net/11583/2557562.
Texto completoXia, Bo. "Analog-to-digital interface design in wireless receivers". Texas A&M University, 2004. http://hdl.handle.net/1969.1/3260.
Texto completoYu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition". Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
Texto completoLaotaveerungrueng, Noppasit. "A High-Voltage, High-Current Multi-Channel Arbitrary Waveform Generator ASIC for Neural Interface and MEMS Applications". Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1291675462.
Texto completoHenniquau, Dimitri. "Conception d’une interface fonctionnelle permettant la communication de neurones artificiels et biologiques pour des applications dans le domaine des neurosciences". Thesis, Université de Lille (2018-2021), 2021. http://www.theses.fr/2021LILUN032.
Texto completoNeuromorphic engineering is an exciting emerging new field, which combines skills in electronics, mathematics, computer sciences and biomorphic engineering with the aim of developing artificial neuronal networks capable of reproducing the brain’s data processing. Thus, neuromorphic systems not only offer more effective and energy efficient solutions than current data processing technologies, but also set the bases for developing novel original therapeutic strategies in the context of pathological brain dysfunctions. The research group Circuits Systèmes Applications des Micro-ondes (CSAM) of the Institute for Electronics, Microelectronics and Nanotechnologies (IEMN) in Lille, in which this thesis work was carried out, has contributed to the generation of such neuromorphic systems by developing a toolbox constituted of artificial neurons and synapses. In order to implement neuromorphic engineering in the therapeutic arsenal for treating neurologic disorders, we need to interface living and artificial neurons to ensure real communication between these different components. In this context and using the original tools developed by the CSAM group, the main goal of this thesis work was to design and produce a functional interface allowing a bidirectional communication loop to be established between living and artificial neurons. These artificial neurons have been developed by the CSAM group using CMOS technology and are able to emit biomimetic electrical signals. Living neurons were obtained from differentiated PC-12 cells. A first step in this work consisted in modeling and simulating this interface between artificial and living neurons; a second part of the thesis was dedicated to the fabrication and characterization of neurobiohybrid interfaces, and to the growth and characterization of living neurons before studying their capacities to communicate with artificial neurons. First, a model of neuronal membrane representing a living neuron interfaced with a metallic planar electrode has been developed. We thus showed that it is possible to excite neurons using biomimetic signals produced by artificial neurons while maintaining a low excitation voltage. Low voltage excitation would improve energy efficiency of neurobiohybrid systems integrating artificial neurons and reduce the impact of harmful electrical signals on living neurons. Then, the neurobiohybrid interfacing living and artificial neurons has been designed and produced. The results obtained by experimental characterization of this interface validate the approach consisting in exciting living neurons through a metallic planar electrode. Finally, living neurons from PC-12 cells were grown and differentiated directly onto neurobiohybrids. Then, an experimental proof of the ability of biomimetic electrical signals to excite living neurons was obtained using calcium imaging. To conclude, the work presented in this manuscript clearly establishes a proof of concept for the excitation of living neurons using a biomimetic signal in our experimental conditions and thus substantiates the first part of the bidirectional communication loop between artificial neurons and living neurons
Luo, Yi. "Ultra-Wideband Transceiver with Error Correction for Cortical Interfaces in NanometerCMOS Process". DigitalCommons@USU, 2017. https://digitalcommons.usu.edu/etd/5859.
Texto completoKraemer, Michael M. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS". Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0027/document.
Texto completoWorldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs)at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form basic transmitter and receiver chips. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished.The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemented. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy
Vakili-Amini, Babak. "A Mixed-Signal Low-Noise Sigma-Delta Interface IC for Integrated Sub-Micro-Gravity Capacitive SOI Accelerometers". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10437.
Texto completoTUOHETI, ABUDUWAILI. "Smart Embedded Systems for Biomedical Applications". Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2742529.
Texto completoCecchetto, Claudia. "Neuronal Population Encoding of Sensory Information in the Rat Barrel Cortex: Local Field Potential Recording and Characterization by an Innovative High-Resolution Brain-Chip Interface". Doctoral thesis, Università degli studi di Padova, 2016. http://hdl.handle.net/11577/3424482.
Texto completoLe reti neuronali sono alla base della codifica dell'informazione cerebrale. L'obiettivo principale dello studio delle popolazioni neuronali è quello di caratterizzare la relazione tra uno stimolo e la risposta individuale o globale dei neuroni e di studiare il rapporto tra le varie attività elettriche dei neuroni appartenenti ad una particolare rete, comprendendo anche come la topologia e la connettività della rete neuronale influiscano sulla loro funzionalità. Fino ad oggi, molte tecniche sono state sviluppate per studiare questi sistemi complessi: studi a singola cellula mirano a studiare singoli neuroni e le loro connessioni con un numero limitato di altre cellule; sul lato opposto, approcci su larga scala e a bassa risoluzione, come la risonanza magnetica funzionale o l'elettroencefalogramma, registrano segnali elettrofisiologici generati nel cervello da vaste popolazioni di cellule. Più recentemente, sono state sviluppate tecniche di registrazione multisito che mirano ad abbattere le limitazioni dei precedenti approcci, rendendo possibile la misurazione ad alta risoluzione di segnali generati da grandi ensamble neuronali e da diverse regioni del cervello simultaneamente, ad esempio mediante l'uso di chip impiantabili a semiconduttore. I potenziali di campo locali (LFP) catturano processi sinaptici chiave che non possono essere estratti dall'attività di spiking di qualche neurone isolato. Numerosi studi hanno utilizzato gli LFP per studiare i meccanismi corticali coinvolti nei processi sensoriali, motori e cognitivi, come la memoria e la percezione. Gli LFP rappresentano anche dei segnali interessanti nell'ambito delle applicazioni neuroprotesiche e per monitorare l'attività cerebrale negli esseri umani, dal momento che possono essere registrati più stabilmente e facilmente in impianti cronici rispetto agli spike neuronali. In questo studio, sono riportati dei profili LFP registrati dalla barrel cortex di ratto tramite chip ad ago ad alta risoluzione basati su tecnologia CMOS e confrontati con quelli ottenuti tramite elettrodi convenzionali in Ag/AgCl inseriti in micropipette di vetro, strumenti comunemente usati in elettrofisiologia. La barrel cortex di ratto è un esempio ben noto di mapping topografico, nel quale ogni baffo sul muso dell'animale è mappato in una specifica area corticale, chiamata barrel. La barrel cortex contiene la rappresentazione sensoriale dei baffi dell'animale e rappresenta uno dei primi stadi di elaborazione dell'informazione tattile, insieme al ganglio del trigemino e al talamo. Essa è un'area di primaria importanza per lo studio del funzionamento della corteccia cerebrale, visto che le colonne corticali che formano i blocchi di base della neocorteccia possono essere visualizzati facilmente all'interno della barrel cortex. La barrel cortex inoltre è utilizzata come sistema di test in numerose metodologie innovative, grazie alla sua struttura unica ed istantaneamente identificabile, e grazie anche al fatto che le specie dotate di barrel, i roditori, sono gli animali da laboratorio più comuni. La barrel cortex e le sue interconnessioni neuronali sono stati oggetto delle ricerche più disparate in questi ultimi decenni. Attualmente, alcuni studi (come questo) non mirano solamente a comprendere meglio la barrel cortex, ma anche ad analizzare problematiche in campi scientifici collegati, utilizzando la barrel cortex come modello base. In questo lavoro, sono stati evocati segnali LFP nella barrel cortex tramite deflessioni ripetute dei baffi dell'animale, realizzate in modo controllato tramite un sistema di deflessione piezoelettrica a closed-loop innescato da un sistema di acquisizione LabView. Le risposte evocate generate nella barrel dalla stimolazione ripetuta dei baffi presentano elevata variabilità nella forma e nelle latenze temporali. Inoltre, il tipo di anestesia utilizzata può influenzare profondamente il profilo della risposta evocata. Questo studio riporta i risultati preliminari sulla variabilità della risposta neuronale e sull'effetto di due anestetici di uso comune su questi segnali, confrontando le distribuzioni delle risposte evocate in ratti anestetizzati con tiletamina-xylazina (il quale agisce prevalentemente sui recettori eccitatori di tipo NMDA) e uretano (che agisce in modo più bilanciato e complesso su entrambi i sistemi eccitatori ed inibitori, preservando la plasticità sinaptica). Sono state analizzate e discusse alcune caratteristiche rappresentative del segnale evocato (ad esempio, le latenze temporali e l'ampiezza degli eventi), registrato a varie profondità corticali. Per tutte le prondità corticali acquisite, sono state stimate le distribuzioni statistiche di tali parametri, in modo da valutare la variabilità degli LFP evocati dalle stimolazioni meccaniche individuali delle vibrisse del ratto lungo l'intera colonna corticale. I primi risultati presentano una grande variabilità nelle risposte corticali, sia in latenza che in ampiezza. Inoltre, è stata riscontrata una differenza significativa nella latenza del primo picco principale delle risposte evocate: gli LFP evocati in animali anestetizzati con tiletamina-xylazina presentavano una latenza più lunga di quelli registrati in ratti anestetizzati con uretano. Inoltre, le distribuzioni dei parametri analizzati erano più strette e piccate in uretano, in corrispondenza di tutte le profondità corticali. Questo comportamento è sicuramente da attribuire al differente meccanismo d'azione dei due anestetici su specifici recettori sinaptici, e quindi nell'elaborazione e nella trasmissione dell'informazione sensoriale lungo tutto il percorso corticale. E' stato inoltre discusso il ruolo della attività basale nella modulazione della risposta evocata. A questo proposito, è stata registrata l'attività spontanea in corrispondenza dei vari layer corticali ed analizzata nel contesto statistico delle 'valanghe neuronali'. Una valanga neuronale è una cascata di attività elettrica in una rete neuronale, la cui distribuzione statistica dei parametri principali (dimensione e vita media) può essere approssimata da una legge di potenza. La distribuzione delle dimensioni di una valanga in una rete neuronale segue una legge di potenza del tipo P(s)=s^-a, con a=1.5. Tale esponente è un riflesso delle correlazioni spaziali a lungo raggio nell'attività neuronale spontanea. Dal momento che i picchi negativi (nLFPs) nelle tracce elettrofisiologiche originano dalla somma di potenziali d'azione sincronizzati generati da neuroni posti nelle vicinanze dell'elettrodo di registrazione, ci siamo chiesti se fosse possibile modellizare i singoli nLFP registrati nell'attività basale tramite un singolo elettrodo come il risultato di valanghe neuronali locali. Pertanto, abbiamo analizzato la distribuzione della dimensione (cioè l'ampiezza in uV) di tali picchi, in modo da identificare una distribuzione power-law appropriata, che potesse descrivere anche le registrazioni a singolo elettrodo. Infine, sono presentate e discusse le prime registrazioni in assoluto degli LFP evocati lungo un'intera colonna corticale ottenute tramite l'ultima generazione di chip impiantabili a tecnologia CMOS. Questi ultimi presentano una matrice di 256 siti di registrazione, organizzata secondo due possibili topologie, 16 x 16 o 4 x 64, e avente una distanza tra gli elettrodi pari a 15 um o 33 um rispettivamente. Una precisa dinamica di propagazione dei potenziali evocati può già essere riconosciuta in questi primissimi profili corticali. Nel prossimo futuro, l'uso di questi dispositivi a semiconduttore potrà aiutare a comprendere il decorso di sindromi neurodegerative come il Parkinson o l'Alzheimer, associando sintomi e comportamenti tipo della malattia a specifiche caratteristiche neuronali. I chip impiantabili potranno anche essere utilizzati come 'electroceuticals', ossia potranno aiutare a rallentare (o addirittura a capovolgere) il decorso delle malattie neurogenerative, costituendo le basi di protesi neuronali in grado di sostenere fisicamente o allenare funzionalmente le popolazioni neuronali danneggiate. L'identificazione e il rilevamento di segnali neuronali ad alta risoluzione aiuterà anche a sviluppare complesse interfacce cervello-macchina, che consentiranno il controllo di protesi intelligenti e che forniranno sofisticati meccanismi di feedback a chi ha perso l'uso di alcune parti del proprio corpo o determinate funzioni cerebrali.
Crescentini, Marco <1984>. "Advanced CMOS Interfaces for Bio-Nanosensors". Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2012. http://amsdottorato.unibo.it/4660/1/crescentini_marco_tesi.pdf.
Texto completoCrescentini, Marco <1984>. "Advanced CMOS Interfaces for Bio-Nanosensors". Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2012. http://amsdottorato.unibo.it/4660/.
Texto completoJawed, Syed Arsalan. "CMOS Readout Interfaces for MEMS Capacitive Microphones". Doctoral thesis, Università degli studi di Trento, 2009. https://hdl.handle.net/11572/368656.
Texto completoJawed, Syed Arsalan. "CMOS Readout Interfaces for MEMS Capacitive Microphones". Doctoral thesis, University of Trento, 2009. http://eprints-phd.biblio.unitn.it/82/1/thesis_mems_microphone_readout.pdf.
Texto completoKraemer, Michael. "Design of a low-power 60 GHz transceiver front-end and behavioral modeling and implementation of its key building blocks in 65 nm CMOS". Phd thesis, INSA de Toulouse, 2010. http://tel.archives-ouvertes.fr/tel-00554674.
Texto completoCICIOTTI, FULVIO. "Oscillator-Based CMOS Readout Interfaces for Gas Sensing Applications". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2019. http://hdl.handle.net/10281/241089.
Texto completoDetection of toxic and dangerous gases has always been a need for safety purpose and, in recent years, portable and low-cost gas sensing systems are becoming of main interest. This thesis presents fast, high precision, low-power, versatile CMOS interface circuits for portable gas sensing applications. The target sensors are Metal Oxide Semiconductor (MOX) sensors which are widely used due to their inherent compatibility with integrated MEMS technologies. The chosen readout typologies are based on the time-domain Resistor-Controlled Oscillator. This guarantees wide dynamic range, good precision and the ability to cope with the large MOX sensor resistance variations. Four different prototypes have been successfully developed and tested. Chemical measurements with a real SnO2 MOX sensor have also been performed to validate the results, showing a minimum CO detection capability in ambient air of 5 ppm. The ASICs are able to cover 128 dB of DR at 4 Hz of digital output data rate, or 148 dB at 0.4 Hz, while providing a relative error always better than 0.4% (SNDR >48 dB). Target performances have been achieved with aggressive design strategies and system-level optimization, and using a scaled (compared to typical implementations in this field) 130nm CMOS technology provided by Infineon Technologies AG. Power consumption is about 450 μA. Moreover, this work introduces the possibility to use the same oscillator-based architecture to perform capacitive sensors readout. Measurement results with capacitive MEMS sensors have shown 116 dB of DR in CSENS mode, with an SNR of 74 dB at 10 Hz of digital output data rate. The architectures developed in this thesis are compatible with the modern standards in the portable gas sensing industry.
Graham, Anthony H. D. "Biocompatible low-cost CMOS electrodes for neuronal interfaces, cell impedance and other biosensors". Thesis, University of Bath, 2010. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.527140.
Texto completoGriffiths, Alexander D. "Novel optical communications and imaging enabled by CMOS interfaced LED technology". Thesis, University of Strathclyde, 2018. http://digitool.lib.strath.ac.uk:80/R/?func=dbin-jump-full&object_id=30328.
Texto completoLeene, Lieuwe. "Brain machine interfaces : low power techniques for CMOS based system integration". Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/47980.
Texto completoGagnon-Turcotte, Gabriel. "Interfaces neuronales CMOS haute résolution pour l'électrophysiologie et l'optogénétique en boucle fermée". Doctoral thesis, Université Laval, 2019. http://hdl.handle.net/20.500.11794/36493.
Texto completola taille et la consommation énergétique, en plus de ne pas être optimisée pour cette application. La seconde phase du projet a permis de concevoir un système sur puce (SoC) complementary metal oxide semiconductor (CMOS) pour faire de l’enregistrement neuronal et de optogénétique multicanal, permettant de réduire significativement la taille et la consommation énergétique comparativement aux alternatives commerciales. Ceci est une contribution importante, car c’est la première puce à être doté de ces deux fonctionnalités. Le SoC possède 10 canaux d’enregistrement et 4 canaux de stimulation optogénétique. La conception du bioamplificateur inclut une bande passante programmable (0.5 Hz - 7 kHz) et un faible bruit referré à l’entré (IRN de 3.2 μVrms), ce qui permet de cibler différents types de signaux biologiques (PA, LFP, etc.). Le convertisseur analogique numérique (ADC) de type Delta- Sigma (DS) MASH 1-1-1 est conçu pour fonctionner de faibles taux de sur-échantillonnage (OSR _50) pour réduire sa consommation et possède une résolution programmable (ENOB de 9.75 Bits avec un OSR de 25). Cet ADC exploite une nouvelle technique réduisant la taille du circuit en soustrayant la sortie de chaque branche du DS dans le domaine numérique, comparativement à la méthode analogique classique. La consommation totale d’un canal d’enregistrement est de 11.2 μW. Le SoC implémente un nouveau circuit de stimulation optique basé sur une source de courant de type cascode avec rétroaction, ce qui permet d’accommoder une large gamme de LED et de tensions de batterie comparativement aux circuits existants. Le SoC est intégré dans un système optogénétique sans fil et validé in vivo. À ce jour et en excluant ce projet, aucun système sans-fil ne fait de l’optogénétique en boucle fermée simultanément au suivi temps réel de l’activité neuronale. Une contribution importante de ce travail est d’avoir développé le premier système optogénétique multicanal qui est capable de fonctionner en boucle fermée et le premier à être validé lors d’expériences in vivo impliquant des animaux libres de leurs mouvements. Pour ce faire, la troisième phase du projet a visé la conception d’un SoC CMOS numérique, appelé neural decoder integrated circuit (ND-IC). Le ND-IC et le SoC développé lors de la phase 2 ont été intégrés dans un système optogénétique sans fil. Le ND-IC possède 3 modules : 1) le détecteur de PA adaptatif, 2) le module de compression possédant un nouvel arbre de tri pour discriminer les coefficients, et 3) le module de classement automatique des PA qui réutilise les données générées par le module de détection et de compression pour réduire sa complexité. Un lien entre un canal d’enregistrement et un canal de stimulation est établi selon l’association de chaque PA à un neurone, grâce à la classification, et selon l’activité de ce neurone dans le temps. Le ND-IC consomme 56.9 μW et occupe 0.08 mm2 par canal. Le système pèse 1.05 g, occupe un volume de 1.12 cm3, possède une autonomie de 3h, et est validé in vivo.
The future of brain research lies in the development of new technologies that will help understand how this complex organ processes, integrates and transfers information. Among these, optogenetics is a recent technology that allows the use of light to selectively activate neurons in the cortex of transgenic animals to observe their effect in a large biological network. This experimental setting is typically based on observing the neuronal activity of transgenic mice, as they express a wide variety of genes and diseases, while being inexpensive. However, most available neural recording or optogenetic devices are not suitable, because they are hard-wired, too heavy and/or too simplistic. Unfortunately, few wireless systems exist, and they are greatly limited by the required bandwidth to transmit neural data, while not providing simultaneous multi-channel neural recording and optogenetic, a must for stimulating and observing several areas of the brain. In current devices, the analysis of the neuronal data is performed ex situ, while the research would greatly benefit from wireless systems that are smart enough to interpret and stimulate the neurons in closed-loop, in situ. The goal of this project is to design analog-digital circuits for acquisition and processing of neural signals, algorithms for analysis and processing of these signals and miniature electrooptical wireless systems for: i) Conducting experiments combining high-resolution multi-channel neuronal recording and high-resolution multi-channel optogenetics with freely-moving animals. ii) Conduct optogenetic experiments synchronized with the neural recording, i.e. in closed loop, with freely-moving animals. iii) Increase the resolution while reducing the size, weight and energy consumption of the wireless optogenetic systems to minimize the impact of research with small animals. This project is in 3 phases, and its main contributions have been reported in ten conferences (ISSCC, ISCAS, EMBC, etc.) and four published journal papers, or submitted, as well as in a patent and two disclosures. The design of a high resolution optogenetic system poses several challenges. In particular, since the neuronal signals have a high frequency content (10 kHz), the number of chanv nels under observation is limited by the bandwidth of the wireless transmitters (2-4 channels in general). Thus, the first phase of the project focused on the development of neural signal compression algorithms and their integration into a high-resolution miniature and lightweight wireless optogenetics system (2.8g), having 32 recording channels and 32 optical stimulation channels. This system detects, compresses and transmits the waveforms of the signals produced by the neurons, i.e. action potentials (AP), in real time, via an embedded low-power field programmable gate array (FPGA). This processor implements an AP detector algorithm based on adaptive thresholding, which allows to compress the signals by transmitting only the detected waveforms. Each AP is further compressed by a Symmlet-2 discrete wavelet transform (DWT) followed dynamic discrimination and requantification of the DWT coefficients, making it possible to achieve high compression ratios with a good reconstruction quality. Results demonstrate that this algorithm is more robust than existing approach, while allowing to reconstruct the compressed signals with better quality (average SNDR of 25 dB 5% for a compression ratio (CR) of 4.2). With detection, CRs greater than 500 are reported during the in vivo validation. The use of commercial components in wireless optogenetic systems increases the size and power consumption, while not being optimized for this application. The second phase of the project consisted in designing a complementary metal oxide semiconductor (CMOS) system-on-chip (SoC) for neural recording and multi-channel optogenetics, which significantly reduces the size and energy consumption compared to commercial alternatives. This is important contribution, since it’s the first chip to integrate both features. This SoC has 10 recording channels and 4 optogenetic stimulation channels. The bioamplifier design includes a programmable bandwidth (0.5 Hz -7 kHz) and a low input-referred noise (IRN of 3.2 μVrms), which allows targeting different biological signals (AP, LFP, etc.). The Delta-Sigma (DS) MASH 1-1-1 low-power analog-to-digital converter (ADC) is designed to work with low OSR (50), as to reduce its power consumption, and has a programmable resolution (ENOB of 9.75 bits with an OSR of 25). This ADC uses a new technique to reduce its circuit size by subtracting the output of each DS branch in the digital domain, rather than in the analog domain, as done conventionally. A recording channel, including the bioamplifier, the DS and the decimation filter, consumes 11.2 μW. Optical stimulation is performed with an on-chip LED driver using a regulated cascode current source with feedback, which accommodates a wide range of LED parameters and battery voltages. The SoC is integrated into a wireless optogenetic platform and validated in vivo.
To date and excluding this project, no wireless system is making closed-loop optogenetics simultaneously to real-time monitoring of neuronal activity. An important contribution of this work is to have developed the first multi-channel optogenetic system that is able to work in closed-loop, and the first to be validated during in vivo experiments involving freely-moving animals. To do so, the third phase of the project aimed to design a digital CMOS chip, called neural decoder integrated circuit (ND-IC). The ND-IC and the SoC developed in Phase 2 are integrated within a wireless optogenetic system. The ND-IC has 3 main cores: 1) the adaptive AP detector core, 2) the compression core with a new sorting tree for discriminating the DWT coefficients, and 3 ) the AP automatic classification core that reuses the data generated by the detection and compression cores to reduce its complexity. A link between a recording channel and a stimulation channel is established according to the association of each AP with a neuron, thanks to the classification, and according to the bursting activity of this neuron. The ND-IC consumes 56.9 μW and occupies 0.08 mm2 per channel. The system weighs 1.05 g, occupies a volume of 1.12 cm3, has an autonomy of 3h, and is validated in vivo.
De, Luca Anthony. "Redistribution atomique de contaminants métalliques aux interfaces des structures des technologies CMOS". Thesis, Aix-Marseille, 2014. http://www.theses.fr/2014AIXM4302/document.
Texto completoDuring this thesis work, we studied the atomic redistribution of metallic contaminantsin silicon and near a SiO2/Si interface. To conduct this study, we used three complementary characterisation techniques : transmission electron microscopy (TEM), atomic probe tomography (APT) and secondary ion mass spectrometry (SIMS).We first studied the diffusion and equilibrium segregation of various contaminants at a SiO2/Si interface, and more particularly, the diffusion of W and Mo. W exhibits a very slow diffusion kinetic.Physico-chemical characterizations performed by TEM and APT allowed discussing the concentrationprofiles obtained by SIMS leading to the diffusion model that we proposed. The study of Mo diffusionrevealed that this specy exhibits a low solubility limit in silicon and strongly interacts with irradiation-induced defects, leading to its precipitation.In a second phase, we studied the effect of a mobile interface, during a reaction, on the atomic redistribution of contaminants near this interface. We performed a comparative study of the behaviourof Fe and W during oxidation processes. W precipitates in the silicon substrate and is progressivelyrejected (snowplow) by the oxidation. Fe preferentially precipitates at the SiO2/Si interface. Theseprecipitates mask a part of the silicon substrate and thus hinder its oxidation, leading to the formation of characteristics pyramidal-shaped defects at the interface. Low temperature nickel germano-silicide formation have also been investigated. This reaction leads to the 3D snowplow of germanium atoms at the NiSiGe/SiGe interface
Rebillat, Francis. "Caractérisation des interfaces et des matériaux d'interphases dans les CMCs". Bordeaux 1, 1996. http://www.theses.fr/1996BOR10560.
Texto completoLlanos, Roger Vicente Caputo. "Voltage scaling interfaces for multi-voltage digital systems". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/159617.
Texto completoMultiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.
TANG, JIANJING. "DESIGN AND ANALYSIS OF A 32X32-BIT DATABASE FILTER CHIP BASED ON A CMOS COMPATIBLE PHOTONIC VLSI DEVICE TECHNOLOGY". University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1059399964.
Texto completoGamet, Arnaud. "Etude et mise en oeuvre de transitions passives aux interfaces circuit/boîtier pour les bases de temps intégrées résonantes". Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0002.
Texto completoNowadays, the integration of oscillators into microcontrollers is a major industrial challenge which involves a large competition between the main actors of this market. Indeed, sine wave oscillators are essential circuits, and are fore the most part based on external crystal or MEMs resonators. More and more investigations are carried out in order to integrate the resonant structure into the package, and avoid all external constraints able to restrict the performances of the oscillator. With this in mind, we studied in this work the electrical behavior, in particular the inductive behavior of bond wires which are electrical connections between a die and its package. The main advantage to use this type of component is its low cost of manufacturing. This passive component has been characterized using several measurement tools on a wide range of frequencies. A RLC model has been presented, allowing analogue designers to use an electrical equivalent circuit in standard CMOS technology. The integration of the passive component in a resonant cell has been demonstrated in a prototype
Pumarica, Julio Cesar Saldaña. "Sistemas de detecção e classificação de impulsos elétricos de sinais neurais extracelulares". Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-19122016-133542/.
Texto completoNeural signals recording through implantable microelectrode arrays in cortex extracellular medium has become an experimental paradigm for neuroscience. Moreover, recent research about motor neuroprostheses has shown that it is possible to decode motor commands from the signals recorded in the cerebral cortex extracellular medium. In both situations, experimental neuroscience and motor neuroprostheses development, one of the issues encountered in the state-of-the-art is the use of integrated circuits (chips) implanted in the brain. In these chips, neural signals measured with microelectrodes are amplified, filtered, processed, and transmitted to an external computer through wires that run through the skull. There is interest in developing implantable chips that transmit signals to the external computer without the need for wires passing through the skull. In the survey of the state-of-the-art it has found the use of such implantable wireless chips in rats and monkeys, but until the date of this writing we have not found reports of application in humans. One of the aspects that must be taken into account in the development of wireless implantable neural interfaces is the bandwidth of the communication channel. The greater the amount of data to be transmitted, the greater the bandwidth required and higher chip heating due to power dissipation. This thesis deals with extracellular neural signals processing systems that aim to reduce the amount of data to be transmitted and in this way to enable wireless transmission. In order to integrate them into an implantable chip, those processing systems must be optimized in terms of area and power consumption. Two processes found in the research of implantable neural interfaces are spike detection and spike sorting. In this thesis solutions for these types of processing are presented considering their implementation by CMOS (Complementary Metal Oxide Semiconductor). For the case of spike detection in this thesis it is presented an alternative for the hardware implementation of a mathematical operator known as NEO (Nonlinear Energy Operator). Through the application of this operator to a neural signal the presence of spikes becomes evident and the noise is attenuated. One of the innovative characteristics of the implementation presented in this thesis is the use of a squarer circuit which consists of only three transistors, as a basic function block for performing operation of NEO. NEO circuit consumes 300 pJ in processing a spike, and was characterized by simulation up to 30 kHz, frequency which is compatible with sampling rates found in the literature. The other processing discussed in this thesis, known as Spike Sorting, is the grouping of electrical impulses recorded by an electrode into categories so that the spikes belonging to the same category were generated by a single neuron. In other words, the goal is to recognize which of the spikes measured by the electrode belong to the same neuron, given that it is possible that several neurons influence the measure performed by a single electrode. A solution for the Spike Sorting suitable in the context of implantable systems, is the template matching. This technique is based on generating templates during an initial phase at the end of which the number of generated templates corresponds to the number of neurons identified by the electrode. In the next phase, the system associates each detected spike to one of the templates generated initially. In this thesis it is proposed a classification systems which performs that second phase of the spike sorting process. This thesis presents the design of a spike classification system based on template matching technique, implemented in CMOS technology. The processing proposed in this work is based on the time-based representation of the analog samples. This kind of representation of analog signals by delays of digital pulses is being widely used as an alternative to the classical representation of samples by voltage, current or electric charge. The advantage of this time-mode representation is that it is not severely affected by reduced supply voltage of integrated circuits manufactured in sub-micrometer technologies. The classification hit rate of the developed system is greater than 99% even when an offset of 20 mV is assumed for the output comparator. All the circuits presented in this work were designed using devices from TSMC 90nm technology.
Ahn, Byung Ki. "Interfacial Mechanics in Fiber-Reinforced Composites: Mechanics of Single and Multiple Cracks in CMCs". Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/29791.
Texto completoPh. D.
Saidi, Bilel. "Metal gate work function modulation mechanisms for 20-14 nm CMOS low thermal budget integration". Toulouse 3, 2014. http://www.theses.fr/2014TOU30300.
Texto completoTo continue CMOS scaling, the HfO2/metal gate stack replaced the historical SiO2/PolySi gate stack. But the uncontrolled interdiffusion and reactivities of the new gate materials integrated with the classical high thermal budget approach appear to be a roadblock to reach the effective work function (EWF) and equivalent oxide thickness (EOT) ITRS targets. One solution consisted in implementing an approach with a lower thermal budget. Using this new approach, the aim of this thesis work was to understand the physical mechanisms, which enable to reach an EOT<1nm and an EWF relevant for nMOS and pMOS co-integration as required for the next 20-14nm CMOS nodes. Using spatially resolved TEM/EDX analyses and macroscopic TOF-SIMS and XPS techniques, elemental distributions and chemical bonds across nanometric-sized stacks were discussed and, based on thermodynamic considerations, correlated with the measured EWF and EOT. We showed for the first time that the modulation of nitrogen during TiAlN deposition on HfO2 results in a ~0. 8eV EWF shift between the N-poor and N-rich HfO2/TiAlNx electrodes. The TiAlN complex system was understood after the identification of the EWF and EOT modulation mechanisms in the simple gate stacks TiN/Ti, Al or TiAl. Although TiAlNx electrodes define the best compromise for a variable EWF with a sub-nm EOT, it exhibits a low thermal stability. Therefore, we investigated two simpler metallic and stable systems using TaNix and NiTix alloys resulting from thermally assisted Ni-Ta and Ni-Ti interdiffusion in HfO2/Ta/Ni and HfO2/Ni/Ti stacks, respectively. These Ni-based electrodes are shown to be promising for a low thermal budget CMOS co-integration
Gómez, Cama José María. "Diseño de moduladores Delta-Sigma en tecnología CMOS-VLSI. Aplicación al desarrollo de circuitos de interfaz para sensores capacitivos". Doctoral thesis, Universitat de Barcelona, 2000. http://hdl.handle.net/10803/1508.
Texto completoAspectos como la automatización de viviendas y edificios se empieza a considerar una cuestión clave para la industria informática. Los cuales se basan en buses de campo. Estos precisan de sensores que le informen del estado de la vivienda, industria, vehículo... que se desea controlar, y actuadores que permitan modificar dicho estado.
Sin embargo, los sensores y actuadores son, en general, sistemas analógicos, con salidas difícilmente estandarizables si no se les incluye una electrónica que acondicione la señal, la convierta en digital, y la adapte a dicho estándar.
La respuesta a esta necesidad la han dado los microsistemas, que permiten incluir en una oblea de silicio sensores, actuadores y la electrónica de control necesaria dando lugar a los llamados sensores y actuadores inteligentes.
Sin embargo, la fabricación de estos microsistemas suele precisar de procesos tecnológicos complejos y costosos, que requieren de etapas que normalmente no se realizan en los procesos CMOS estándar. Esto puede implicar la necesidad de realizar el sensor/actuador en una oblea distinta de la del circuito, por problemas de compatibilidad entre procesos.
Esta tesis también se enmarca dentro de este campo, y busca el diseño de un circuito de interfaz para sensores capacitivos micromecanizados en silicio.
Teniendo en cuenta la posible utilización posterior, se ha impuesto que el diseño debe ser compatible con una tecnología CMOS de bajo coste. Esto lleva a realizar el diseño en tecnologías concebidas inicialmente para la implementación de circuitos digitales.
La salida del interfaz debe ser digital, para poder ser conectado fácilmente a un bus digital. Por este motivo, se ha realizado un estudio de las posibles metodologías de conversión.
Por último, se ha buscado un diseño siguiendo una metodología Top-Down, acorde con las utilizadas en las tecnologías digitales. Esto simplifica el proceso de diseño cuando se hacen sistemas mixtos, ya que se pueden realizar los diferentes pasos en paralelo.
A la hora de escribir esta tesis también se ha seguido este esquema, organizando los capítulos en el mismo orden.
Medida de Microsensores Capacitivos: Describe el problema de la medida, haciendo hincapié en los problemas que se pueden encontrar con un microsensor capacitivo. También realiza el estudio de un microsensor concreto, un acelerómetro xyz para el automovil.
Diseño Funcional: En este capítulo se estudian las posibles opciones para el diseño de la interfaz. Y posteriormente se analiza la estabilidad del sistema sensor-interfaz.
Diseño Estructural: A partir de las decisiones tomadas en el diseño funcional, se baja al nivel de bloques y se estudia que componentes y dispositivos son más adecuados para el diseño a partir de la modelización y simulaciones realizadas.
Diseño Físico: Se explica todo el proceso seguido para el diseño de las máscaras de la interfaz. Para ello se presenta una explicación más detallada de aquellos dispositivos que por sus características son más dependientes de las condiciones de las máscaras.
Test: Este último capítulo presenta la metodología seguida para la caracterización de los circuitos, así como los resultados obtenidos
Orság, Lubomír. "CMS systém kombinovaný s eshop systémem". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217289.
Texto completoDu, Sijun. "Energy-efficient interfaces for vibration energy harvesting". Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/270359.
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