Literatura académica sobre el tema "CMOS interface"
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Artículos de revistas sobre el tema "CMOS interface"
Lau, K. T., W. Y. Wang y K. W. Ng. "Adiabatic-CMOS/CMOS-adiabatic logic interface circuit". International Journal of Electronics 87, n.º 1 (enero de 2000): 27–32. http://dx.doi.org/10.1080/002072100132417.
Texto completoGhoshal, U., S. V. Kishore, A. R. Feldman, Luong Huynh y T. Van Duzer. "CMOS amplifier designs for Josephson-CMOS interface circuits". IEEE Transactions on Appiled Superconductivity 5, n.º 2 (junio de 1995): 2640–43. http://dx.doi.org/10.1109/77.403132.
Texto completoWei, Daniel, Stephen R. Whiteley, Lizhen Zheng, Heejoung Park, Hoki Kim y Theodore Van Duzer. "New Josephson-CMOS Interface Amplifier". IEEE Transactions on Applied Superconductivity 21, n.º 3 (junio de 2011): 805–8. http://dx.doi.org/10.1109/tasc.2010.2088358.
Texto completoTakagi, Shinichi, Sanjeewa Dissanayake y Mitsuru Takenaka. "High Mobility Ge-Based CMOS Device Technologies". Key Engineering Materials 470 (febrero de 2011): 1–7. http://dx.doi.org/10.4028/www.scientific.net/kem.470.1.
Texto completoWu, Xiang y Fang Ming Deng. "A Capacitive Humidity Sensor for Low-Cost Low-Power Application". Applied Mechanics and Materials 556-562 (mayo de 2014): 1847–51. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1847.
Texto completoChen, Wei Ping, Chang Chun Dong, Xiao Wei Liu y Zhi Ping Zhou. "A Miniature Fluxgate Sensor with CMOS Interface Circuitry". Key Engineering Materials 483 (junio de 2011): 164–68. http://dx.doi.org/10.4028/www.scientific.net/kem.483.164.
Texto completoCivardi, L., U. Gatti, F. Maloberti y G. Torelli. "An integrated CMOS interface for lambda sensor". IEEE Transactions on Vehicular Technology 43, n.º 1 (1994): 40–46. http://dx.doi.org/10.1109/25.282264.
Texto completoSchubert, M. "70V-to-5V differential CMOS input interface". Electronics Letters 30, n.º 4 (17 de febrero de 1994): 296–97. http://dx.doi.org/10.1049/el:19940235.
Texto completoObaid, Abdulmalik, Mina-Elraheb Hanna, Yu-Wei Wu, Mihaly Kollo, Romeo Racz, Matthew R. Angle, Jan Müller et al. "Massively parallel microwire arrays integrated with CMOS chips for neural recording". Science Advances 6, n.º 12 (marzo de 2020): eaay2789. http://dx.doi.org/10.1126/sciadv.aay2789.
Texto completoDeng, Fang Ming y Yi Gang He. "A Low-Cost Low-Power Capacitive Humidity Sensor in CMOS Technology". Applied Mechanics and Materials 556-562 (mayo de 2014): 1842–46. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1842.
Texto completoTesis sobre el tema "CMOS interface"
Berber, Feyza. "CMOS temperature sensor utilizing interface-trap charge pumping". Texas A&M University, 2005. http://hdl.handle.net/1969.1/4157.
Texto completoZhao, Dongning. "A low-noise CMOS interface for capacitive microaccelerometers". Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31715.
Texto completoHafizović, Sadik. "Neural interface and atomic-force microscope in CMOS technology /". Zürich : Physical Electronics Laboratory, ETH Zürich, 2006. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=16806.
Texto completoSilay, Kanber Mithat. "High Performance Cmos Capacitive Interface Circuits For Mems Gyroscopes". Master's thesis, METU, 2006. http://etd.lib.metu.edu.tr/upload/2/12607518/index.pdf.
Texto completom CMOS process. Fabricated interfaces are characterized by measuring their ac responses, noise response and transient characteristics for a sinusoidal input. It is observed that, biasing impedances up to 60 gigaohms can be obtained with subthreshold transistors. Self biasing architecture eliminates the need for biasing the source of the subthreshold transistor to set the output dc point to 0 V. Single ended SOG gyroscopes are characterized with the single ended capacitive interfaces, and a 45 dB gain improvement is observed with the addition of capacitive interface to the drive mode. Minimum resolvable capacitance change and displacement that can be measured are found to be 58.31 zF and 38.87 Fermi, respectively. The scale factor of the gyroscope is found to be 1.97 mV/(°
/sec) with a nonlinearity of only 0.001% in ±
100 °
/sec measurement range. The bias instability and angle random walk of the gyroscope are determined using Allan variance method as 2.158 °
/&
#8730
hr and 124.7 °
/hr, respectively.
Cho, Taeg Sang. "An energy efficient CMOS interface to carbon nanotube sensor arrays". Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40519.
Texto completoIncludes bibliographical references (p. 95-98).
A carbon nanotube is considered as a candidate for a next-generation chemical sensor. CNT sensors are attractive as they allow room-temperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major sources of power dissipation in other types of sensor systems. Nevertheless, a poor control of the CNT resistance poses a constraint on the attainable energy efficiency of the sensor platform. An investigation on the CNT sensors shows that the dynamic range of the interface should be 17 bits, while the resolution at each base resistance should be 7 bits. The proposed CMOS interface extends upon the previously published work to optimize the energy performance through both the architecture and circuit level innovations. The 17-bit dynamic range is attained by distributing the requirement into a 10-bit Analog-to-Digital Converter (ADC) and a 8-bit Digital-to-Analog Converter (DAC). An extra 1-bit leaves room for any unaccounted subblock performance error. Several system-level all-digital calibration schemes are proposed to account for DAC nonlinearity, ADC offset voltage, and a large variation in CNT base resistance. Circuit level techniques are employed to decrease the leakage current in the sensitive frontend node, to decrease the energy consumption of the ADC, and to efficiently control the DAC. The interface circuit is fabricated in 0.18 /m CMOS technology, and can operate at 1.83 kS/s sampling rate at 32 pW worst case power. The resistance measurement error across the whole dynamic range is less than 1.34% after calibration. A functionality of the full chemical sensor system has been demonstrated to validate the concepts introduced in this thesis.
by Taeg Sang Cho.
S.M.
Zhang, Tan Tan. "Nano-watt class CMOS interface circuits for wireless sensor nodes". Thesis, University of Macau, 2018. http://umaclib3.umac.mo/record=b3952097.
Texto completoHehn, Thorsten [Verfasser] y Yiannos [Akademischer Betreuer] Manoli. "A CMOS Integrated Interface Circuit for Piezoelectric Energy Harvesters = Eine CMOS-Integrierte Schnittstellenschaltung für Piezoelektrische Energy Harvester". Freiburg : Universität, 2014. http://d-nb.info/1123479119/34.
Texto completoFrey, Urs. "High-density neural interface and microhotplate gas sensor in CMOS technology /". Zürich : Physical Electronics Laboratory, ETH Zürich, 2007. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=17460.
Texto completoLeung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface". Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.
Texto completoBARTESELLI, EDOARDO. "Accurate Voltage Reference Generator for Audio Interface in 65/55nm CMOS Technology". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/364988.
Texto completoIn recent years, mobile devices are very complex and feature-rich that consume a lot of energy. For this reason, the electronics industry is pushing towards reducing power and current consumption in electronic devices to increase battery life. Everything has to be done while maintaining the same performance or improving it. This thesis presents an accurate voltage reference generator for audio interface in CMOS technology at 65/55nm and particular attention has been paid to current consumption. The reference is made up of a Bandgap voltage reference and a Low Dropout regulator. The topology chosen for the bandgap is a current mode bandgap with adjustable output resistor. This guarantees a reference voltage of less than 1.2V thanks to the sum of two currents instead of two voltages. A double loop was chosen for the LDO regulator to ensure rapid transient response. First, the voltage reference generator was simulated in CMOS technology at 65nm. In the 65nm simulations all targeted specifications were successfully achieved. For BG, power consumption is less than 5uA, DC PSR lower than -60dB and a temperature coefficient around 5ppm/°C. The LDO has a fast settling time lower 150ns, a PSR of less than -70dB in the audio band ([20, 20K]Hz) and a power consumption of less than 10uA. Then, it was simulated and measured with 55nm CMOS technology and three different prototypes were developed and tested. The results are not as good as the 65 nm results because this was the first time the technology was used. Then, the three developed test chips were used to understand the behavior of the technology and to compare simulations with measurements, but each test chip is an improvement on the previous one. The latest test chip features PSR very close to specifications for BG and LDO and power consumption of 5uA for the BG, 10uA for the LDO NM and 5uA for the LDO LP.
Libros sobre el tema "CMOS interface"
Incorporated, Advanced Micro Devices. High performance CMOS bus interface products data book. Sunnyvale, Calif: Advanced Micro Devices, 1989.
Buscar texto completoCarrara, Sandro. Bio/CMOS Interfaces and Co-Design. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-4690-3.
Texto completoDesign of custom CMOS amplifiers for nanoscale bio-interfaces. [New York, N.Y.?]: [publisher not identified], 2019.
Buscar texto completoLow, P. F., J. K. Mitchell, G. Sposito y H. van Olphen. Clay-Water Interface and its Rheological Implications. Editado por N. Güven y R. M. Pollastro. Boulder, Colorado: Clay Minerals Society, 1992. http://dx.doi.org/10.1346/cms-wls-4.
Texto completoInstitute, SAS, ed. Getting started with the SAS System in the CMS environment. 6a ed. Cary, NC: SAS Institute, 1997.
Buscar texto completoMeeting, Materials Research Society y Symposium C, "CMOS Gate-Stack Scaling-- Materials, Interfaces and Reliability Implications" (2009 : San Francisco, Calif.), eds. CMOS gate-stack scaling-- materials, interfaces and reliability implications: Symposium held April 14-16, 2009, San Francisco, california, U.S.A. Warrendale, Pa: Materials Research Society, 2009.
Buscar texto completoManoli, Yiannos y Thorsten Hehn. CMOS Circuits for Piezoelectric Energy Harvesters: Efficient Power Extraction, Interface Modeling and Loss Analysis. Springer, 2014.
Buscar texto completoManoli, Yiannos y Thorsten Hehn. CMOS Circuits for Piezoelectric Energy Harvesters: Efficient Power Extraction, Interface Modeling and Loss Analysis. Springer London, Limited, 2015.
Buscar texto completoManoli, Yiannos y Thorsten Hehn. CMOS Circuits for Piezoelectric Energy Harvesters: Efficient Power Extraction, Interface Modeling and Loss Analysis. Springer, 2016.
Buscar texto completoBenson, Niels. Organic CMOS technology by dielectric interface engineering: Chemically functionalized dielectrics for the control of OFET polarity / charge carrier transport properties. Suedwestdeutscher Verlag fuer Hochschulschriften, 2009.
Buscar texto completoCapítulos de libros sobre el tema "CMOS interface"
Hurley, P., O. Engström, D. Bauza y G. Ghibaudo. "Characterization of Interface Defects". En Nanoscale CMOS, 545–73. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch15.
Texto completoBernstein, Kerry, Keith M. Carrig, Christopher M. Durham, Patrick R. Hansen, David Hogenmiller, Edward J. Nowak y Norman J. Rohrer. "Interface Techniques". En High Speed CMOS Design Styles, 207–46. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4615-5573-5_6.
Texto completoMaurath, Dominic y Yiannos Manoli. "Switched-Inductor Capacitive Interface". En CMOS Circuits for Electromagnetic Vibration Transducers, 215–40. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9272-1_8.
Texto completoBindal, Ahmet. "TTL Logic and CMOS-TTL Interface". En Electronics for Embedded Systems, 89–122. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-39439-8_4.
Texto completoHehn, Thorsten y Yiannos Manoli. "Analysis of Different Interface Circuits". En CMOS Circuits for Piezoelectric Energy Harvesters, 41–56. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9288-2_3.
Texto completoMaurath, Dominic y Yiannos Manoli. "Input Load Adapting Charge Pump Interface". En CMOS Circuits for Electromagnetic Vibration Transducers, 159–97. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9272-1_6.
Texto completoTokuda, Takashi, Toshihiko Noda, Kiyotaka Sasagawa y Jun Ohta. "CMOS-Based Neural Interface Device for Optogenetics". En Optogenetics, 375–89. Tokyo: Springer Japan, 2015. http://dx.doi.org/10.1007/978-4-431-55516-2_27.
Texto completoTokuda, Takashi, Makito Haruta, Kiyotaka Sasagawa y Jun Ohta. "CMOS-Based Neural Interface Device for Optogenetics". En Advances in Experimental Medicine and Biology, 585–600. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-8763-4_41.
Texto completoThewes, Roland, Alexander Frey, Meinrad Schienle, Christian Paulus, Birgit Holzapfl, Martin Jenkner, Petra Schindler-Bauer y Franz Hofmann. "CMOS Sensor Interface Arrays for DNA Detection". En Analog Circuit Design, 65–89. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4020-2805-2_4.
Texto completoKhadouri, Saleh H., Gerard C. M. Meijer y Frank M. L. Van Der Goes. "A CMOS Interface for Thermocouples with Reference-Junction Compensation". En Smart Sensor Interfaces, 73–86. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6061-6_7.
Texto completoActas de conferencias sobre el tema "CMOS interface"
Hei Wong, Hiroshi Iwai y Kuniyuki Kakushima. "Material and interface instabilities of high-κ MOS gate dielectric films". En 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570990.
Texto completoVelayudhan, V., J. Martin-Martinez, R. Rodriguez, M. Porti, M. Nafria, X. Aymerich, C. Medina y F. Gamiz. "TCAD simulation of interface traps related variability in bulk decananometer mosfets". En 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957078.
Texto completoShiraishi, K., Y. Akasaka, K. Torii, T. Nakayama, S. Miyazaki, T. Nakaoka, H. Watanabe et al. "New findings in nano-scale interface physics and their relations to nano-CMOS technologies". En 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570992.
Texto completoAya Seike, Itsutaku Sano, Keisaku Yamada y Iwao Ohdomari. "Evaluation of phosphorus diffusion in the confined nano-wire under the influence of Si/SiO2 interface". En 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570985.
Texto completoBenson, Niels, Marcus Ahles, Martin Schidleja, Andrea Gassmann, Eric Mankel, Thomas Mayer, Christian Melzer, Roland Schmechel y Heinz von Seggern. "Organic CMOS technology by interface treatment". En SPIE Optics + Photonics, editado por Zhenan Bao y David J. Gundlach. SPIE, 2006. http://dx.doi.org/10.1117/12.680049.
Texto completoAbbott, Jeffrey, Tianyang Ye, Hongkun Park y Donhee Ham. "CMOS interface with biological molecules and cells". En ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC). IEEE, 2019. http://dx.doi.org/10.1109/esscirc.2019.8902832.
Texto completoTokuda, Takashi, Jiawen Li, Mizuki Takeuchi, Masato Fukamachi y Yasufumi Yokoshiki. "CMOS-based distributed implantable brain interface device". En 2022 20th IEEE Interregional NEWCAS Conference (NEWCAS). IEEE, 2022. http://dx.doi.org/10.1109/newcas52662.2022.9842281.
Texto completoWaeny, Martin y Peter Schwider. "CMOS megapixel digital camera with CameraLink interface". En Electronic Imaging 2002, editado por Morley M. Blouke, John Canosa y Nitin Sampat. SPIE, 2002. http://dx.doi.org/10.1117/12.463420.
Texto completoRifaan, Mochammad y Robert Rieger. "Attenuating CMOS low-frequency capacitive sensor interface". En 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2017. http://dx.doi.org/10.1109/edssc.2017.8126408.
Texto completoMorell, William y Ashok Srivastava. "Novel, Low-power ECRL-CMOS Interface Circuit". En 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2019. http://dx.doi.org/10.1109/mwscas.2019.8885081.
Texto completoInformes sobre el tema "CMOS interface"
Lim, Chee. High-performance Input/Output Circuit for CMOS Integrated Circuit Interface. Portland State University Library, enero de 2000. http://dx.doi.org/10.15760/etd.7186.
Texto completoSainudeen, Zuhail y Navid Yazdi. Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem. Fort Belvoir, VA: Defense Technical Information Center, julio de 2001. http://dx.doi.org/10.21236/ada402437.
Texto completoSaripalli, Ganesh. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories. Office of Scientific and Technical Information (OSTI), enero de 2002. http://dx.doi.org/10.2172/806590.
Texto completoLi, Honghai, Lihwa Lin, Cody Johnson, Yan Ding, Mitchell Brown, Tanya Beck, Alejandro Sánchez y Weiming Wu. A revisit and update on the verification and validation of the Coastal Modeling System (CMS) : report 1--hydrodynamics and waves. Engineer Research and Development Center (U.S.), septiembre de 2022. http://dx.doi.org/10.21079/11681/45444.
Texto completoIzhar, Shamay, Maureen Hanson y Nurit Firon. Expression of the Mitochondrial Locus Associated with Cytoplasmic Male Sterility in Petunia. United States Department of Agriculture, febrero de 1996. http://dx.doi.org/10.32747/1996.7604933.bard.
Texto completoChapman, Ray, Phu Luong, Sung-Chan Kim y Earl Hayter. Development of three-dimensional wetting and drying algorithm for the Geophysical Scale Transport Multi-Block Hydrodynamic Sediment and Water Quality Transport Modeling System (GSMB). Engineer Research and Development Center (U.S.), julio de 2021. http://dx.doi.org/10.21079/11681/41085.
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