Literatura académica sobre el tema "CMOS device"
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Artículos de revistas sobre el tema "CMOS device"
Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty y Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application". Indonesian Journal of Electrical Engineering and Computer Science 28, n.º 2 (1 de noviembre de 2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.
Texto completoXiong, Qi, Shao Hua Zhou y Jiang Ping Zeng. "The Analysis of Device Model in CMOS Integrated Temperature Sensor". Advanced Materials Research 986-987 (julio de 2014): 1600–1605. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1600.
Texto completoChiovetti, Bob. ""Chip Wars" Heat Up On The Digital Imaging Front". Microscopy Today 7, n.º 2 (marzo de 1999): 3–4. http://dx.doi.org/10.1017/s1551929500063847.
Texto completoShawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque y Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes". International Journal of High Speed Electronics and Systems 27, n.º 03n04 (septiembre de 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.
Texto completoWong, Hei. "Abridging CMOS Technology". Nanomaterials 12, n.º 23 (29 de noviembre de 2022): 4245. http://dx.doi.org/10.3390/nano12234245.
Texto completoFOSSUM, JERRY G. "A SIMULATION-BASED PREVIEW OF EXTREMELY SCALED DOUBLE-GATE CMOS DEVICES AND CIRCUITS". International Journal of High Speed Electronics and Systems 12, n.º 02 (junio de 2002): 563–72. http://dx.doi.org/10.1142/s0129156402001460.
Texto completoMOONEY, P. M. "MATERIALS FOR STRAINED SILICON DEVICES". International Journal of High Speed Electronics and Systems 12, n.º 02 (junio de 2002): 305–14. http://dx.doi.org/10.1142/s0129156402001265.
Texto completoBirla, Shilpi, Sudip Mahanti y Neha Singh. "Leakage reduction technique for nano-scaled devices". Circuit World 47, n.º 1 (29 de mayo de 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.
Texto completoWon, Jongun, Youngchae Roh, Minseung Kang, Yeaji Park, Jaehyeon Kang, Hyeongjun Seo, Changhoon Joe y SangBum Kim. "A Capacitor-Based Synaptic Device with IGZO Access Transistors for Neuromorphic Computing". ECS Transactions 111, n.º 2 (19 de mayo de 2023): 133–36. http://dx.doi.org/10.1149/11102.0133ecst.
Texto completoTang, L., S. Latif y D. A. B. Miller. "Plasmonic device in silicon CMOS". Electronics Letters 45, n.º 13 (2009): 706. http://dx.doi.org/10.1049/el.2009.0839.
Texto completoTesis sobre el tema "CMOS device"
Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.
Texto completoYu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
Texto completoPh.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
Jain, Ishita. "Modeling and simulation of self-heating effects in sub-14NM CMOS devices". Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8137.
Texto completoWu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture". Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Texto completoThe continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
Xu, Chen. "Low voltage CMOS digital imaging architecture with device scaling considerations /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20XU.
Texto completoIncludes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.
Kopalle, Deepika Niu Guofu. "RF linearity analysis in nano scale CMOS using harmonic balance device simulations". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/KOPALLE_DEEPIKA_43.pdf.
Texto completoOdanaka, Shinji. "A STUDY OF NUMERICAL PROCESS AND DEVICE MODELING CAD FOR SUBMICROMETER CMOS". Kyoto University, 1990. http://hdl.handle.net/2433/86214.
Texto completoWang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Texto completoHUSSAIN, IZHAR. "TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies". Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710840.
Texto completoAbel, Christopher J. "An investigation of nonideal process and device effects in fundamental CMOS analog subcircuits /". The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487865929454587.
Texto completoLibros sobre el tema "CMOS device"
Simon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.
Buscar texto completoSimon, Deleonibus, ed. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.
Buscar texto completoIncorporated, Advanced Micro Devices. PAL device data book: Bipolar and CMOS. [Sunnyvale, CA]: Advanced Micro Devices Inc., 1990.
Buscar texto completoYtterdal, Trond, Yuhua Cheng y Tor A. Fjeldly. Device Modeling for Analog and RF CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2003. http://dx.doi.org/10.1002/0470863803.
Texto completoDevice modeling for analog and RF CMOS circuit design. Chichester: John Wiley & Sons, 2004.
Buscar texto completoSemenov, Oleg, Hossein Sarbishaei y Manoj Sachdev. ESD Protection Device and Circuit Design for Advanced CMOS Technologies. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8301-3.
Texto completoHossein, Sarbishaei y Sachdev Manoj, eds. ESD protection device and circuit design for advanced CMOS technologies. [Dordrecht]: Springer, 2008.
Buscar texto completoMadrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Reading, Mass: Addison-Wesley, 1992.
Buscar texto completoUnited States. National Aeronautics and Space Administration., ed. Application of linear response theory to experimental data of simultasneous radiation and annealing response of a CMOS device. [Washington, DC: National Aeronautics and Space Administration, 1989.
Buscar texto completoL, Helms Harry, ed. CMOS devices: 1987 source book. Englewood Cliffs, N.J: Technipubs, 1987.
Buscar texto completoCapítulos de libros sobre el tema "CMOS device"
Martinez, A., A. Asenov y M. Pala. "NEGF for 3D Device Simulation of Nanometric Inhomogenities". En Nanoscale CMOS, 335–80. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch10.
Texto completoGrasser, T., R. Strasser, M. Knaipp, K. Tsuneno, H. Masuda y S. Selberherr. "Device Simulator Calibration for Quartermicron CMOS Devices". En Simulation of Semiconductor Processes and Devices 1998, 93–96. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_26.
Texto completoDavies, M. S. y P. D. T. O’Connor. "Reliability Assessment of Cmos Asic Designs". En Semiconductor Device Reliability, 137–46. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-009-2482-6_8.
Texto completoSolomon, P. M. "Device Proposals Beyond Silicon CMOS". En Future Trends in Microelectronics, 127–40. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2010. http://dx.doi.org/10.1002/9780470649343.ch10.
Texto completoGharavi, Sam y Babak Heydari. "mm-Wave Device Modeling". En Ultra High-Speed CMOS Circuits, 5–21. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_2.
Texto completoGharavi, Sam y Babak Heydari. "mm-Wave Device Optimization". En Ultra High-Speed CMOS Circuits, 23–34. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_3.
Texto completoDubois, E., G. Larrieu, R. Valentin, N. Breil y F. Danneville. "Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration". En Nanoscale CMOS, 157–204. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch5.
Texto completoLabiod, Samir, Abdelmalek Mouatsi, Zakaria Hadef y Billel Smaani. "Conventional CMOS circuit design". En Device Circuit Co-Design Issues in FETs, 21–56. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-2.
Texto completoSalama, Husien, Alain Tshipamba y Khalifa Ahmed. "Modeling for CMOS circuit design". En Device Circuit Co-Design Issues in FETs, 1–20. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-1.
Texto completoCham, Kit Man, Soo-Young Oh, Daeje Chin y John L. Moll. "Transistor Design for Submicron CMOS Technology". En Computer-Aided Design and VLSI Device Development, 171–97. Boston, MA: Springer US, 1986. http://dx.doi.org/10.1007/978-1-4613-2553-6_9.
Texto completoActas de conferencias sobre el tema "CMOS device"
Horstmann, Manfred y Reinhard Mahnkopf. "CMOS Devices - Device/Design Interaction". En 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4418974.
Texto completoChang, Chih-Sheng y Akira Hokazono. "CMOS Devices - Advanced Device Structures". En 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4419091.
Texto completoXiao, Yang, Martin A. Trefzer, Scott Roy, James Alfred Walker, Simon J. Bale y Andy M. Tyrrell. "Circuit optimization using device layout motifs". En 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957081.
Texto completoHatakeyama, T., K. Fushinobu y K. Okazaki. "Investigation of Device Interactions Between Two MOSFETs in Si CMOS". En ASME 2008 International Mechanical Engineering Congress and Exposition. ASMEDC, 2008. http://dx.doi.org/10.1115/imece2008-67204.
Texto completo"Silicon CMOS". En 2007 65th Annual Device Research Conference. IEEE, 2007. http://dx.doi.org/10.1109/drc.2007.4373644.
Texto completoTang, Liang, Salman Latif y David A. B. Miller. "Plasmonic device in Si CMOS". En LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS 2008). IEEE, 2008. http://dx.doi.org/10.1109/leos.2008.4688527.
Texto completoTrivedi, Fossum y Vandooren. "Non-classical CMOS device design". En 2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03). IEEE, 2003. http://dx.doi.org/10.1109/soi.2003.1242935.
Texto completoSasagawa, Kiyotaka, Makito Haruta, Yasumi Ohta, Hironari Takehara y Jun Ohta. "Implantable Fluorescent CMOS Imaging Device". En 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2020. http://dx.doi.org/10.1109/edtm47692.2020.9117820.
Texto completoReddy, Anyam Apuroop Kumar, Syed Azeemuddin y M. R. Sayeh. "A CMOS proteretic bistable device". En 2016 IEEE Annual India Conference (INDICON). IEEE, 2016. http://dx.doi.org/10.1109/indicon.2016.7839016.
Texto completo"Emerging CMOS devices". En 2016 74th Annual Device Research Conference (DRC). IEEE, 2016. http://dx.doi.org/10.1109/drc.2016.7548398.
Texto completoInformes sobre el tema "CMOS device"
James F. Christian, PhD y PhD Christopher Stapels. Next-Generation Active Pixel Sensor Device With CMOS APDs. Office of Scientific and Technical Information (OSTI), marzo de 2007. http://dx.doi.org/10.2172/900308.
Texto completoSmith, J. H., S. Montague, J. J. Sniegowski y J. R. Murray. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS. Office of Scientific and Technical Information (OSTI), octubre de 1996. http://dx.doi.org/10.2172/380312.
Texto completoBrotman, Susan. The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter. Portland State University Library, enero de 2000. http://dx.doi.org/10.15760/etd.6585.
Texto completoKoga, Rokutaro y Wojciech A. Kolasinski. Heavy-Ion-Induced Snapback in CMOS Devices. Fort Belvoir, VA: Defense Technical Information Center, agosto de 1990. http://dx.doi.org/10.21236/ada226765.
Texto completoPlewa, Matthew I. y Justin Vandenbroucke. Detecting cosmic rays using CMOS sensors in consumer devices. Ames (Iowa): Iowa State University. Library. Digital Press, enero de 2015. http://dx.doi.org/10.31274/ahac.9757.
Texto completoKoh, Seong J. y Choong-Un Kim. Fabrication of Single Electron Devices within the Framework of CMOS Technology. Fort Belvoir, VA: Defense Technical Information Center, diciembre de 2008. http://dx.doi.org/10.21236/ada491301.
Texto completoSmith, J. H., S. Montague, J. J. Sniegowski y P. J. McWhorter. Embedded micromechanical devices for the monolithic integration of MEMS and CMOS. Office of Scientific and Technical Information (OSTI), julio de 1995. http://dx.doi.org/10.2172/114489.
Texto completoFonstad, Clifton G. Monolithic Integration of Optoelectronic Devices and Si-CMOS on Gallium Arsenide. Fort Belvoir, VA: Defense Technical Information Center, noviembre de 2000. http://dx.doi.org/10.21236/ada391141.
Texto completoStaple, B. D., H. A. Watts, C. Dyck, A. P. Griego, F. W. Hewlett y J. H. Smith. SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices. Office of Scientific and Technical Information (OSTI), agosto de 1998. http://dx.doi.org/10.2172/663240.
Texto completoKoga, R., S. J. Hansel, W. R. Crain, K. B. Crawford, S. D. Pinkerton, J. Quan y M. Maher. Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 Volts. Fort Belvoir, VA: Defense Technical Information Center, enero de 1998. http://dx.doi.org/10.21236/ada349539.
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