Literatura académica sobre el tema "CHIRP INPUT"
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Artículos de revistas sobre el tema "CHIRP INPUT"
Liu, Weici. "Effect of initial chirp for input pulse on supercontinuum generation". Journal of Physics: Conference Series 2029, n.º 1 (1 de septiembre de 2021): 012019. http://dx.doi.org/10.1088/1742-6596/2029/1/012019.
Texto completoMulsow, Jason, James J. Finneran, Madelyn G. Strahan, Dorian S. Houser y Robert F. Burkard. "Input compensation of dolphin and sea lion auditory brainstem responses using frequency-modulated up-chirps". Journal of the Acoustical Society of America 154, n.º 2 (1 de agosto de 2023): 739–50. http://dx.doi.org/10.1121/10.0020566.
Texto completoSolyman, Ahmad AA, Hani Attar, Mohammad R. Khosravi y Baki Koyuncu. "MIMO-OFDM/OCDM low-complexity equalization under a doubly dispersive channel in wireless sensor networks". International Journal of Distributed Sensor Networks 16, n.º 6 (junio de 2020): 155014772091295. http://dx.doi.org/10.1177/1550147720912950.
Texto completovan Brederode, J. F. M. y A. J. Berger. "GAD67-GFP+ Neurons in the Nucleus of Roller. II. Subthreshold and Firing Resonance Properties". Journal of Neurophysiology 105, n.º 1 (enero de 2011): 249–78. http://dx.doi.org/10.1152/jn.00492.2010.
Texto completoTang, Qing y Guanshen Zhang. "Chirp encoded joint transform correlators with input scale search". Optics Communications 107, n.º 1-2 (abril de 1994): 23–27. http://dx.doi.org/10.1016/0030-4018(94)90097-3.
Texto completoTan, See Ling, Yu-Fu Chen, Chieh-Yu Liu, Kuo-Chung Chu y Pei-Chun Li. "Shortened neural conduction time in young adults with tinnitus as revealed by chirp-evoked auditory brainstem response". Journal of the Acoustical Society of America 153, n.º 4 (abril de 2023): 2178–89. http://dx.doi.org/10.1121/10.0017789.
Texto completoMunaweera, P. C. T. y K. A. I. L. Wijewardena Gamalath. "Simulation of Pulse Propagation in Optical Fibers". International Letters of Chemistry, Physics and Astronomy 64 (febrero de 2016): 159–70. http://dx.doi.org/10.18052/www.scipress.com/ilcpa.64.159.
Texto completoMunaweera, P. C. T. y K. A. I. L. Wijewardena Gamalath. "Simulation of Pulse Propagation in Optical Fibers". International Letters of Chemistry, Physics and Astronomy 64 (15 de febrero de 2016): 159–70. http://dx.doi.org/10.56431/p-qb35f6.
Texto completoZupanc, Günther K. H. y Leonard Maler. "Evoked chirping in the weakly electric fish Apteronotus leptorhynchus: a quantitative biophysical analysis". Canadian Journal of Zoology 71, n.º 11 (1 de noviembre de 1993): 2301–10. http://dx.doi.org/10.1139/z93-323.
Texto completoDon, Manuel, Claus Elberling y Erin Maloff. "Input and Output Compensation for the Cochlear Traveling Wave Delay in Wide-Band ABR Recordings: Implications for Small Acoustic Tumor Detection". Journal of the American Academy of Audiology 20, n.º 02 (febrero de 2009): 099–108. http://dx.doi.org/10.3766/jaaa.20.2.3.
Texto completoTesis sobre el tema "CHIRP INPUT"
Hadi, Muhammad Usman. "Digital predistortion for compensation of nonlinearities in Radio over Fiber Links". Master's thesis, Alma Mater Studiorum - Università di Bologna, 2016.
Buscar texto completoLinke, Kevin Robert. "An on-chip input driver for a high-voltage SAR ADC". Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91837.
Texto completoCataloged from PDF version of thesis.
Includes bibliographical references (page 49).
This thesis describes the design of a novel on-chip input driver for a SAR ADC. The driver achieves performance gains relative to off-chip alternatives by being integrated into the signal path of the ADC between the sampling switches and sampling capacitor. This placement allows for auto-zeroing the offset of the driver and reducing flicker noise. Additional performance benefits are possible because the driver can be optimized for the specific load and timings of the ADC. The most important benefit of an on-chip input driver is that it simplifies the design process for the ADC user by eliminating the external op-amp and reducing the constraints on the external filter by reducing input current load. Design simplicity is especially important to users in high-voltage SAR ADC applications, so the input driver is designed for an ADC with a +/- 10.24 V input range and +/- 15 V supply rails. This high-voltage input relaxes noise and headroom constraints, but makes device overvoltage a significant concern. The driver is designed in a BiCMOS process, and simulation results with a computer-modeled ADC are presented here. In these simulations, the driver achieves a THD of -124.7 dB at 2 kHz and a noise voltage spectral density of 5.5 nV / [square root of] Hz with a power consumption of 27.6 mW. The LT1469, an example of a state-of-the-art external input driver, has a THD of -123 dB at 2 kHz, a noise voltage spectral density of 5 nV / [square root of] Hz, and a power consumption of 123 mW.
by Kevin Robert Linke.
M. Eng.
Zhu, Yan. "Microfluidic Technology for Low-Input Epigenomic Analysis". Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/83402.
Texto completoPh. D.
Fan, Su Yan. "Wide-input-range supply voltage tolerant capacitive sensor readout using on-chip solar cell". Thesis, University of Macau, 2015. http://umaclib3.umac.mo/record=b3335734.
Texto completoBurrow, Ryan David. "Enhancing Input/Output Correctness, Protection, Performance, and Scalability for Process Control Platforms". Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/89903.
Texto completoMaster of Science
Complex modern systems, from unmanned aircraft system to industrial plants are almost always controlled digitally. These digital control systems (DCSes) need to be verified for correctness since failures can have disastrous consequences. However, proving that a DCS will always act correctly can be infeasible if the system is too complex. In addition, with the growth of inter-connectivity of systems through the internet, malicious actors have more access than ever to attempt to cause these systems to deviate from their proper operation. This thesis seeks to solve these problems by introducing a new architecture for DCSes that uses isolated components that can be verified for correctness. In addition, safety monitors are implemented as a part of the architecture to prevent unsafe operation.
Wilson, James Edward. "Design techniques for first pass silicon in SOC radio transceivers". Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1180555088.
Texto completoZvěřina, Martin. "Výpočtová simulace procesu třískového obrábění". Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2010. http://www.nusl.cz/ntk/nusl-229040.
Texto completoYoo, Sungjong. "Electromagnetic Modeling of Multi-Dimensional Scale Problems: Nanoscale Solar Materials, RF Electronics, Wearable Antennas". Diss., The University of Arizona, 2014. http://hdl.handle.net/10150/333484.
Texto completoMANDAVIA, DHAIVAT. "SLIDING MODE OBSERVERS FOR OBSERVING THE DYNAMICS OF NUCLEAR REACTOR SYSTEMS". Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14612.
Texto completoPeng, Chih-Yang y 彭志洋. "Block and Input/Ouput Buffer Placement in Flip-Chip Design". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/61649670636516290542.
Texto completo國立臺灣大學
電子工程學研究所
91
The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as well as the delay skew of the paths. In this thesis, we propose a hierarchical top-down method for the block and input/output buffer placement in flip-chip design. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the following two steps: the alternating and interacting global optimization step and the partitioning step. The global optimization step places modules based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the modules are divided into two groups according to their coordinates and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of modules, defined by the ratio of the total module area to the chip area. At last, we refine the placement by perturbing modules inside a subregion as well as in different subregions. Compared with the placement using the B*-tree alone, our method obtains significantly better results, with an average cost of only 48.4\% of that obtained by using the B*-tree alone.
Libros sobre el tema "CHIRP INPUT"
Nicopoulos, Chrysostomos. Network-on-Chip Architectures: A Holistic Design Exploration. Dordrecht: Springer Netherlands, 2009.
Buscar texto completoElizabeth, Theibert, ed. Potato chip economics: Everything you need to know about business clearly and concisely explained. Lanham: John Hunt Publishing, 2013.
Buscar texto completoKeating, Michael. Simple art of SoC design: Closing the gap between RTL and ESL. New York: Springer, 2011.
Buscar texto completoChen, Sao-Jie. Hardware Software Co-Design of a Multimedia SOC Platform. Dordrecht: Springer Netherlands, 2009.
Buscar texto completoEmbedded SoPC design with Altera NiosII processor and VHDL examples. Hoboken, N.J: Wiley, 2011.
Buscar texto completoChi-Ying, Tsui, Reis Ricardo, Choy Oliver C. S y SpringerLink (Online service), eds. VLSI-SoC: Advanced Research for Systems on Chip: 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012.
Buscar texto completoZhou, Clarence. LIN System Basis Chip Including LIN Transceiver, Voltage Regulator and Wake-Input. Microchip Technology Incorporated, 2018.
Buscar texto completoWolters-Broder, Lisa. ATA663232/55 LIN System Basis Chip Including LIN Transceiver, Voltage Regulator and Wake-Input. Microchip Technology Incorporated, 2017.
Buscar texto completoDas, Chita R., Springer, Chrysostomos Nicopoulos y Vijaykrishnan Narayanan. Network-on-Chip Architectures: A Holistic Design Exploration. Springer Netherlands, 2012.
Buscar texto completoReis, Ricardo, Ian O'Connor, Sergei Kostin, Thomas Hollstein, Jaan Raik y Anton Tšertov. VLSI-SoC : System-on-Chip in the Nanoscale Era – Design, Verification and Reliability: 24th IFIP WG 10.5/IEEE International Conference on Very Large ... and Communication Technology ). Springer, 2017.
Buscar texto completoCapítulos de libros sobre el tema "CHIRP INPUT"
Deng, Ke, Qinye Yin, Yiwen Zhang y Ming Luo. "Chip-by-Chip Iterative Multiuser Detection for VBLAST Coded Multiple-Input Multiple-Output Systems". En Networking - ICN 2005, 26–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/978-3-540-31957-3_4.
Texto completoWang, Xinyu, Zhigang Yu y Huazhen Xu. "A Simple and Efficient Input Selection Function for Networks-on-Chip". En Distributed Computing and Networking, 525–39. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-25959-3_39.
Texto completoXiong, Guoqiang, Yue Cao, Jun Chen y Beixi Kong. "Screening Method of Chip-Dependent Industries Based on Input-Output Theory". En Proceedings of the Fifteenth International Conference on Management Science and Engineering Management, 275–84. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-79203-9_21.
Texto completoSeyd-Darwish, I., P. Chavel, J. Taboury, F. Devos, T. Maurin y R. Reynaud. "Optical Input and Output Functions for a Cellular Automaton on a Silicon Chip". En Optical Information Technology, 143–52. Berlin, Heidelberg: Springer Berlin Heidelberg, 1993. http://dx.doi.org/10.1007/978-3-642-78140-7_17.
Texto completoWang, Xinyu, Zhigang Yu y Huazhen Xu. "Improving Routing Efficiency for Networks-on-Chip through an Efficient Input Selection Strategy". En Future Control and Automation, 445–52. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31006-5_52.
Texto completoMuroyama, Masanori, Tohru Ishihara y Hiroto Yasuura. "Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption". En Lecture Notes in Computer Science, 62–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_7.
Texto completoNejad, Ebrahim Behrouzian, Ahmad Khademzadeh, Kambiz Badie, Amir Masoud Rahmani, Mohammad Behrouzian Nejad y Ahmad Zadeali. "ICAIS: Improved Contention Aware Input Selection Technique to increase routing efficiency for Network-On-Chip". En Lecture Notes in Electrical Engineering, 289–97. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21697-8_37.
Texto completoBrahma, Sandipan y Steven Henikoff. "CUT&RUN Profiling of the Budding Yeast Epigenome". En Methods in Molecular Biology, 129–47. New York, NY: Springer US, 2022. http://dx.doi.org/10.1007/978-1-0716-2257-5_9.
Texto completoCruz, J. M. y L. O. Chua. "A 16 x 16 Cellular Neural Network Universal Chip: The First Complete Single-Chip Dynamic Computer Array with Distributed Memory and with Gray-Scale Input-Output". En Cellular Neural Networks and Analog VLSI, 3–13. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-4730-0_1.
Texto completoUma, R., H. Sarojadevi y V. Sanju. "Routing of Flits in Parallel Input Interface Scenario in a Generalized Network-On-Chip Framework Using Wormhole Flow Control Algorithm". En Emerging Research in Computing, Information, Communication and Applications, 679–93. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1342-5_52.
Texto completoActas de conferencias sobre el tema "CHIRP INPUT"
Sun, Zuwen y Natalie Baddour. "The Effect of Pulse Compression Chirp Parameters on Profilometry Information and Resolution". En ASME 2018 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/detc2018-85613.
Texto completoReddy, Bhattagiri Lekhan, Kunta Prasanth Kumar, Akula Shanmukha Naga Veera Sai, K. Anuraj y S. S. Poorna. "Comparative Study of Convergence of Optimization Algorithms with Chirp Signal Input". En 2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS). IEEE, 2021. http://dx.doi.org/10.1109/icaccs51430.2021.9442023.
Texto completoIslam, M. N., C. F. Soccolich y C. J. Chen. "All-optical time domain chirp switches". En OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.wm2.
Texto completoGrycewicz, Thomas J. y Bahram Javidi. "Experimental demonstration of a chirp-modulated joint transfrom correlator using separate input SLMs". En SPIE's 1995 International Symposium on Optical Science, Engineering, and Instrumentation, editado por Bahram Javidi y Joseph L. Horner. SPIE, 1995. http://dx.doi.org/10.1117/12.217646.
Texto completoKATO, Hiroki y Akihiro MARUTA. "Power and Chirp Tolerances of Input Pulse for Dispersion Managed Soliton Transmission System". En Optical Amplifiers and Their Applications. Washington, D.C.: OSA, 1999. http://dx.doi.org/10.1364/oaa.1999.thd8.
Texto completoTang, Qing y Bahram Javidi. "Multiple-objects recognition by using chirp- encoded nonlinear joint-transform correlators". En OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.wr.3.
Texto completoMilián, C., A. Jarnac, Y. Brelet, V. Jukna, A. Houard, A. Mysyrowicz y A. Couairon. "Nonlinear energy deposition in water from fs-laser pulses: effect of the input chirp". En SPIE Photonics Europe, editado por Benjamin J. Eggleton, Alexander L. Gaeta, Neil G. R. Broderick, Alexander V. Sergienko, Arno Rauschenbeutel y Thomas Durt. SPIE, 2014. http://dx.doi.org/10.1117/12.2051676.
Texto completoZachinyaev, Yuriy y Konstantin Rumyantsev. "The optimal input optical pulse shape for the self-phase modulation based chirp generator". En INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, MATERIALS AND APPLIED SCIENCE. Author(s), 2018. http://dx.doi.org/10.1063/1.5032043.
Texto completoHansen, P. B., S. L. Danielsen, C. Joergensen, K. E. Stubkjaer, M. Schilling, K. Wünstel, W. Idler, P. Doussiere y F. Pommerau. "All optical wavelength conversion schemes for increased input power dynamic range". En Photonics in Switching. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/ps.1997.pthd3.
Texto completoAngarita, John, Daniel Doyle, Gustavo Gargioni y Jonathan Black. "Input Excitation Analysis for Black-Box Quadrotor Model System Identification". En ASME 2020 Dynamic Systems and Control Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/dscc2020-3159.
Texto completoInformes sobre el tema "CHIRP INPUT"
Thompson, Marshall y Ramez Hajj. Flexible Pavement Recycling Techniques: A Summary of Activities. Illinois Center for Transportation, julio de 2021. http://dx.doi.org/10.36501/0197-9191/21-022.
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