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Artículos de revistas sobre el tema "Charge storage memory"

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Publicado: 25 de mayo de 2024

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1

Mabrook, M. F., Youngjun Yun, C. Pearson, D. A. Zeze y M. C. Petty. "Charge Storage in Pentacene/Polymethylmethacrylate Memory Devices". IEEE Electron Device Letters 30, n.º 6 (junio de 2009): 632–34. http://dx.doi.org/10.1109/led.2009.2018128.

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2

Spassov, Dencho y Albena Paskaleva. "Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks". Nanomaterials 13, n.º 17 (30 de agosto de 2023): 2456. http://dx.doi.org/10.3390/nano13172456.

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The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.
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3

Tsoukalas, Dimitris, S. Kolliopoulou, P. Dimitrakis, P. Normand y M. C. Petty. "Nanoparticles for Charge Storage Using Hybrid Organic Inorganic Devices". Advances in Science and Technology 54 (septiembre de 2008): 451–57. http://dx.doi.org/10.4028/www.scientific.net/ast.54.451.

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We present a concept for integration of low temperature fabricated memory devices in a 3-D architecture using a hybrid silicon-organic technology. The realization of electrically erasable read-only memory (EEPROM) like device is based on the fabrication of a V-groove SiGe MOSFET, the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir-Blodgett (LB) technique. Such structures were processed at a temperature lower than 400°C following a process based on wafer bonding. The electrical characteristics of the final hybrid MISFET memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented.
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4

Gong, Changjie, Xin Ou, Bo Xu, Xuexin Lan, Yan Lei, Jianxin Lu, Yan Chen et al. "Enhanced charge storage performance in AlTi4Ox/Al2O3multilayer charge trapping memory devices". Japanese Journal of Applied Physics 53, n.º 8S3 (7 de julio de 2014): 08NG02. http://dx.doi.org/10.7567/jjap.53.08ng02.

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5

Tang, Zhen-Jie, Rong Li y Jiang Yin. "The charge storage characteristics of ZrO2nanocrystallite-based charge trap nonvolatile memory". Chinese Physics B 22, n.º 6 (junio de 2013): 067702. http://dx.doi.org/10.1088/1674-1056/22/6/067702.

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6

Tsoukalas, Dimitris y Emanuele Verrelli. "Inorganic Nanoparticles for either Charge Storage or Memristance Modulation". Advances in Science and Technology 77 (septiembre de 2012): 196–204. http://dx.doi.org/10.4028/www.scientific.net/ast.77.196.

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We present prototype memory devices using metallic and metal oxide nanoparticles obtained by a physical deposition technique. The two memory device examples demonstrated concern the use of platinum nanoparticles for flash-type memories and the use of titanium oxide nanoparticles for resistive memories. Both approaches give interesting device memory properties with resistive memories being still in an early exploratory phase.
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7

Bandić, Zvonimir Z., Dmitri Litvinov y M. Rooks. "Nanostructured Materials in Information Storage". MRS Bulletin 33, n.º 9 (septiembre de 2008): 831–37. http://dx.doi.org/10.1557/mrs2008.178.

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AbstractThe ever-increasing demand for information storage has pushed research and development of nonvolatile memories, particularly magnetic disk drives and silicon-based memories, to areal densities where bit sizes are approaching nanometer dimensions. At this level, material and device phenomena make further scaling increasingly difficult. The difficulties are illustrated in the examples of magnetic media and flash memory, such as thermal instability of sub-100-nm bits in magnetic memory and charge retention in flash memory, and solutions are discussed in the form of patterned media and crosspoint memories. The materials-based difficulties are replaced by nanofabrication challenges, requiring the introduction of new techniques such as nanoimprinting lithography for cost-effective manufacturing and self-assembly for fabrication on the sub-25-nm scale. Articles in this issue describe block-copolymer lithographic fabrication of patterned media, materials studies on the scaling limits of phase-change-based crosspoint memories, nanoscale fabrication using imprint lithography, and biologically inspired protein-based memory.
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8

Lee, Meng Chuan y Hin Yong Wong. "Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM". Journal of Nanomaterials 2013 (2013): 1–17. http://dx.doi.org/10.1155/2013/195325.

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Charge storage nonvolatile memory (NVM) is one of the main driving forces in the evolution of IT handheld devices. Technology scaling of charge storage NVM has always been the strategy to achieve higher density NVM with lower cost per bit in order to meet the persistent consumer demand for larger storage space. However, conventional technology scaling of charge storage NVM has run into many critical reliability challenges related to fundamental device characteristics. Therefore, further technology scaling has to be supplemented with novel approaches in order to surmount these reliability issues to achieve desired reliability performance. This paper is focused on reviewing critical research findings on major reliability challenges and technical solutions to mitigate technology scaling challenges of charge storage NVM. Most of these technical solutions are still in research phase while a few of them are more mature and ready for production phase. Three of the mature technical solutions will be reviewed in detail, that is, tunnel oxide top/bottom nitridation, nanocrystal, and phase change memory (PCM). Key advantages and reported reliability challenges of these approaches are thoroughly reviewed in this paper. This paper will serve as a good reference to understand the future trend of innovative technical solutions to overcome the reliability challenges of charge storage NVM due to technology scaling.
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9

Wang, Shuai, Jing Pu, Daniel S. H. Chan, Byung Jin Cho y Kian Ping Loh. "Wide memory window in graphene oxide charge storage nodes". Applied Physics Letters 96, n.º 14 (5 de abril de 2010): 143109. http://dx.doi.org/10.1063/1.3383234.

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10

Lee, Gae-Hun, Jung-Min Lee, Yun Heub Song, Ji Chel Bea, Tetsu Tanaka y Mitsumasa Koyanagi. "Multilevel Charge Storage in a Multiple Alloy Nanodot Memory". Japanese Journal of Applied Physics 50, n.º 9R (1 de septiembre de 2011): 095001. http://dx.doi.org/10.7567/jjap.50.095001.

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11

Lee, Gae-Hun, Jung-Min Lee, Yun Heub Song, Ji Chel Bea, Tetsu Tanaka y Mitsumasa Koyanagi. "Multilevel Charge Storage in a Multiple Alloy Nanodot Memory". Japanese Journal of Applied Physics 50, n.º 9 (20 de septiembre de 2011): 095001. http://dx.doi.org/10.1143/jjap.50.095001.

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12

Fujiwara, Ichiro, Sigeru Kojima y Jun'etsu Seto. "High Density Charge Storage Memory with Scanning Probe Microscopy". Japanese Journal of Applied Physics 35, Part 1, No. 5A (15 de mayo de 1996): 2764–69. http://dx.doi.org/10.1143/jjap.35.2764.

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13

Cui, J. B., R. Sordan, M. Burghard y K. Kern. "Carbon nanotube memory devices of high charge storage stability". Applied Physics Letters 81, n.º 17 (21 de octubre de 2002): 3260–62. http://dx.doi.org/10.1063/1.1516633.

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14

Spassov, Dencho, Albena Paskaleva, Elżbieta Guziewicz, Wojciech Wozniak, Todor Stanchev, Tsvetan Ivanov, Joanna Wojewoda-Budka y Marta Janusz-Skuza. "Charge Storage and Reliability Characteristics of Nonvolatile Memory Capacitors with HfO2/Al2O3-Based Charge Trapping Layers". Materials 15, n.º 18 (9 de septiembre de 2022): 6285. http://dx.doi.org/10.3390/ma15186285.

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Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO2/Al2O3 nanolaminates and Al-doped HfO2, are used as the charge trapping layer, and SiO2 (of different thickness) or Al2O3 is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO2 tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O2 significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O2 annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO2, while electron traps are related to Al2O3. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM.
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15

Salaoru, Iulia y Shashi Paul. "Memory Effect of a Different Materials as Charge Storage Elements for Memory Applications". Advances in Science and Technology 77 (septiembre de 2012): 205–8. http://dx.doi.org/10.4028/www.scientific.net/ast.77.205.

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In recent years, the interest in the application of organic materials in electronic devices (light emitting diodes, field effect transistors, solar cells), has shown a rapid increase. Polymer memory devices (PDMs) is a very recent addition to the organic electronics. The polymer memory devices can be fabricated by depositing a blend (an admixture of organic polymer, small organic molecules and metal or semiconductor nanoparticles) between two metal electrodes. We demonstrate the memory effect in the device with simple structure based on blend of polymer with different materials like ionic compound (NaCl), ferroelectrical nano-particles (BaTiO3) and small organic molecules In 2007 Paul has proposed a model to explain memory effect a switching between two distinctive conductivity states when voltage is applied based on electrical dipole formation in the polymer matrix. Here, we investigate if our memory devices based on different types of materials are fitted with the proposed model.
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16

Yin, Changyong, Ziqi Zhao, Shiqi Zhang y Zexiang Gao. "Research on the operation state prediction of energy storage unit based on neural network". Journal of Physics: Conference Series 2558, n.º 1 (1 de agosto de 2023): 012035. http://dx.doi.org/10.1088/1742-6596/2558/1/012035.

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Abstract As a device that can conduct energy storage and release, the energy storage system can accelerate the utilization of new energy and enhance the operation stability of the grid. The main significance of the time series prediction is to analyze the future change trend of the data based on historical data. To more exactly predict the future change trend of the operating state parameters of the energy storage unit, the charge and discharge current data and operating voltage data of the energy storage unit are analyzed and studied. The long short-term memory is used to predict the operating voltage and charge and discharge current of the distributed energy storage unit.
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17

Kim, Eunkyeom, Kyoungmin Kim, Daeho Son, Jeongho Kim, Kyungsu Lee, Moonsup Han, Sunghwan Won, Junghyun Sok, Wan-Shick Hong y Kyoungwan Park. "Nonvolatile memory characteristics of metallic nanodots as charge-storage nodes". Microelectronic Engineering 85, n.º 12 (diciembre de 2008): 2366–69. http://dx.doi.org/10.1016/j.mee.2008.09.037.

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18

Yeh, P. H., L. J. Chen, P. T. Liu, D. Y. Wang y T. C. Chang. "Metal nanocrystals as charge storage nodes for nonvolatile memory devices". Electrochimica Acta 52, n.º 8 (febrero de 2007): 2920–26. http://dx.doi.org/10.1016/j.electacta.2006.09.006.

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19

Nakamura, Taichi. "Multilevel storage memory using serial—parallel–serial charge—coupled device". Electronics and Communications in Japan (Part II: Electronics) 72, n.º 2 (1989): 23–34. http://dx.doi.org/10.1002/ecjb.4420720204.

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20

Liu, Weihua, Fei Wu, Xiang Chen, Meng Zhang, Yu Wang, Xiangfeng Lu y Changsheng Xie. "Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory". ACM Transactions on Storage 18, n.º 2 (31 de mayo de 2022): 1–25. http://dx.doi.org/10.1145/3491230.

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Solid-state drive (SSD) gradually dominates in the high-performance storage scenarios. Three-dimension (3D) NAND flash memory owning high-storage capacity is becoming a mainstream storage component of SSD. However, the interferences of the new 3D charge-trap (CT) NAND flash are getting unprecedentedly complicated, yielding to many problems regarding reliability and performance. Alleviating these problems needs to understand the characteristics of 3D CT NAND flash memory deeply. To facilitate such understanding, in this article, we delve into characterizing the performance, reliability, and threshold voltage ( V th ) distribution of 3D CT NAND flash memory. We make a summary of these characteristics with multiple interferences and variations and give several new insights and a characterization methodology. Especially, we characterize the skewed ( V th ) distribution, ( V th ) shift laws, and the exclusive layer variation in 3D NAND flash memory. The characterization is the backbone of designing more reliable and efficient flash-based storage solutions.
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21

Lu, X. B. y J. Y. Dai. "Memory effects of carbon nanotubes as charge storage nodes for floating gate memory applications". Applied Physics Letters 88, n.º 11 (13 de marzo de 2006): 113104. http://dx.doi.org/10.1063/1.2179374.

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22

Liu, W. J., L. Chen, P. Zhou, Q. Q. Sun, H. L. Lu, S. J. Ding y David W. Zhang. "Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device". Journal of Nanomaterials 2016 (2016): 1–6. http://dx.doi.org/10.1155/2016/6751497.

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We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.
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23

Shih, Wen-Chieh, Chih-Hao Cheng, Joseph Ya-min Lee y Fu-Chien Chiu. "Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications". Advances in Materials Science and Engineering 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/548329.

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Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5as the charge storage layer and Y2O3as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6 V. Using a pulse voltage of 6 V, a threshold voltage shift of ~1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.
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24

Kim, Moon Kyung y Sandip Tiwari. "NON-VOLATILE HIGH SPEED & LOW POWER CHARGE TRAPPING DEVICES". International Journal of High Speed Electronics and Systems 17, n.º 01 (marzo de 2007): 147–52. http://dx.doi.org/10.1142/s0129156407004369.

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We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO 2/ SiO 2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO 2/ SiO 2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ~0.44 eV for the write process and ~0.47 eV for the erase process in SiO 2/ SiO 2 structural device which is somewhat more efficient than those of SONOS structure memory.
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25

Cui, Ziyang, Dongxu Xin, Taeyong Kim, Jiwon Choi, Jaewoong Cho y Junsin Yi. "Improvement of the Charge Retention of a Non-Volatile Memory by a Bandgap-Engineered Charge Trap Layer". ECS Journal of Solid State Science and Technology 10, n.º 12 (1 de diciembre de 2021): 125002. http://dx.doi.org/10.1149/2162-8777/ac3f1d.

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In recent years, research based on HfO2 as a charge trap memory has become increasingly popular. This material, with its advantages of moderate dielectric constant, good interface thermal stability and high charge trap density, is currently gaining in prominence in the next generation of nonvolatile memory devices. In this study, memory devices based on a-IGZO thin-film transistor (TFT) with HfO2/Al2O3/HfO2 charge trap layer (CTL) were fabricated using atomic layer deposition. The effect of the Al2O3 layer thickness (1, 2, and 3 nm) in the CTL on memory performance was studied. The results show that the device with a 2-nm Al2O3 layer in the CTL has a 2.47 V memory window for 12 V programming voltage. The use of the HfO2/Al2O3/HfO2 structure as a CTL lowered the concentration of electrons near the tunnel layer and the loss of trapped electrons. At room temperature, the memory window is expected to decrease by 0.61 V after 10 years. The large storage window (2.47 V) and good charge retention (75.6% in 10 years) of the device under low-voltage conditions are highly advantageous. The charge retention of the HfO2/Al2O3/HfO2 trap layer affords a feasible method for fabricating memory devices based on a-IGZO TFT.
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26

Yang, Yang, Liping Ma y Jianhua Wu. "Organic Thin-Film Memory". MRS Bulletin 29, n.º 11 (noviembre de 2004): 833–37. http://dx.doi.org/10.1557/mrs2004.237.

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AbstractRecently, organic nonvolatile memory devices have attracted considerable attention due to their low cost and high performance. This article reviews recent developments in organic nonvolatile memory and describes in detail an organic electrical bistable device (OBD) that has potential for applications. The OBD consists of a tri-layer of organics/metal nanoclusters/organics sandwiched between top and bottom electrodes. A sufficiently high applied bias causes the metal nanoparticle layer to become polarized, resulting in charge storage near the two metal/organic interfaces. This stored charge lowers the resistance of the device and leads to an electrical switching behavior. The ON and OFF states of an OBD differ in their conductivity by several orders of magnitude and show remarkable bistability—once either state is reached, the device tends to remain in that state for a prolonged period of time. More important, the conductivity states of an OBD can be precisely controlled by the application of a positive voltage pulse (to write) or a negative voltage pulse (to erase). Device performance tests show that the OBD is a promising candidate for high-density, low-cost electrically addressable data storage applications.
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27

Chou, Ying-Hsuan, Hsuan-Chun Chang, Cheng-Liang Liu y Wen-Chang Chen. "Polymeric charge storage electrets for non-volatile organic field effect transistor memory devices". Polymer Chemistry 6, n.º 3 (2015): 341–52. http://dx.doi.org/10.1039/c4py01213e.

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28

Zhou, H. C., Y. X. Zhou, Yu Qiu y Jun Zhu. "Enhanced charge storage capability of (Bi2O3)0.4(ZrO2)0.6 charge trapping layer in nanocrystal memory devices". Functional Materials Letters 12, n.º 04 (agosto de 2019): 1950046. http://dx.doi.org/10.1142/s1793604719500462.

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A structure of p-Si/Al2O3/(Bi2O3)[Formula: see text](ZrO2)[Formula: see text](BZO)/Al2O3/Pt has been fabricated as Nanocrystal Charge Trapping Memory (NCTM), where the double nanocrystals (NCs) of Bi2O3 and ZrO2 generated in BZO charge trapping layer (CTL) through rapid temperature annealing (RTA). A large memory window (MW) of [Formula: see text]8.6[Formula: see text]V and high defect traps of [Formula: see text][Formula: see text]cm[Formula: see text] were obtained at a low sweeping voltages of [Formula: see text]8[Formula: see text]V after 800∘C for 90[Formula: see text]s in O2 ambient. The devices of different RTA conditions were investigated to analyze the process of NCs traps formation by the X-ray diffraction and X-ray photoelectron spectroscopy. Excellent retention characteristics of the room temperature were observed after 104[Formula: see text]s because of the deep defect traps and high quantum wells between CTL and tunneling oxide layer (TOL).
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29

Kwon, Wookhyun, In Jun Park y Changhwan Shin. "Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage". JSTS:Journal of Semiconductor Technology and Science 15, n.º 2 (30 de abril de 2015): 286–91. http://dx.doi.org/10.5573/jsts.2015.15.2.286.

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30

El-Atab, N. y A. Nayfeh. "Ultra-Small ZnO Nanoparticles for Charge Storage in MOS-Memory Devices". ECS Transactions 72, n.º 5 (19 de mayo de 2016): 73–79. http://dx.doi.org/10.1149/07205.0073ecst.

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31

Ganguly, Udayan, Edwin C. Kan y Yuegang Zhang. "Carbon nanotube-based nonvolatile memory with charge storage in metal nanocrystals". Applied Physics Letters 87, n.º 4 (25 de julio de 2005): 043108. http://dx.doi.org/10.1063/1.1999014.

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32

Alba-Martin, Maria, Timothy Firmager, Joseph Atherton, Mark C. Rosamond, Daniel Ashall, Amal Al Ghaferi, Ahmad Ayesh et al. "Improved memory behaviour of single-walled carbon nanotubes charge storage nodes". Journal of Physics D: Applied Physics 45, n.º 29 (2 de julio de 2012): 295401. http://dx.doi.org/10.1088/0022-3727/45/29/295401.

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33

Ray, Sounak K., Debashis Panda y Rakesh Aluguri. "Enhanced charge storage characteristics of nickel nanocrystals embedded flash memory structures". Journal of Experimental Nanoscience 8, n.º 3 (abril de 2013): 389–95. http://dx.doi.org/10.1080/17458080.2012.708440.

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34

Zheng, Chaoyue, Tong Tong, Yueming Hu, Yuming Gu, Huarui Wu, Dequn Wu, Hong Meng et al. "Charge-Storage Aromatic Amino Compounds for Nonvolatile Organic Transistor Memory Devices". Small 14, n.º 25 (27 de mayo de 2018): 1800756. http://dx.doi.org/10.1002/smll.201800756.

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35

Liu, L., J. P. Xu, F. Ji, J. X. Chen y P. T. Lai. "Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications". Applied Physics Letters 101, n.º 3 (16 de julio de 2012): 033501. http://dx.doi.org/10.1063/1.4737158.

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36

Yang, Kun, Hongxia Liu, Shulong Wang, Wenlong Yu y Tao Han. "Comprehensive Performance Quasi-Non-Volatile Memory Compatible with Large-Scale Preparation by Chemical Vapor Deposition". Nanomaterials 10, n.º 8 (27 de julio de 2020): 1471. http://dx.doi.org/10.3390/nano10081471.

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Two-dimensional materials with atomic thickness have become candidates for wearable electronic devices in the future. Graphene and transition metal sulfides have received extensive attention in logic computing and sensing applications due to their lower power dissipation, so that their processes have been relatively mature for large-scale preparation. However, there are a few applications of two-dimensional materials in storage, which is not in line with the development trend of integration of storage and computing. Here, a charge storage quasi-non-volatile memory with a lanthanum incorporation high-k dielectric for next-generation memory devices is proposed. Thanks to the excellent electron capture capability of LaAlO3, the MoS2 memory exhibits a very comprehensive information storage capability, including robust endurance and ultra-fast write speed of 1 ms approximately. It is worth mentioning that it exhibits a long-term stable charge storage capacity (refresh time is about 1000 s), which is 105 times that of the dynamic random access memory (refresh time is on a milliseconds timescale) so that the unnecessary power dissipation greatly reduces caused by frequent refresh. In addition, its simple manufacturing process makes it compatible with various current two-dimensional electronic devices, which will greatly promote the integration of two-dimensional electronic computing.
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37

Li, Chao, Bo Lei, Wendy Fan, Daihua Zhang, M. Meyyappan y Chongwu Zhou. "Molecular Memory Based on Nanowire–Molecular Wire Heterostructures". Journal of Nanoscience and Nanotechnology 7, n.º 1 (1 de enero de 2007): 138–50. http://dx.doi.org/10.1166/jnn.2007.18011.

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This article reviews the recent research of molecular memory based on self-assembled nanowire–molecular wire heterostructures. These devices exploit a novel concept of using redox-active molecules as charge storage flash nodes for nanowire transistors, and thus boast many advantages such as room-temperature processing and nanoscale device area. Various key elements of this technology will be reviewed, including the synthesis of the nanowires and molecular wires, and fabrication and characterization of the molecular memory devices. In particular, multilevel memory has been demonstrated using In2O3 nanowires with self-assembled Fe-bis(terpyridine) molecules, which serve to multiple the charge storage density without increasing the device size. Furthermore, in-depth studies on memory devices made with different molecules or with different functionalization techniques will be reviewed and analyzed. These devices represent a conceptual breakthrough in molecular memory and may work as building blocks for future beyond-CMOS nanoelectronic circuits.
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38

Zhang, Guoxian, Yu-Jung Lee, Prabhat Gautam, Chia-Chi Lin, Cheng-Liang Liu y Julian M. W. Chan. "Pentafluorosulfanylated polymers as electrets in nonvolatile organic field-effect transistor memory devices". Journal of Materials Chemistry C 7, n.º 26 (2019): 7865–71. http://dx.doi.org/10.1039/c9tc00756c.

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39

Islam, Sk Masiul y P. Banerji. "Size effect of InAs quantum dots grown by metal organic chemical vapor deposition technique in storing electrical charges for memory applications". RSC Advances 5, n.º 9 (2015): 6906–11. http://dx.doi.org/10.1039/c4ra13317j.

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40

LU, CHIH-YUAN. "NONVOLATILE MEMORY TECHNOLOGY: A DRIVER TO FUTURE NANOELECTRONICS". SPIN 02, n.º 01 (marzo de 2012): 1230001. http://dx.doi.org/10.1142/s2010324712300010.

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Flash memory has served as an important technology driver due to its many new applications. Despite the fact that NAND flash has out run lithography and other scaling barriers and thus is facing steep challenges, several innovative solutions are being developed to carry its momentum, and it continues to serve as a technology driver in the nanoelectronics era. New devices that are not based on charge storage, on the other hand, are promising to further boost system performance by offering low-power, high-density, and fast latency storage. These new developments should provide the next generation memory and storage solutions that will elevate system performance to a new level.
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41

Jin, Risheng, Keli Shi, Beibei Qiu y Shihua Huang. "Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate". Nanotechnology 33, n.º 2 (22 de octubre de 2021): 025201. http://dx.doi.org/10.1088/1361-6528/ac2dc5.

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Abstract Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼109), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits.
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42

James, David D., Akhtar Bayat, Scott R. Smith, Jean-Christophe Lacroix y Richard L. McCreery. "Nanometric building blocks for robust multifunctional molecular junctions". Nanoscale Horizons 3, n.º 1 (2018): 45–52. http://dx.doi.org/10.1039/c7nh00109f.

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43

Lo, Chen-Tsyr, Yu Watanabe, Hiroshi Oya, Kazuhiro Nakabayashi, Hideharu Mori y Wen-Chang Chen. "Non-volatile transistor memory devices using charge storage cross-linked core–shell nanoparticles". Chemical Communications 52, n.º 45 (2016): 7269–72. http://dx.doi.org/10.1039/c6cc02750d.

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Solution processable cross-linked nanoparticles with a cross-linked conjugated polythiophene core and a hydrophilic shell are firstly explored as charge storage materials for high performance transistor-type memory devices.
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44

Kim, Jaemin, Donghee Son, Mincheol Lee, Changyeong Song, Jun-Kyul Song, Ja Hoon Koo, Dong Jun Lee et al. "A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement". Science Advances 2, n.º 1 (enero de 2016): e1501101. http://dx.doi.org/10.1126/sciadv.1501101.

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Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.
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45

Wang, Jer-Chyi, Chih-Ting Lin y Chi-Feng Chang. "Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory". Current Applied Physics 14, n.º 3 (marzo de 2014): 232–36. http://dx.doi.org/10.1016/j.cap.2013.11.019.

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46

Novak, Steven, Bongmook Lee, Xiangyu Yang y Veena Misra. "Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications". Journal of The Electrochemical Society 157, n.º 6 (2010): H589. http://dx.doi.org/10.1149/1.3365031.

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47

Miura, Atsushi, Yukiharu Uraoka, Takashi Fuyuki, Shigeo Yoshii y Ichiro Yamashita. "Floating nanodot gate memory fabrication with biomineralized nanodot as charge storage node". Journal of Applied Physics 103, n.º 7 (abril de 2008): 074503. http://dx.doi.org/10.1063/1.2888357.

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48

Lin, Chao-Cheng, Ting-Chang Chang, Chun-Hao Tu, Wei-Ren Chen, Chih-Wei Hu, Simon M. Sze, Tseung-Yuen Tseng, Sheng-Chi Chen y Jian-Yang Lin. "Charge Storage Characteristics of Mo Nanocrystal Memory Influenced by Ammonia Plasma Treatment". Journal of The Electrochemical Society 156, n.º 9 (2009): H716. http://dx.doi.org/10.1149/1.3155446.

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49

Liu, L., J. P. Xu, F. Ji, X. D. Huang y P. T. Lai. "A Novel MONOS Memory With High-$\kappa$ HfLaON as Charge-Storage Layer". IEEE Transactions on Device and Materials Reliability 11, n.º 2 (junio de 2011): 244–47. http://dx.doi.org/10.1109/tdmr.2011.2117428.

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50

Sargentis, Ch, K. Giannakopoulos, A. Travlos, P. Normand y D. Tsamakis. "Study of charge storage characteristics of memory devices embedded with metallic nanoparticles". Superlattices and Microstructures 44, n.º 4-5 (octubre de 2008): 483–88. http://dx.doi.org/10.1016/j.spmi.2008.03.003.

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