Bibliografías temáticas / Cache codé

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Literatura académica sobre el tema "Cache codé"

Autor: Grafiati
Publicado: 25 de mayo de 2024
Última modificación: 31 de julio de 2025

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Artículos de revistas sobre el tema "Cache codé"

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Ding, Wei, Yuanrui Zhang, Mahmut Kandemir, and Seung Woo Son. "Compiler-Directed File Layout Optimization for Hierarchical Storage Systems." Scientific Programming 21, no. 3-4 (2013): 65–78. http://dx.doi.org/10.1155/2013/167581.

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File layout of array data is a critical factor that effects the behavior of storage caches, and has so far taken not much attention in the context of hierarchical storage systems. The main contribution of this paper is a compiler-driven file layout optimization scheme for hierarchical storage caches. This approach, fully automated within an optimizing compiler, analyzes a multi-threaded application code and determines a file layout for each disk-resident array referenced by the code, such that the performance of the target storage cache hierarchy is maximized. We tested our approach using 16 I
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Calciu, Irina, M. Talha Imran, Ivan Puddu, et al. "Using Local Cache Coherence for Disaggregated Memory Systems." ACM SIGOPS Operating Systems Review 57, no. 1 (2023): 21–28. http://dx.doi.org/10.1145/3606557.3606561.

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Disaggregated memory provides many cost savings and resource provisioning benefits for current datacenters, but software systems enabling disaggregated memory access result in high performance penalties. These systems require intrusive code changes to port applications for disaggregated memory or employ slow virtual memory mechanisms to avoid code changes. Such mechanisms result in high overhead page faults to access remote data and high dirty data amplification when tracking changes to cached data at page-granularity. In this paper, we propose a fundamentally new approach for disaggregated me
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Pan, Qinglin, Ji Qi, Jiatai He, Heng Zhang, Jiageng Yu, and Yanjun Wu. "Beaver: A High-Performance and Crash-Consistent File System Cache via PM-DRAM Collaborative Memory Tiering." Proceedings of the ACM on Measurement and Analysis of Computing Systems 8, no. 3 (2024): 1–24. https://doi.org/10.1145/3700414.

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The in-memory cache layer is crucial in building a file system. Crash-consistency is highly desirable for applications running on the file system, ensuring that data is written in an all-or-none fashion during unexpected system failures or crashes. However, existing works fail to achieve both high read and write performance in constructing a crash-consistent cache layer. In this paper, we propose Beaver, a new in-memory file system cache that achieves both crash-consistency and high read/write performance. Beaver exploits a read/write distinguishable memory hierarchy involving both PM and DRAM
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Pan, Qinglin, Ji Qi, Jiatai He, Heng Zhang, Jiageng Yu, and Yanjun Wu. "Beaver: A High-Performance and Crash-Consistent File System Cache via PM-DRAM Collaborative Memory Tiering." ACM SIGMETRICS Performance Evaluation Review 53, no. 1 (2025): 70–72. https://doi.org/10.1145/3744970.3727273.

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The in-memory cache layer is crucial in building a file system. Crash-consistency is highly desirable for applications running on the file system, ensuring that data is written in an all-or-none fashion during unexpected system failures or crashes. However, existing works fail to achieve both high read and write performance in constructing a crash-consistent cache layer. In this paper, we propose Beaver, a new in-memory file system cache that achieves both crash-consistency and high read/write performance. Beaver exploits a read/write distinguishable memory hierarchy involving both PM and DRAM
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Charrier, Dominic E., Benjamin Hazelwood, Ekaterina Tutlyaeva, et al. "Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver." International Journal of High Performance Computing Applications 33, no. 5 (2019): 973–86. http://dx.doi.org/10.1177/1094342019842645.

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We study the performance behaviour of a seismic simulation using the ExaHyPE engine with a specific focus on memory characteristics and energy needs. ExaHyPE combines dynamically adaptive mesh refinement (AMR) with ADER-DG. It is parallelized using tasks, and it is cache efficient. AMR plus ADER-DG yields a task graph which is highly dynamic in nature and comprises both arithmetically expensive tasks and tasks which challenge the memory’s latency. The expensive tasks and thus the whole code benefit from AVX vectorization, although we suffer from memory access bursts. A frequency reduction of t
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Moon, S. M. "Increasing cache bandwidth using multiport caches for exploiting ILP in non-numerical code." IEE Proceedings - Computers and Digital Techniques 144, no. 5 (1997): 295. http://dx.doi.org/10.1049/ip-cdt:19971283.

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Mittal, Shaily, and Nitin. "Memory Map: A Multiprocessor Cache Simulator." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/365091.

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Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an opti
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Ma, Ruhui, Haibing Guan, Erzhou Zhu, Yongqiang Gao, and Alei Liang. "Code cache management based on working set in dynamic binary translator." Computer Science and Information Systems 8, no. 3 (2011): 653–71. http://dx.doi.org/10.2298/csis100327022m.

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Software code cache employed to store translated or optimized codes, amortizes the overhead of dynamic binary translation via reusing of stored-altered copies of original program instructions. Though many conventional code cache managements, such as Flush, Least-Recently Used (LRU), have been applied on some classic dynamic binary translators, actually they are so unsophisticated yet unadaptable that it not only brings additional unnecessary overhead, but also wastes much cache space, since there exist several noticeable features in software code cache, unlike pages in memory. Consequently, th
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Das, Abhishek, and Nur A. Touba. "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote." Electronics 9, no. 5 (2020): 709. http://dx.doi.org/10.3390/electronics9050709.

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Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on
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Simecek, Ivan, and Pavel Tvrdík. "A new code transformation technique for nested loops." Computer Science and Information Systems 11, no. 4 (2014): 1381–416. http://dx.doi.org/10.2298/csis131126075s.

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For good performance of every computer program, good cache utilization is crucial. In numerical linear algebra libraries, good cache utilization is achieved by explicit loop restructuring (mainly loop blocking), but it requires a complicated memory pattern behavior analysis. In this paper, we describe a new source code transformation called dynamic loop reversal that can increase temporal and spatial locality. We also describe a formal method for predicting cache behavior and evaluate results of the model accuracy by the measurements on a cache monitor. The comparisons of the numbers of measur
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Tesis sobre el tema "Cache codé"

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Parrinello, Emanuele. "Fundamental Limits of Shared-Cache Networks." Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS491.

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Dans le contexte des réseaux de diffusion de contenu, les avantages puissants de la combinaison du cache et de la multidiffusion codée ont été démontrés pour les réseaux où chaque utilisateur est équipé de son propre cache isolé. Cette thèse vise à fournir les principes fondamentaux des réseaux à cache partagé où la communication avec les utilisateurs est assistée par un petit ensemble de caches, chacun d'entre eux servant un nombre arbitraire d'utilisateurs. Notre modèle de cache partagé, non seulement capture les réseaux cellulaires sans fil hétérogènes où les petites stations de base assist
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Malik, Adeel. "Stochastic Coded Caching Networks : a Study of Cache-Load Imbalance and Random User Activity." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS045.pdf.

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Dans cette thèse, nous élevons la mise en cache codée de son cadre purement théorique de l'information à un cadre stochastique où la stochasticité des réseaux provient de l'hétérogénéité des comportements de demande des utilisateurs. Nos résultats soulignent que la stochasticité des réseaux assistés par cache peut conduire à la disparition des gains de la mise en cache codée. Nous déterminons l'étendue exacte du goulot d'étranglement du déséquilibre de la charge du cache codé dans les réseaux stochastiques, ce qui n'a jamais été exploré auparavant. Notre travail fournit des techniques pour att
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Brunero, Federico. "Unearthing the Impact of Structure in Data and in Topology for Caching and Computing Networks." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS368.pdf.

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La mise en cache s'est avérée être un excellent moyen de réduire la charge de trafic dans les réseaux de données. Une étude de la mise en cache en théorie de l'information, connue sous le nom de mise en cache codée, a représenté une percée clé dans la compréhension de la façon dont la mémoire peut être efficacement transformée en débit de données. La mise en cache codée a également révélé le lien profond entre la mise en cache et les réseaux informatiques, qui présentent le même besoin de solutions algorithmiques novatrices pour réduire la charge de trafic. Malgré la vaste littérature, il rest
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Beg, Azam Muhammad. "Improving instruction fetch rate with code pattern cache for superscalar architecture." Diss., Mississippi State : Mississippi State University, 2005. http://library.msstate.edu/etd/show.asp?etd=etd-06202005-103032.

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Palki, Anand B. "CACHE OPTIMIZATION AND PERFORMANCE EVALUATION OF A STRUCTURED CFD CODE - GHOST." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/363.

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This research focuses on evaluating and enhancing the performance of an in-house, structured, 2D CFD code - GHOST, on modern commodity clusters. The basic philosophy of this work is to optimize the cache performance of the code by splitting up the grid into smaller blocks and carrying out the required calculations on these smaller blocks. This in turn leads to enhanced code performance on commodity clusters. Accordingly, this work presents a discussion along with a detailed description of two techniques: external and internal blocking, for data access optimization. These techniques have been t
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Gupta, Saurabh. "PERFORMANCE EVALUATION AND OPTIMIZATION OF THE UNSTRUCTURED CFD CODE UNCLE." UKnowledge, 2006. http://uknowledge.uky.edu/gradschool_theses/360.

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Numerous advancements made in the field of computational sciences have made CFD a viable solution to the modern day fluid dynamics problems. Progress in computer performance allows us to solve a complex flow field in practical CPU time. Commodity clusters are also gaining popularity as computational research platform for various CFD communities. This research focuses on evaluating and enhancing the performance of an in-house, unstructured, 3D CFD code on modern commodity clusters. The fundamental idea is to tune the codes to optimize the cache behavior of the node on commodity clusters to achi
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Zhao, Hui. "High performance cache-aided downlink systems : novel algorithms and analysis." Electronic Thesis or Diss., Sorbonne université, 2022. http://www.theses.fr/2022SORUS366.

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La thèse aborde d'abord le pire goulot d'étranglement de la mise en cache codée sans fil, qui est connue pour diminuer considérablement les gains de multidiffusion assistée par cache. Nous présentons un nouveau schéma, appelé mise en cache codée agrégée, qui peut récupérer entièrement les gains de mise en cache codée en capitalisant sur les informations partagées apportées par la contrainte de taille de fichier effectivement inévitable. La thèse passe ensuite à des scénarios avec des émetteurs avec des réseaux multi-antennes. En particulier, nous considérons maintenant le scénario multi-utilis
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Seyr, Luciana. "Manejo do solo e ensacamento do cacho em pomar de bananeira 'Nanicão'." Universidade Estadual de Londrina. Centro de Ciências Agrárias. Programa de Pós-Graduação em Agronomia, 2011. http://www.bibliotecadigital.uel.br/document/?code=vtls000166653.

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O Brasil é o quarto produtor mundial de banana, com uma produção anual de 6,99 milhões de toneladas. É uma fruta de grande importância econômica e social, visto que é cultivada de Norte a Sul do país, garantindo emprego, renda e alimento para milhões de brasileiros durante o ano inteiro. No Paraná é a terceira fruta mais produzida no estado, com área de 9.900 ha. A maior parte da produção brasileira é destinada ao mercado interno, visto que é a segunda fruta mais consumida no país, e também devido à baixa qualidade da maior parte do produto. Essa baixa qualidade é o reflexo da falta de tecnolo
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Kristipati, Pavan K. "Performance optimization of a structured CFD code GHOST on commodity cluster architectures /." Lexington, Ky. : [University of Kentucky Libraries], 2008. http://hdl.handle.net/10225/976.

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Thesis (M.S.)--University of Kentucky, 2008.<br>Title from document title page (viewed on February 3, 2009). Document formatted into pages; contains: xi, 144 p. : ill. (some col.). Includes abstract and vita. Includes bibliographical references (p. 139-143).
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Dias, Wanderson Roger Azevedo. "Arquitetura pdccm em hardware para compressão/descompressão de instruções em sistemas embarcados." Universidade Federal do Amazonas, 2009. http://tede.ufam.edu.br/handle/tede/2950.

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Made available in DSpace on 2015-04-11T14:03:12Z (GMT). No. of bitstreams: 1 DISSERTACAO - WANDERSON ROGER.pdf: 2032449 bytes, checksum: f75ada58e34bb5da29e9716bc5899cab (MD5) Previous issue date: 2009-04-30<br>Fundação de Amparo à Pesquisa do Estado do Amazonas<br>In the development of the design of embedded systems several factors must be led in account, such as: physical size, weight, mobility, energy consumption, memory, cooling, security requirements, trustiness and everything ally to a reduced cost and of easy utilization. But, on the measure that the systems become more heterogene
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Libros sobre el tema "Cache codé"

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Bella, Arman, ed. Le code caché de votre destin. J'ai lu, 2010.

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Yu-fang, Chʻen, and United States. National Aeronautics and Space Administration., eds. The Effect of code expanding optimizations on instruction cache design. Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, College of Engineering, University of Illinois at Urbana-Champaign, 1991.

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Helen Foresman Spencer Museum of Art, ed. Secrets of the sacred: Empowering Buddhist images in clear, in code, and in cache. Spencer Museum of Art in association with the University of Washington Press, 2011.

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The cache code. Knowonder! Publishing, 2016.

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Takenaka, Norio. TB3186 - How to Achieve Deterministic Code Performance Using a Cortex M Cache Controller (KC). Microchip Technology Incorporated, 2018.

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James, Hillman. Le Code caché de votre destin : Prendre en main son existence. J'ai lu, 2002.

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Aiyappa, Rekha. How to Achieve Deterministic Code Performance Using a Cortex(tm)-M Cache Controller Tech Brief. Microchip Technology Incorporated, 2018.

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Le code caché de Botticelli: Minerve et le Centaure, Les deux testaments. Pépin, 2011.

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Hillman, James. Le code caché de votre destin : Prendre en main son existence en élevant sa conscience de soi. Robert Laffont, 1999.

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Walker, Elsie. Hearing Haneke. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190495909.001.0001.

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Haneke’s films are sonically charged experiences of disturbance, desperation, grief, and many forms of violence. They are unsoftened by music, punctuated by accosting noises, shaped by painful silences, and defined by aggressive dialogue. Haneke is among the most celebrated of living auteurs: he is two-time receipt of the Palme d’Or at Cannes Film Festival (for The White Ribbon [2009] and Amour [2012]), and Academy Award winner of Best Foreign Language Film (for Amour), among numerous other awards. The radical confrontationality of his cinema makes him a most controversial, as well as revered,
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Capítulos de libros sobre el tema "Cache codé"

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Sklar, David. "Accelerating with Code Caches." In Essential PHP Tools: Modules, Extensions, and Accelerators. Apress, 2004. http://dx.doi.org/10.1007/978-1-4302-0714-6_13.

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Simner, Ben, Shaked Flur, Christopher Pulte, et al. "ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures." In Programming Languages and Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-44914-8_23.

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AbstractComputing relies on architecture specifications to decouple hardware and software development. Historically these have been prose documents, with all the problems that entails, but research over the last ten years has developed rigorous and executable-as-test-oracle specifications of mainstream architecture instruction sets and “user-mode” concurrency, clarifying architectures and bringing them into the scope of programming-language semantics and verification. However, the system semantics, of instruction-fetch and cache maintenance, exceptions and interrupts, and address translation,
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Lin, Chun-Chieh, and Chuen-Liang Chen. "Cache Sensitive Code Arrangement for Virtual Machine." In Transactions on High-Performance Embedded Architectures and Compilers III. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19448-1_2.

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Genkin, Daniel, Lev Pachmanov, Eran Tromer, and Yuval Yarom. "Drive-By Key-Extraction Cache Attacks from Portable Code." In Applied Cryptography and Network Security. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-93387-0_5.

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Arslan, Sanem, Haluk Rahmi Topcuoglu, Mahmut Taylan Kandemir, and Oguz Tosun. "Protecting Code Regions on Asymmetrically Reliable Caches." In Architecture of Computing Systems – ARCS 2016. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30695-7_28.

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Guha, Apala, Kim Hazelwood, and Mary Lou Soffa. "Reducing Exit Stub Memory Consumption in Code Caches." In High Performance Embedded Architectures and Compilers. Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-69338-3_7.

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Palkowski, Marek, and Wlodzimierz Bielecki. "Parallel Tiled Cache and Energy Efficient Code for Zuker’s RNA Folding." In Parallel Processing and Applied Mathematics. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-43222-5_3.

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Palkowski, Marek, Wlodzimierz Bielecki, and Mateusz Gruzewski. "Automatic Generation of Parallel Cache-Efficient Code Implementing Zuker’s RNA Folding." In Artificial Intelligence and Soft Computing. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-61401-0_60.

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Nikolopoulos, Dimitrios S. "Code and Data Transformations for Improving Shared Cache Performance on SMT Processors." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39707-6_5.

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Hatchikian-Houdot, Jean-Loup, Pierre Wilke, Frédéric Besson, and Guillaume Hiet. "Formal Hardware/Software Models for Cache Locking Enabling Fast and Secure Code." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-70896-1_8.

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Actas de conferencias sobre el tema "Cache codé"

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Roby, Brian, John Barber, and Ken Karika. "V-22 and the Future of Carrier Onboard Delivery (COD): Improving the Way the Navy Re-Supplies Its Carriers and Maritime Forces." In Vertical Flight Society 70th Annual Forum & Technology Display. The Vertical Flight Society, 2014. http://dx.doi.org/10.4050/f-0070-2014-9602.

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The Carrier onboard delivery (COD) mission involves the use of aircraft to ferry personnel, mail, supplies, VIPs, and high-priority cargo, such as replacement parts from shore bases to aircraft carriers. Several types of aircraft, including helicopters, have been used by navies in the COD role. Helicopters in the USN fleet have also played a major role in re-supply with the Vertical Onboard Delivery, or VOD mission element. The COD/VOD combined mission has heretofore amounted to a maritime hub-and-spoke system whereby the COD aircraft deploy the major re-supply cache to a carrier (hub), follow
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Baiocchi, José A., and Bruce R. Childers. "Heterogeneous code cache." In the 46th Annual Design Automation Conference. ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630103.

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Musoll, Enric, and Mario Nemirovsky. "A study on the performance of two-level exclusive caching." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1999. http://dx.doi.org/10.5753/sbac-pad.1999.19771.

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This work presents a study on the performance of a level-two cache configured as a victim storage for the evicted lines of the level-one cache. This two-level cache configuration, known as exclusive caching, is evaluated for a wide range of level-one and level-two sizes and associalivily degrees, and the miss ratios of both levels are compared to those of the two-level inclusive caching. Although the two-level exclusive strategy has lower miss ratios than the inclusive one by increasing the effective associativity and capacity, the replacement policy of the exclusive caching organization force
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Aftab, Fakhra, and Muhammad Ali Ismail. "Web Ontology based multi-level CACHE Simulator." In 2017 International Conference on Communication, Computing and Digital Systems (C-CODE). IEEE, 2017. http://dx.doi.org/10.1109/c-code.2017.7918928.

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Kim, Junghoon, Inhyuk Kim, and Young Ik Eom. "Code-based cache partitioning for improving hardware cache performance." In the 6th International Conference. ACM Press, 2012. http://dx.doi.org/10.1145/2184751.2184803.

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Bin Bao and Chen Ding. "Defensive loop tiling for shared cache." In 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO). IEEE, 2013. http://dx.doi.org/10.1109/cgo.2013.6495008.

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Roy, Probir, Shuaiwen Leon Song, Sriram Krishnamoorthy, and Xu Liu. "Lightweight detection of cache conflicts." In CGO '18: 16th Annual IEEE/ACM International Symposium on Code Generation and Optimization. ACM, 2018. http://dx.doi.org/10.1145/3168819.

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Moreira, Francis Birck, Eduardo Henrique Molina da Cruz, Marco Antonio Zanata Alves, and Philippe Olivier Alexandre Navaux. "Scratchpad Memories for Parallel Applications in Multi-core Architectures." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2011. http://dx.doi.org/10.5753/wscad.2011.17263.

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Scratchpad memories are largely used in embedded processors due to their reduced energy consumption and area compared to traditional cache memories. In multi-core architectures, these memories are an interesting solution for the storage of shared data and data which is used intensively. However, these memories present some challenges, such as the need for manual choice of the content. Furthermore, different sizes of scratchpad memories result in the need to modify the source code of the application. In this article, we propose the use of a scratchpad memory in a multi-core architecture which a
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Xu, Chengfa, Chengcheng Li, and Bin Tang. "DSP code optimization based on cache." In 2012 International Conference on Graphic and Image Processing, edited by Zeng Zhu. SPIE, 2013. http://dx.doi.org/10.1117/12.2010893.

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Tesone, Pablo, Guillermo Polito, and Stéphane Ducasse. "Profiling code cache behaviour via events." In MPLR '21: 18th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes. ACM, 2021. http://dx.doi.org/10.1145/3475738.3480720.

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