Artículos de revistas sobre el tema "Buffering Architecture"
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Mulder, H. y M. J. Flynn. "Processor architecture and data buffering". IEEE Transactions on Computers 41, n.º 10 (1992): 1211–22. http://dx.doi.org/10.1109/12.166600.
Texto completoTaleb, Tarik, Nei Kato y Yoshiaki Nemoto. "Neighbors-buffering-based video-on-demand architecture". Signal Processing: Image Communication 18, n.º 7 (agosto de 2003): 515–26. http://dx.doi.org/10.1016/s0923-5965(03)00039-0.
Texto completoMauceri, Daniela, Anna M. Hagenston, Kathrin Schramm, Ursula Weiss y Hilmar Bading. "Nuclear Calcium Buffering Capacity Shapes Neuronal Architecture". Journal of Biological Chemistry 290, n.º 38 (31 de julio de 2015): 23039–49. http://dx.doi.org/10.1074/jbc.m115.654962.
Texto completoGuild, K. M. y M. J. O'Mahony. "Routing and buffering architecture in all-optical switching node". Electronics Letters 35, n.º 2 (1999): 161. http://dx.doi.org/10.1049/el:19990129.
Texto completoWang, Ru-yan, Jie Zhang, Fang Guo y Ke-ping Long. "An effective buffering architecture for optical packet switching networks". Photonic Network Communications 16, n.º 3 (27 de junio de 2008): 239–43. http://dx.doi.org/10.1007/s11107-008-0135-0.
Texto completoTan, Xu, Xiao-Wei Shen, Xiao-Chun Ye, Da Wang, Dong-Rui Fan, Lunkai Zhang, Wen-Ming Li, Zhi-Min Zhang y Zhi-Min Tang. "A Non-Stop Double Buffering Mechanism for Dataflow Architecture". Journal of Computer Science and Technology 33, n.º 1 (enero de 2018): 145–57. http://dx.doi.org/10.1007/s11390-017-1747-6.
Texto completoKim, Joongheon y Aziz Mohaisen. "Distributed and reliable decision-making for cloud-enabled mobile service platforms". International Journal of Distributed Sensor Networks 13, n.º 8 (agosto de 2017): 155014771772650. http://dx.doi.org/10.1177/1550147717726509.
Texto completoLeff, A., J. L. Wolf y P. S. Yu. "Efficient LRU-based buffering in a LAN remote caching architecture". IEEE Transactions on Parallel and Distributed Systems 7, n.º 2 (1996): 191–206. http://dx.doi.org/10.1109/71.485508.
Texto completoBrustoloni, José Carlos y Peter Steenkiste. "Effects of buffering semantics on I/O performance". ACM SIGOPS Operating Systems Review 30, SI (28 de octubre de 1996): 277–91. http://dx.doi.org/10.1145/248155.238787.
Texto completoManiotis, P., D. Fitsios, G. T. Kanellos y N. Pleros. "Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture". Journal of Lightwave Technology 31, n.º 24 (diciembre de 2013): 4175–91. http://dx.doi.org/10.1109/jlt.2013.2290741.
Texto completoDe Rossi, Giacomo y Riccardo Muradore. "A Bilateral Teleoperation Architecture using Smith Predictor and Adaptive Network Buffering". IFAC-PapersOnLine 50, n.º 1 (julio de 2017): 11421–26. http://dx.doi.org/10.1016/j.ifacol.2017.08.1806.
Texto completoChen, Kai-Sheng y Wien Hong. "Multi-Level Buffering Services Based on Optical Packet Encoding of Composite Maximal-Length Sequences in a GMPLS Network". Applied Sciences 10, n.º 3 (21 de enero de 2020): 730. http://dx.doi.org/10.3390/app10030730.
Texto completoYang, Shuna y Norvald Stol. "A novel delay line buffering architecture for asynchronous optical packet switched networks". International Journal of Information, Communication Technology and Applications 1, n.º 1 (9 de marzo de 2015): 69–82. http://dx.doi.org/10.17972/ajicta20151112.
Texto completoLi, Lin, Jitender S. Deogun y Stephen D. Scott. "Performance analysis of optical packet switches with a hybrid buffering architecture [Invited]". Journal of Optical Networking 3, n.º 6 (2004): 433. http://dx.doi.org/10.1364/jon.3.000433.
Texto completoReza, Ahmed Galib y Hyotaek Lim. "Hybrid buffering architecture for packet contention resolution of an optical packet switch". Optik 122, n.º 7 (abril de 2011): 591–93. http://dx.doi.org/10.1016/j.ijleo.2010.04.017.
Texto completoKong, B. Y. "Multi‐touch detector architecture based on efficient buffering of intensities and labels". Electronics Letters 56, n.º 14 (julio de 2020): 699–701. http://dx.doi.org/10.1049/el.2020.0884.
Texto completoGeorge, Binto y Jayant R. Haritsa. "Secure buffering in firm real-time database systems". VLDB Journal The International Journal on Very Large Data Bases 8, n.º 3-4 (1 de febrero de 2000): 178–98. http://dx.doi.org/10.1007/s007780050003.
Texto completoDesnoyers, Mathieu y Michel R. Dagenais. "Lockless multi-core high-throughput buffering scheme for kernel tracing". ACM SIGOPS Operating Systems Review 46, n.º 3 (18 de diciembre de 2012): 65–81. http://dx.doi.org/10.1145/2421648.2421659.
Texto completoOrtiz, Jorge y David Andrews. "A Streaming High-Throughput Linear Sorter System with Contention Buffering". International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/963539.
Texto completoWang, Jia, Lin Liu, Yuchen Zhou y Shiyan Hu. "Buffering Carbon Nanotube Interconnects Considering Inductive Effects". Journal of Circuits, Systems and Computers 25, n.º 08 (17 de mayo de 2016): 1650093. http://dx.doi.org/10.1142/s0218126616500936.
Texto completoBYNA, SURENDRA, KIRK W. CAMERON y XIAN-HE SUN. "ISOLATING COSTS IN SHARED MEMORY COMMUNICATION BUFFERING". Parallel Processing Letters 15, n.º 04 (diciembre de 2005): 357–65. http://dx.doi.org/10.1142/s0129626405002271.
Texto completoWhite, Marcus y Stephen Glackin. "Broadband‐acre City: ‘No Traffic Problem, No Buffering’". Architectural Design 93, n.º 1 (enero de 2023): 30–37. http://dx.doi.org/10.1002/ad.2891.
Texto completoZhang, Tianpei y Sachin S. Sapatnekar. "Buffering global interconnects in structured ASIC design". Integration 41, n.º 2 (febrero de 2008): 171–82. http://dx.doi.org/10.1016/j.vlsi.2007.04.002.
Texto completoNenninger, Philipp, Oliver Rooks y Uwe Kiencke. "IMPROVED SYSTEM ARCHITECTURE FOR SAFETY-RELEVANT SYSTEMS USING DYNAMIC DISTRIBUTION AND STATE BUFFERING". IFAC Proceedings Volumes 38, n.º 1 (2005): 176–81. http://dx.doi.org/10.3182/20050703-6-cz-1902.01917.
Texto completoSundan, Bose y Kannan Arputharaj. "ADAPTIVE MULTIPATH MULTIMEDIA STREAMING ARCHITECTURE FOR MOBILE NETWORKS WITH PROACTIVE BUFFERING USING MOBILE PROXIES". Journal of Computing and Information Technology 15, n.º 3 (2007): 215. http://dx.doi.org/10.2498/cit.1000884.
Texto completoHuang, Sheng-Min y Li-Pin Chang. "Exploiting Page Correlations for Write Buffering in Page-Mapping Multichannel SSDs". ACM Transactions on Embedded Computing Systems 15, n.º 1 (20 de febrero de 2016): 1–25. http://dx.doi.org/10.1145/2815622.
Texto completoGeldenhuys, R., Y. Liu, M. T. Hill, G. D. Khoe, F. W. Leuschner y H. J. S. Dorren. "Architectures and Buffering for All-Optical Packet-Switched Cross-Connects". Photonic Network Communications 11, n.º 1 (enero de 2006): 65–75. http://dx.doi.org/10.1007/s11107-006-5324-0.
Texto completoQadri, Muhammad Yasir, Nadia N. Qadri, Martin Fleury y Klaus D. McDonald-Maier. "Software-Controlled Instruction Prefetch Buffering for Low-End Processors". Journal of Circuits, Systems and Computers 24, n.º 10 (25 de octubre de 2015): 1550161. http://dx.doi.org/10.1142/s0218126615501613.
Texto completoFang, J. P., Y. S. Tong y S. J. Chen. "Simultaneous routing and buffering in SOC floorplan design". IEE Proceedings - Computers and Digital Techniques 151, n.º 1 (2004): 17. http://dx.doi.org/10.1049/ip-cdt:20040072.
Texto completoLee, J. H., C. Weems y S. D. Kim. "Selective block buffering TLB system for embedded processors". IEE Proceedings - Computers and Digital Techniques 152, n.º 4 (2005): 507. http://dx.doi.org/10.1049/ip-cdt:20045025.
Texto completoChi Ta Wu, Ang-Chih Hsieh y Ting Ting Hwang. "Instruction buffering for nested loops in low-power design". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, n.º 7 (julio de 2006): 780–84. http://dx.doi.org/10.1109/tvlsi.2006.878348.
Texto completoMin, P. S., M. V. Hegde, A. Chandra y A. Maunder. "Analysis of banyan-based copy networks with internal buffering". Journal of High Speed Networks 5, n.º 3 (1996): 259–75. http://dx.doi.org/10.3233/jhs-1996-5303.
Texto completoGou, Xiantai. "An Adaptive Jitter Buffering Algorithm for Voice over IP Networks". Journal of Computer Research and Development 42, n.º 12 (2005): 2149. http://dx.doi.org/10.1360/crad20051218.
Texto completoHo, Dennis. "Climatic responsive atrium design in Europe". Architectural Research Quarterly 1, n.º 3 (1996): 64–75. http://dx.doi.org/10.1017/s135913550000292x.
Texto completoBregni, Stefano, Angelo Caruso y Achille Pattavina. "Buffering-deflection tradeoffs in optical burst switching". Photonic Network Communications 20, n.º 2 (4 de agosto de 2010): 193–200. http://dx.doi.org/10.1007/s11107-010-0259-x.
Texto completoYiannopoulos, K., S. Sygletos, M. Spyropoulou, E. Varvarigos y I. Tomkos. "Optical buffering up to 160 Gb/s employing a quantum dot semiconductor optical amplifier-based architecture". IET Optoelectronics 5, n.º 1 (1 de febrero de 2011): 50–56. http://dx.doi.org/10.1049/iet-opt.2009.0057.
Texto completoWang, Diane R., Rongkui Han, Edward J. Wolfrum y Susan R. McCouch. "The buffering capacity of stems: genetic architecture of nonstructural carbohydrates in cultivated Asian rice,Oryza sativa". New Phytologist 215, n.º 2 (30 de mayo de 2017): 658–71. http://dx.doi.org/10.1111/nph.14614.
Texto completoSarper, Hasan y Isik Aybay. "Improving VoD Performance with LAN Client Back-End Buffering". IEEE Multimedia 14, n.º 1 (2007): 48–60. http://dx.doi.org/10.1109/mmul.2007.13.
Texto completoLee, J., F. Peper, S. Adachi y K. Morita. "Universal delay-insensitive circuits with bidirectional and buffering lines". IEEE Transactions on Computers 53, n.º 8 (agosto de 2004): 1034–46. http://dx.doi.org/10.1109/tc.2004.51.
Texto completoMyllymaki, Jussi y Miron Livny. "Efficient buffering for concurrent disk and tape I/O". Performance Evaluation 27-28 (octubre de 1996): 453–71. http://dx.doi.org/10.1016/s0166-5316(96)90040-1.
Texto completoGarzarán, María Jesús, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger y Josep Torrellas. "Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors". ACM Transactions on Architecture and Code Optimization 2, n.º 3 (septiembre de 2005): 247–79. http://dx.doi.org/10.1145/1089008.1089010.
Texto completoYoon, Hanbin, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi y Onur Mutlu. "Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories". ACM Transactions on Architecture and Code Optimization 11, n.º 4 (9 de enero de 2015): 1–25. http://dx.doi.org/10.1145/2669365.
Texto completoPETRELLIS, N., G. ADAM y D. VENTZAS. "MONOTONIC ERROR ELIMINATION IN SUBRANGE A/D CONVERTERS". Journal of Circuits, Systems and Computers 22, n.º 01 (enero de 2013): 1250073. http://dx.doi.org/10.1142/s0218126612500739.
Texto completoDOROSHENKO, A. E. "ON ASYNCHRONOUS AVOIDANCE OF DEADLOCKS IN PARALLEL PROGRAMS". Parallel Processing Letters 02, n.º 02n03 (septiembre de 1992): 291–97. http://dx.doi.org/10.1142/s012962649200043x.
Texto completoWodnicki, Robert, Haochen Kang, Di Li, Douglas N. Stephens, Hayong Jung, Yizhe Sun, Ruimin Chen et al. "Highly Integrated Multiplexing and Buffering Electronics for Large Aperture Ultrasonic Arrays". BME Frontiers 2022 (30 de junio de 2022): 1–22. http://dx.doi.org/10.34133/2022/9870386.
Texto completoLoghi, M., P. Azzoni y M. Poncino. "Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, n.º 5 (mayo de 2009): 728–32. http://dx.doi.org/10.1109/tvlsi.2009.2016720.
Texto completoTOMITA, Ryuta, Katsuo INOUE y Syuta KAWAMATA. "HEAD IMPACT BUFFERING EFFECT OF DIRECT PASTED WOODEN FLOORINGS BY HUMAN FALLING IN THE HOUSE". AIJ Journal of Technology and Design 13, n.º 26 (2007): 591–96. http://dx.doi.org/10.3130/aijt.13.591.
Texto completoDavaasambuu, Battulga. "Handover with Buffering for Distributed Mobility Management in Software Defined Mobile Networks". Australian Journal of Telecommunications and the Digital Economy 6, n.º 1 (30 de marzo de 2018): 26–40. http://dx.doi.org/10.18080/ajtde.v6n1.137.
Texto completoDavaasambuu, Battulga. "Handover with Buffering for Distributed Mobility Management in Software Defined Mobile Networks". Journal of Telecommunications and the Digital Economy 6, n.º 1 (30 de marzo de 2018): 26–40. http://dx.doi.org/10.18080/jtde.v6n1.137.
Texto completoMa, X., J. Lee y M. Winslett. "High-level buffering for hiding periodic output cost in scientific simulations". IEEE Transactions on Parallel and Distributed Systems 17, n.º 3 (marzo de 2006): 193–204. http://dx.doi.org/10.1109/tpds.2006.36.
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