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Artículos de revistas sobre el tema "Bit-level"

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Publicado: 14 de marzo de 2023

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1

Peters, Martine. "French, Bit By Bit Multimedia Level 1". CALICO Journal 21, n.º 1 (4 de diciembre de 2017): 167–73. http://dx.doi.org/10.1558/cj.35193.

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2

Pikus, Marcin y Wen Xu. "Bit-Level Probabilistically Shaped Coded Modulation". IEEE Communications Letters 21, n.º 9 (septiembre de 2017): 1929–32. http://dx.doi.org/10.1109/lcomm.2017.2704596.

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3

Dong Ho Kim y Sang Wu Kim. "Bit-level stopping of turbo decoding". IEEE Communications Letters 10, n.º 3 (marzo de 2006): 183–85. http://dx.doi.org/10.1109/lcomm.2006.1603378.

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4

AGGOUN, A., A. ASHUR y M. K. IBRAHIM. "Bit-level pipelined digit-serial multiplier". International Journal of Electronics 75, n.º 6 (diciembre de 1993): 1209–19. http://dx.doi.org/10.1080/00207219308907196.

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5

Grover, Radhika S., Weijia Shang y Qiang Li. "Bit-level two's complement matrix multiplication". Integration 33, n.º 1-2 (diciembre de 2002): 3–21. http://dx.doi.org/10.1016/s0167-9260(02)00020-2.

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6

Donoho, David L. "Unconditional Bases and Bit-Level Compression". Applied and Computational Harmonic Analysis 3, n.º 4 (octubre de 1996): 388–92. http://dx.doi.org/10.1006/acha.1996.0032.

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7

Wang, Peng, Cui Ni, Zhe Li y Guangyuan Zhang. "Optimal CTU-level bit allocation in HEVC for low bit-rate applications". Multimedia Tools and Applications 78, n.º 16 (9 de mayo de 2019): 23733–47. http://dx.doi.org/10.1007/s11042-019-7680-7.

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8

Heule, Marijn y Hans van Maaren. "Parallel SAT Solving using Bit-level Operations1". Journal on Satisfiability, Boolean Modeling and Computation 4, n.º 2-4 (1 de mayo de 2008): 99–116. http://dx.doi.org/10.3233/sat190040.

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9

Roy, Satyaki. "The Extensive Bit-level Encryption System (EBES)". International Journal of Information Technology and Computer Science 5, n.º 5 (1 de abril de 2013): 67–73. http://dx.doi.org/10.5815/ijitcs.2013.05.09.

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10

Khanna, Neeraj, Dripto Chatterjee, Asoke Nath y Joyshree Nath. "Bit Level Encryption Standard (BLES): Version-I". International Journal of Computer Applications 52, n.º 2 (30 de agosto de 2012): 41–46. http://dx.doi.org/10.5120/8177-1496.

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11

Wagdy, M. F. "Diagnosing ADC nonlinearity at the bit level". IEEE Transactions on Instrumentation and Measurement 38, n.º 6 (1989): 1139–41. http://dx.doi.org/10.1109/19.46415.

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12

Aggoun, A., M. K. Ibrahim y A. Ashur. "Bit-level pipelined digit-serial array processors". IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, n.º 7 (julio de 1998): 857–68. http://dx.doi.org/10.1109/82.700933.

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13

Koç, Çetin K. y Ching Yu Hung. "Bit-level systolic arrays for modular multiplication". Journal of VLSI signal processing systems for signal, image and video technology 3, n.º 3 (septiembre de 1991): 215–23. http://dx.doi.org/10.1007/bf00925832.

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14

Ratan, Ram y Arvind Yadav. "Security Analysis of Bit plane Level Image Encryption Schemes". Defence Science Journal 71, n.º 2 (10 de marzo de 2021): 209–21. http://dx.doi.org/10.14429/dsj.71.15643.

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A selective bit-plane encryption scheme was proposed for securing the transmission of image data in mobile environments with a claim that it provides a high security viz. the encryption of the four most significant bit-planes is sufficient for a high image data security. This paper presents the security analysis of the said encryption scheme and reports new important results. We perform the security analysis of the bit-level encryption by considering the normal images and their histogram equalised enhanced images. We consider different bit-plane aspects to analyse the security of the image encryption, and show that the encryption of the four most significant bit-planes is not adequate. The contents of the images can be obtained even when all the bit-planes except one least significant bit-plane are encrypted in the histogram equalised images as shown in the results. The bit-plane level security analysis seems very useful for the analysis of the bit-plane level image encryption schemes.
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15

Swords, Sol. "Term-Level Reasoning in Support of Bit-blasting". Electronic Proceedings in Theoretical Computer Science 249 (2 de mayo de 2017): 95–111. http://dx.doi.org/10.4204/eptcs.249.7.

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16

McWhirter, J., D. Wood, K. Wood, R. Evans, J. McCanny y A. McCabe. "Multibit convolution using a bit level systolic array". IEEE Transactions on Circuits and Systems 32, n.º 1 (enero de 1985): 95–99. http://dx.doi.org/10.1109/tcs.1985.1085589.

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17

Zhang, Mu, Kui Cai, Qin Huang y Shuai Yuan. "On Bit-Level Decoding of Nonbinary LDPC Codes". IEEE Transactions on Communications 66, n.º 9 (septiembre de 2018): 3736–48. http://dx.doi.org/10.1109/tcomm.2018.2827994.

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18

Kankaala, K., T. Ala-Nissila y I. Vattulainen. "Bit-level correlations in some pseudorandom number generators". Physical Review E 48, n.º 6 (1 de diciembre de 1993): R4211—R4214. http://dx.doi.org/10.1103/physreve.48.r4211.

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19

Chang, L. W. y J. H. Lin. "A bit-level systolic array for median filter". IEEE Transactions on Signal Processing 40, n.º 8 (1992): 2079–83. http://dx.doi.org/10.1109/78.150009.

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20

Honjo, T., K. Tanaka y T. Nakamizo. "Bit level Systolic Implementation on LMS adaptive filter". Proceedings of the ISCIE International Symposium on Stochastic Systems Theory and its Applications 1995 (5 de mayo de 1995): 1–6. http://dx.doi.org/10.5687/sss.1995.1.

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21

Nayak, S. S., M. N. Murty y H. Panda. "Bit-level systolic implementation of discrete orthogonal transforms". Signal Processing 81, n.º 11 (noviembre de 2001): 2437–43. http://dx.doi.org/10.1016/s0165-1684(01)00021-4.

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22

Jullien, G. A., W. C. Miller, R. Grondin, L. Del Pup, S. S. Bizzan y Dapeng Zhang. "Dynamic computational blocks for bit-level systolic arrays". IEEE Journal of Solid-State Circuits 29, n.º 1 (1994): 14–22. http://dx.doi.org/10.1109/4.272090.

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23

Lu, Yang, Jun Xie, Hang Li y Huijuan Cui. "GOP-level bit allocation using reverse dynamic programming". Tsinghua Science and Technology 14, n.º 2 (abril de 2009): 183–88. http://dx.doi.org/10.1016/s1007-0214(09)70028-8.

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24

Lukac, Rastislav y Konstantinos N. Plataniotis. "Bit-level based secret sharing for image encryption". Pattern Recognition 38, n.º 5 (mayo de 2005): 767–72. http://dx.doi.org/10.1016/j.patcog.2004.11.010.

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25

Harrison, J. A., K. J. Blow y A. J. Poustie. "All-optical bit-level retiming and jitter suppression". Optics Communications 240, n.º 1-3 (octubre de 2004): 221–26. http://dx.doi.org/10.1016/j.optcom.2004.06.015.

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26

Bickel, Jessica E., Mina Khan y Katherine E. Aidala. "A multi-level single-bit data storage device". Journal of Applied Physics 115, n.º 17 (7 de mayo de 2014): 17D511. http://dx.doi.org/10.1063/1.4867603.

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27

Wu, Cheng-Wen y Ming-Kwang Chang. "Bit-level systolic arrays for finite-field multiplications". Journal of VLSI signal processing systems for signal, image and video technology 10, n.º 1 (junio de 1995): 85–92. http://dx.doi.org/10.1007/bf02407028.

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28

El-Aasser, Minar, Phoebe Edward, Mohamed Mandour, Mohamed Ashour y Tallal Elshabrawy. "A comprehensive hybrid bit-level and packet-level LoRa-LPWAN simulation model". Internet of Things 14 (junio de 2021): 100386. http://dx.doi.org/10.1016/j.iot.2021.100386.

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29

Sanghun Park y Kiyoung Choi. "Performance-driven high-level synthesis with bit-level chaining and clock selection". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, n.º 2 (2001): 199–212. http://dx.doi.org/10.1109/43.908436.

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30

Barannik, Vladimir, Yuriy Ryabukha, Pavlo Gurzhiy, Vitaliy Tverdokhlib y Igor Shevchenko. "TRANSFORMANTS BIT REPRESENTATION ENCODING WITHIN VIDEO BIT RATE CONTROL". Information systems and technologies security, n.º 1 (1) (2019): 52–56. http://dx.doi.org/10.17721/ists.2019.1.52-56.

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The conceptual basements of constructing an effective encoding method within the bit rate control module of video traffic in the video data processing system at the source level are considered. The essence of using the proposed method in the course of the video stream bit rate controlling disclosed, namely, the principles of constructing the fragment of the frame code representation and approaches for determining the structural units of the individual video frame within which the control is performed. The method focuses on processing the bit representation of the DCT transformants, and at his processing stage transformant was considered as a structural component of the video stream frame at which the encoding is performed. At the same time, to ensure the video traffic bit rate controlling flexibility, decomposition is performed with respect to each of the transformants to the level of the plurality of bit planes. It is argued that the proposed approach is potentially capable to reducing the video stream bit rate in the worst conditions, that is, when component coding is performed. In addition, this principle of video stream fragmen code representation forming allows to control the level of error that can be made in the bit rate control process. However, in conditions where the bit representation of the transformant is encoded, the method is able to provide higher compression rates as a result of the fact that the values of the detection probability of binary series lengths and the values of detected lengths within the bit plane will be greater than in the case of component coding. This is explained by the structural features of the distribution of binary elements within each of the bit planes, which together form the transformer DCT. In particular, high-frequency transformer regions are most often formed by chains of zero elements. The solutions proposed in the development of the encoding method are able to provide sufficient flexibility to control the bit rate of the video stream, as well as the ability to quickly change the bit rate in a wide range of values
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31

Xue, Linlin, Jianhong Lv y Zhongpeng Wang. "Performance Enhancement of Bit-Level XOR Compressed Image OFDM Transmission Systems". Mobile Information Systems 2022 (27 de agosto de 2022): 1–12. http://dx.doi.org/10.1155/2022/4364706.

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The bit error rate (BER) formula of the M-QAM system is derived under nonequally likely condition of the constellation points, from which improving the BER performance of the M-QAM system by optimizing the probability distribution of constellation points is identified. Based on the analysis, the bit-level XOR method is employed to encrypt the image data and modify the probability distribution of the constellation points. The simulation results show that bit-level XOR is helpful to obtain a better probability distribution of the 16-QAM system compared to that without bit XOR and hence can improve the BER performance of the proposed OFDM transmission system. Simulation results based on test images over the AWGN channel further confirm that the reliability of the OFDM transmission system and the reconstructed quality of the compressed image are both significantly enhanced using bit-level XOR operation.
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32

Seo, Hwajeong, Hyunjun Kim, Kyoungbae Jang, Hyeokdong Kwon, Minjoo Sim, Gyeongju Song y Siwoo Uhm. "Compact Implementation of ARIA on 16-Bit MSP430 and 32-Bit ARM Cortex-M3 Microcontrollers". Electronics 10, n.º 8 (11 de abril de 2021): 908. http://dx.doi.org/10.3390/electronics10080908.

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In this paper, we propose the first ARIA block cipher on both MSP430 and Advanced RISC Machines (ARM) microcontrollers. To achieve the optimized ARIA implementation on target embedded processors, core operations of ARIA, such as substitute and diffusion layers, are carefully re-designed for both MSP430 (Texas Instruments, Dallas, TX, USA) and ARM Cortex-M3 microcontrollers (STMicroelectronics, Geneva, Switzerland). In particular, two bytes of input data in ARIA block cipher are concatenated to re-construct the 16-bit wise word. The 16-bit word-wise operation is executed at once with the 16-bit instruction to improve the performance for the 16-bit MSP430 microcontroller. This approach also optimizes the number of required registers, memory accesses, and operations to half numbers rather than 8-bit word wise implementations. For the ARM Cortex-M3 microcontroller, the 8×32 look-up table based ARIA block cipher implementation is further optimized with the novel memory access. The memory access is finely scheduled to fully utilize the 3-stage pipeline architecture of ARM Cortex-M3 microcontrollers. Furthermore, the counter (CTR) mode of operation is more optimized through pre-computation techniques than the electronic code book (ECB) mode of operation. Finally, proposed ARIA implementations on both low-end target microcontrollers (MSP430 and ARM Cortex-M3) achieved (209 and 96 for 128-bit security level, respectively), (241 and 111 for 192-bit security level, respectively), and (274 and 126 for 256-bit security level, respectively). Compared with previous works, the running timing on low-end target microcontrollers (MSP430 and ARM Cortex-M3) is improved by (92.20% and 10.09% for 128-bit security level, respectively), (92.26% and 10.87% for 192-bit security level, respectively), and (92.28% and 10.62% for 256-bit security level, respectively). The proposed ARIA–CTR implementation improved the performance by 6.6% and 4.0% compared to the proposed ARIA–ECB implementations for MSP430 and ARM Cortex-M3 microcontrollers, respectively.
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33

Singha, Jayashree, Saikat Jana y Souvik Singha. "Encoding Algorithm using Bit Level Encryption and Decryption Technique". International Journal of Computer Applications 160, n.º 2 (15 de febrero de 2017): 23–26. http://dx.doi.org/10.5120/ijca2017912975.

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34

Tiwari, Shashwat, Ayushi Lal, Shivani Agarwal, Ayush Kumar, Anupam Singh y Nitin Arora. "Novel bit-level Adaptive and Asymmetric Data Compression Technique". International Journal of Computer Applications 177, n.º 35 (17 de febrero de 2020): 14–17. http://dx.doi.org/10.5120/ijca2020919832.

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35

Kito, Nobutaka y Kazuyoshi Takagi. "An RSFQ flexible-precision multiplier utilizing bit-level processing". Journal of Physics: Conference Series 1975, n.º 1 (1 de julio de 2021): 012025. http://dx.doi.org/10.1088/1742-6596/1975/1/012025.

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36

Hubballi, Neminath y Mayank Swarnkar. "$BitCoding$ : Network Traffic Classification Through Encoded Bit Level Signatures". IEEE/ACM Transactions on Networking 26, n.º 5 (octubre de 2018): 2334–46. http://dx.doi.org/10.1109/tnet.2018.2868816.

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37

Chung-Chin Lu y Sy-Hann Huang. "On bit-level trellis complexity of Reed-Muller codes". IEEE Transactions on Information Theory 41, n.º 6 (1995): 2061–64. http://dx.doi.org/10.1109/18.476337.

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38

Benkrid, Khaled. "New bit-level algorithm for general purpose median filtering". Journal of Electronic Imaging 12, n.º 2 (1 de abril de 2003): 263. http://dx.doi.org/10.1117/1.1557153.

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39

Vardy, A. y Y. Be'ery. "Bit-level soft-decision decoding of Reed-Solomon codes". IEEE Transactions on Communications 39, n.º 3 (marzo de 1991): 440–44. http://dx.doi.org/10.1109/26.79287.

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40

Petkov, Nikolai y Fridrich Sloboda. "A bit-level systolic array for digital contour smoothing". Parallel Computing 12, n.º 3 (diciembre de 1989): 301–13. http://dx.doi.org/10.1016/0167-8191(89)90088-4.

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41

Chang, Long-Wen y Ming-Chang Wu. "A bit level systolic array for Walsh-Hadamard transforms". Signal Processing 31, n.º 3 (abril de 1993): 341–47. http://dx.doi.org/10.1016/0165-1684(93)90091-n.

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42

Knowles, S. C., J. G. McWhirter, R. F. Woods y J. V. McCanny. "Bit-Level systolic architectures for high performance IIR filtering". Journal of VLSI signal processing systems for signal, image and video technology 1, n.º 1 (agosto de 1989): 9–24. http://dx.doi.org/10.1007/bf00932062.

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43

Woods, Roger F., John V. McCanny y John G. McWhirter. "From Bit Level Systolic Arrays to HDTV Processor Chips". Journal of Signal Processing Systems 53, n.º 1-2 (4 de octubre de 2007): 35–49. http://dx.doi.org/10.1007/s11265-007-0132-z.

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44

Hu, Z. y G. A. King. "A bit-level systolic implementation of the median filter". Microprocessors and Microsystems 19, n.º 4 (enero de 1995): 185–86. http://dx.doi.org/10.1016/0141-9331(95)91857-z.

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45

Ait-Boudaoud, D., M. K. Ibrahim y B. R. Hayes-Gill. "Novel cell architecture for bit level systolic arrays multiplication". IEE Proceedings E Computers and Digital Techniques 138, n.º 1 (1991): 21. http://dx.doi.org/10.1049/ip-e.1991.0003.

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46

Um, Junhyung y Taewhan Kim. "Optimal bit-level arithmetic optimisation for high-speed circuits". Electronics Letters 36, n.º 5 (2000): 405. http://dx.doi.org/10.1049/el:20000337.

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47

Hoekstra, J. "Junction charge-coupled devices for bit-level systolic arrays". IEE Proceedings G (Electronic Circuits and Systems) 134, n.º 4 (1987): 194. http://dx.doi.org/10.1049/ip-g-1.1987.0027.

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48

Lin, Yi-Nan, Wei-Wen Hung, Tsan-Jieh Chen y Erl-Huei Lu. "Modeling the bit-level stochastic correlation for turbo decoding". Computer Communications 29, n.º 18 (noviembre de 2006): 3856–62. http://dx.doi.org/10.1016/j.comcom.2006.06.023.

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49

Li, Zhen, Changgen Peng, Weijie Tan y Liangrong Li. "A Novel Chaos-Based Color Image Encryption Scheme Using Bit-Level Permutation". Symmetry 12, n.º 9 (11 de septiembre de 2020): 1497. http://dx.doi.org/10.3390/sym12091497.

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To ensure the security of digital images during transmission and storage, an efficient and secure chaos-based color image encryption scheme using bit-level permutation is proposed. Our proposed image encryption algorithm belongs to symmetric cryptography. Here, we process three color components simultaneously instead of individually, and consider the correlation between them. We propose a novel bit-level permutation algorithm that contains three parts: a plain-image related rows and columns substitution, a pixel-level roll shift part, and a bit-level cyclic shift part. In the plain-related rows and columns substitution part, we involve the plain-image information to generate a control sequence by using a skew tent system. This process ensures that the correlation between three color components can be totally broken, and our cryptosystem has enough plain-image sensitivity to resist the differential attack. In the pixel-level roll shift part and bit-level cyclic shift part, we have a fully bit-level permutation controlled by two sequences using a Rucklidge system. The simulation and some common security analyses are given. Test results show that our proposed scheme has good security performance and a speed advantage compared to other works.
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50

Hu, Yingchun, Simin Yu y Zeqing Zhang. "On the Cryptanalysis of a Bit-Level Image Chaotic Encryption Algorithm". Mathematical Problems in Engineering 2020 (3 de agosto de 2020): 1–15. http://dx.doi.org/10.1155/2020/5747082.

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In this paper, the security analysis of a bit-level image chaotic encryption algorithm based on the 1D chaotic map is proposed. The original image chaotic encryption algorithm includes bit-level permutation encryption, diffusion encryption, and linear transform. Deciphering of it can be divided into two stages. First, bit-level permutation encryption, diffusion encryption, and linear transform can be simplified into bit-level equivalent permutation encryption and equivalent diffusion encryption, which is a key breakthrough point of cryptanalysis. Second, the chaotic sequence generated by this algorithm is independent of the plaintext image. Therefore, the equivalent diffusion key and the equivalent permutation key can be obtained by chosen-plaintext attack, respectively. Theoretical analysis and numerical simulation experiment results verify the effectiveness of the analytical method. Finally, some suggestions are proposed to promote the security of the original image chaotic encryption algorithm.
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