Literatura académica sobre el tema "Bank Level Parallelism (BLP)"
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Artículos de revistas sobre el tema "Bank Level Parallelism (BLP)"
Shin, Wongyu, Jaemin Jang, Jungwhan Choi, Jinwoong Suh y Lee-Sup Kim. "Bank-Group Level Parallelism". IEEE Transactions on Computers 66, n.º 8 (1 de agosto de 2017): 1428–34. http://dx.doi.org/10.1109/tc.2017.2665475.
Texto completoXue, Dongliang, Linpeng Huang y Chentao Wu. "A pure hardware-driven scheduler for enhancing bank-level parallelism in a persistent memory controller". Future Generation Computer Systems 107 (junio de 2020): 383–93. http://dx.doi.org/10.1016/j.future.2020.01.047.
Texto completoNajoui, Mohamed, Mounir Bahtat, Anas Hatim, Said Belkouch y Noureddine Chabini. "VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing". Journal of Circuits, Systems and Computers 26, n.º 09 (24 de abril de 2017): 1750129. http://dx.doi.org/10.1142/s0218126617501298.
Texto completoKhadirsharbiyani, Soheil, Jagadish Kotra, Karthik Rao y Mahmut Taylan Kandemir. "Data Convection". ACM SIGMETRICS Performance Evaluation Review 50, n.º 1 (20 de junio de 2022): 37–38. http://dx.doi.org/10.1145/3547353.3522647.
Texto completoMa, Jianliang, Jinglei Meng, Tianzhou Chen y Minghui Wu. "CaLRS: A Critical-Aware Shared LLC Request Scheduling Algorithm on GPGPU". Scientific World Journal 2015 (2015): 1–10. http://dx.doi.org/10.1155/2015/848416.
Texto completoGRÉWAL, G., S. COROS y M. VENTRESCA. "A MEMETIC ALGORITHM FOR PERFORMING MEMORY ASSIGNMENT IN DUAL-BANK DSPS". International Journal of Computational Intelligence and Applications 06, n.º 04 (diciembre de 2006): 473–97. http://dx.doi.org/10.1142/s1469026806002039.
Texto completoFang, Juan, Jiajia Lu, Mengxuan Wang y Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems". Journal of Circuits, Systems and Computers 28, n.º 07 (27 de junio de 2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.
Texto completoFang, Juan, Mengxuan Wang y Zelin Wei. "A memory scheduling strategy for eliminating memory access interference in heterogeneous system". Journal of Supercomputing 76, n.º 4 (10 de enero de 2020): 3129–54. http://dx.doi.org/10.1007/s11227-019-03135-7.
Texto completoKhadirsharbiyani, Soheil, Jagadish Kotra, Karthik Rao y Mahmut Kandemir. "Data Convection". Proceedings of the ACM on Measurement and Analysis of Computing Systems 6, n.º 1 (24 de febrero de 2022): 1–25. http://dx.doi.org/10.1145/3508027.
Texto completoLiao, Xiaofei, Zhan Zhang, Haikun Liu y Hai Jin. "Improving Bank-level Parallelism for In-Memory Checkpointing in Hybrid Memory Systems". IEEE Transactions on Big Data, 2018, 1. http://dx.doi.org/10.1109/tbdata.2018.2865964.
Texto completoTesis sobre el tema "Bank Level Parallelism (BLP)"
Patil, Adarsh. "Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures". Thesis, 2017. http://etd.iisc.ac.in/handle/2005/4124.
Texto completoWang, Shao-Fu y 王少甫. "Exploiting Bank-level Parallelism via Data Consistency Relaxation for Non-volatile Memory System". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/55825295588163105110.
Texto completo國立臺灣大學
資訊工程學研究所
103
The maturity of emerging non-volatile memory (NVM) technologies presents promising next-generation memory system design. Because of its mixed performance characteristics between DRAM and persistent store, e.g., high density, byte-addressability, and non-volatility, architects rethink the design of traditional memory hierarchy. With NVM as main memory, programmer can place non-volatile data structures on main memory and directly access them by ld/st instructions. Non-volatile data structures demand consistency and atomicity guarantees in case of sudden system crash. To guarantee consistency and atomicity, some forms of write-ahead logging (WAL) semantics are needed. Because modern memory controller reorders writes to exploit bank-level parallelism, persist barrier is adopted by many existing works to guarantee the order between writes. However, we observe that persist barriers introduce unnecessary write ordering constraints and hurt the system performance by restricting memory controller from exploiting bank-level parallelism. In this thesis, we propose Semantics-aware Memory Scheduler. By using a new software/hardware interface to transfer knowledge of application''s logging semantics to memory controller, Semantics-aware Memory Scheduler eliminates unnecessary write ordering constraints by differentiating between log writes and target data writes. Through allowing more concurrent memory writes, memory controller can provide more performance by maximizing bank-level parallelism. Experimental results of full-system simulation show that Semantics-aware Memory Scheduler can improve throughput by up to 2.89x (2.13x on average).
Actas de conferencias sobre el tema "Bank Level Parallelism (BLP)"
Malik, Kshitiz, Mayank Agarwal, Sam S. Stone, Kevin M. Woley y Matthew I. Frank. "Branch-mispredict level parallelism (BLP) for control independence". En 2008 IEEE 14th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2008. http://dx.doi.org/10.1109/hpca.2008.4658628.
Texto completoTang, Xulong, Mahmut Kandemir, Praveen Yedlapalli y Jagadish Kotra. "Improving bank-level parallelism for irregular applications". En 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2016. http://dx.doi.org/10.1109/micro.2016.7783760.
Texto completoDing, Wei, Diana Guttman y Mahmut Kandemir. "Compiler Support for Optimizing Memory Bank-Level Parallelism". En 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2014. http://dx.doi.org/10.1109/micro.2014.34.
Texto completoLee, Chang Joo, Veynu Narasiman, Onur Mutlu y Yale N. Patt. "Improving memory bank-level parallelism in the presence of prefetching". En the 42nd Annual IEEE/ACM International Symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1669112.1669155.
Texto completoPoremba, Matthew, Tao Zhang y Yuan Xie. "Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision". En DAC '16: The 53rd Annual Design Automation Conference 2016. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2897937.2898024.
Texto completoKwon, Young-Cheon, Suk Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je Min Ryu, Jong-Pil Son, O. Seongil et al. "25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications". En 2021 IEEE International Solid- State Circuits Conference (ISSCC). IEEE, 2021. http://dx.doi.org/10.1109/isscc42613.2021.9365862.
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