Tesis sobre el tema "Audio circuits"

Cette thèse porte sur la modélisation de composants électroniques non linéaires pour la simulation de circuits analogiques audio. Notre but est de proposer des modèles à la fois assez sophistiqués pour que les simulations sonnent de façon réaliste, et assez simples pour permettre le temps réel. À cette fin, nous explorons deux approches, toutes deux fondées sur le formalisme des Systèmes Hamiltoniens à Ports (SHP). En effet, ce formalisme préserve la passivité et le bilan de puissance du système, ce qui, couplé à des méthodes numériques ad hoc, garantit la stabilité des simulations. La première approche est orientée "boîte blanche" : on suppose la topologie du circuit connue et on se concentre sur la modélisation de composants spécifiques, à savoir les bobines ferromagnétiques (présentes dans les pédales wah-wah et les amplis guitare) et les opto-isolateurs (présents dans les trémolos et les compresseurs optiques). Les modèles proposés sont issus de la physique, passifs, modulaires, et utilisables en temps réel. La deuxième approche est orientée "boîte grise" : on cherche à retrouver la topologie et les lois constitutives d'un circuit à partir de mesures. L'apprentissage est informé par une structure SHP sous-jacente, et les non-linéarités sont traitées au moyen de noyaux reproduisants. Ainsi, on impose certaines propriétés physiques indispensables, tout en autorisant une large gamme de comportements non linéaires. Le modèle obtenu est interprétable et nécessite moins de paramètres comparé à un modèle issu de réseaux profonds. Enfin, une généralisation de cette approche pour une plus grand classe de circuits est esquissée à travers l'introduction de l'opérateur de Koopman<br>This thesis is concerned with the modeling of nonlinear components and circuits for simulations in audio applications. Our goal is to propose models that are sufficiently sophisticated for simulations to sound realistic, but that remain simple enough for real time to be attainable. To this end, we explore two approaches, both based on a port-Hamiltonian systems formulation. Indeed, this formulation structurally guarantees power balance and passivity. Combined with ad hoc numerical methods, this ensures the numerical stability of simulations. The first approach is comparable to "white box" modeling. It assumes that the circuit topology is known, and focuses on the modeling of specific components found in vintage audio circuits, namely ferromagnetic coils (found in wah-wah pedals and guitar amplifiers) and opto-isolators (found in tremolos and optical compressors). The proposed models are physically-based, passive, modular, and usable in real time. The second approach is comparable to "grey box" modeling. It aims to retrieve the topology and constitutive laws of a circuit from measurements. The learning of the circuit topology is informed by an underlying port-Hamiltonian formulation, and nonlinearities are concomitantly addressed through kernel-based methods. Thus, necessary physical properties are enforced, while the use of reproducing kernels allows for a variety of nonlinear behaviors to be described with a smaller number of parameters and a higher interpretability compared to neural network methods. Finally, a possible generalization of this approach for a larger class of circuits is outlined through the introduction of the Koopman operator

A la différence de la conception numérique, la conception analogique souffre d’un réel retard au niveau de la solution logicielle qui permet une conception à la fois rapide et fiable. Le dimensionnement de circuits analogiques exige en effet un nombre assez élevé de simulations et de vérifications et dépend beaucoup de l’expertise du concepteur. Pour pallier à ce retard, des outils de conception automatique basés sur des algorithmes d’optimisation locale et globale sont développés. Ces outils restent encore immatures car ils n’offrent que des réponses partielles aux questions du dimensionnement, alors que l’obtention d’un dimensionnement optimal d’un circuit analogique en un temps raisonnable reste toujours un enjeu majeur. La réduction du temps de conception de circuits analogiques intégrés nécessite la mise en place de méthodologies permettant une conception systématique et automatisable sur certaines étapes. Dans le cadre de cette thèse, nous avons travaillé suivant trois approches. Il s’agit d’abord de l’approche méthodologique. A ce niveau nous préconisons une approche hiérarchique descendante « top-down ». Cette dernière consiste à partitionner le système à dimensionner en sous blocs de fonctions élémentaires dont les spécifications sont directement héritées des spécifications du niveau système. Ensuite, nous avons cherché à réduire le temps de conception à travers l’exploration de solutions optimales à l’aide des algorithmes hybrides. Nous avons cherché à profiter de la rapidité de la recherche globale et de la précision de la recherche locale. L’intérêt des algorithmes de recherche hybride réside dans le fait qu’ils permettent d’effectuer une exploration efficace de l’espace de conception du circuit sans avoir besoin d’une connaissance préalable d’un dimensionnement initial. Ce qui peut être très intéressant pour un concepteur débutant. Enfin, nous avons travaillé sur l’accélération du temps des simulations en proposant l’utilisation des méta-modèles. Ceux-ci présentent un temps de simulation beaucoup plus réduit que celui des simulations des modèles électriques. Les méta-modèles sont obtenus automatiquement depuis une extraction des résultats des simulations électriques<br>Contrary to digital design, analog design suffers from a real delay in the software solution that enables fast and reliable design. In this PhD, three approaches are proposed. The first is the methodological approach. At this level we recommend a "top-down" hierarchical approach. It consists of partitioning the system to size into sub-blocks of elementary functions whose specifications are directly inherited from the system level specification. Next, we aimed to reduce design time through the exploration of optimal solutions using hybrid algorithms. We attempted to take advantage of the rapid global search and local search accuracy. The interest of hybrid search algorithms is that they allow to conduct effective exploration of the design space of the circuit without the need for prior knowledge of an initial design. This can be very useful for a beginner designer. Finally, we worked on the acceleration of time simulations proposing the use of meta-models which present a more reduced time than electrical simulation models. Meta-models are obtained automatically from extracting results of electrical simulations

Cette thèse s'intéresse à la simulation temps-réel de circuit audio nonlinéaires. Dans cette thèse, nous utilisons le formalisme des systèmes Hamiltoniens à ports (SHP) pour garantir le bilan de puissance et la passivité. De plus, nous adoptons un cadre fonctionnel à temps continu pour représenter des signaux "analogiques virtuels" et nous proposons d'approximer les solutions par projection sur des trames temporelles. En tant que résultat principal, nous établissons une condition suffisante sur les projecteurs de sorte à obtenir des trajectoires à bilan de puissance garanti. Notre but est double: premièrement, pour gérer l'expansion de bande-passante causée par les nonlinéarités, nous considérons des méthodes numériques traitant des signaux à bande non-limitée qui à la place ont un "taux d'innovation borné"; Deuxièmement, pour revenir dans le domaine des signaux à bande limitée, nous concevons des "convertisseurs analogique-numérique virtuels" Plusieurs méthodes numériques sont construites afin d'être à bilan de puissance garanti, avec une précision d'ordre élevé et un un ordre de régularité contrôlable. Leurs propriétés sont étudiées: existence et unicité, ordre de précision, dispersion, mais aussi, résolution fréquentielle au delà de la fréquence de Nyquist, rejet du repliement ainsi que noyaux reproduisants et noyaux de Peano. Cette approche révèle des ponts entre l'analyse numérique, le traitement du signal et la théorie de l'échantillonnage généralisé en mettant en relation la précision, la propriété de reproduction des polynômes, la bande passante ou les bancs de filtre de Legendre, etc. Nous exposons un cadre systématique pour transformer des schémas électronique en équations puis en simulations. Ce cadre est ensuite appliqué à des circuits audio représentatifs, contenant à la fois des équations différentielles ordinaires et des équation algebro-différentielles. Un travail spécifique est dédié à la modélisation SHP des amplificateurs opérationnels. Enfin, nous revisitons la modélisation des SHP dans le cadre de l'algèbre géométrique, ce qui ouvre des perspectives pour l'encodage de la structure géométrique des équations<br>This work addresses the real-time simulation of nonlinear audio circuits. In this thesis, we use the port-Hamiltonian (pH) formalism to guarantee power balance and passivity. Moreover, we adopt a continuous-time functional framework to represent "virtual analog" signals and propose to approximate solutions by projection over time frames. As a main result, we establish a sufficient condition on projectors to obtain time-continuous power-balanced trajectories. Our goal is twofold: first, to manage frequency-bandwidth expansion due to nonlinearities, we consider numerical engines processing signals that are not bandlimited but, instead, have a "finite rate of innovation"; second, to get back to the bandlimited domain, we design "virtual analog-to-digital converters". Several numerical methods are built to be power-balanced, high-order accurate, with a controllable regularity order. Their properties are studied: existence and uniqueness, accuracy order and dispersion, but also, frequency resolution beyond the Nyquist frequency, aliasing rejection, reproducing and Peano kernels. This approach reveals bridges between numerical analysis, signal processing and generalised sampling theory, by relating accuracy, polynomial reproduction, bandwidth, Legendre filterbanks, etc. A systematic framework to transform schematics into equations and simulations is detailed. It is applied to representative audio circuits (for the UVI company), featuring both ordinary and differential-algebraic equations. Special work is devoted to pH modelling of operational amplifiers. Finally, we revisit pH modelling within the framework of Geometric Algebra, opening perspectives for structure encoding

L’objectif de ce travail c’est l’étude et développement d’un système d’extraction des caractéristiques en utilisant techniques de traitement de signal en temps continu, afin de mitiger les inconvénients des implémentations existants basées en techniques analogiques et numériques conventionnelles, d’un système toujours en veille pour l’Internet des Objets. La cible est l’extraction du contenu spectral d’un signal audio en utilisant une nouvelle architecture basée en une cascade configurable de filtres à réponse impulsionnelle fini en temps continu. Un schéma efficace pour cascader des filtres est obtenu grâce aux techniques proposées pour l’élimination des glitches et du codage delta. Par ailleurs, ce travail introduit une fonction en temps continu pour estimer la puissance instantanée dans des bandes de fréquences sélectionnées et construire un spectrogramme à la sortie. Le système proposé à 12-bandes fréquentielles a été validée par des simulations comportementales. L’élément clé pour l’implémentation de ce système est un élément de délai numérique. Un nouveau élément de retard a été conçu et fabriquée en technologie 28 nm FDSOI et atteints une plage de délai record entre 30 ns et 97 µs avec une consommation de puissance de 15fJ/événement. En extrapolant ce résultat, le système proposé atteints une consommation approximée de 2.85 µW lors du traitement d’un signal vocal produit par une femme, tandis que la consommation statique est autours de 100 nW dans les périodes où il n’y a pas d’activité. Donc, la performance en termes de consommation moyenne d’énergie de ce système surpasse celle des implémentations dans l’état de l’art<br>The focus of this work is the study and development of a feature extraction system using Continuous-Time Digital Signal Processing (CT DSP) techniques, to mitigate the drawbacks of existing implementations based on traditional analog and digital solutions of always-on monitoring sensors for the Internet of Things (IoT). The target is to extract the spectral content of an audio signal using a novel architecture based on a cascade of configurable CT DSP Finite Impulse Response (FIR) filters. An efficient cascade scheme is enabled by the proposed glitch elimination and delta encoding techniques. Additionally, this work introduces a CT function to estimate the instantaneous power within selected frequency bands to build an output spectrogram. The proposed 12-band system has been validated using behavioral simulations. The key element for the implementation of this system is the digital delay element. A new delay element has been designed and fabricated in 28nm FDSOI technology and achieves a record tuning range from 30 ns to 97 µs with a power consumption of 15 fJ/event. By extrapolating this result, the system would have an overall peak power consumption of 2.85 µW when processing typical female speech, while consuming approximately 100 nW when no events are generated. Thus, the average system power consumption outperforms state-of-the-art feature extraction circuits

In immersive audio environments with distributed microphones, Independent Component Analysis (ICA) can be applied to uncover signals from a mixture of other signals and noise, such as in a cocktail party recording. ICA algorithms have been developed for instantaneous source mixtures and convolutional source mixtures. While ICA for instantaneous mixtures works when no delays exist between the signals in each mixture, distributed microphone recordings typically result various delays of the signals over the recorded channels. The convolutive ICA algorithm should account for delays; however, it requires many parameters to be set and often has stability issues. This thesis introduces the Channel Aligned FastICA (CAICA), which requires knowledge of the source distance to each microphone, but does not require knowledge of noise sources. Furthermore, the CAICA is combined with Time Frequency Masking (TFM), yielding even better SOI extraction even in low SNR environments. Simulations were conducted for ranking experiments tested the performance of three algorithms: Weighted Beamforming (WB), CAICA, CAICA with TFM. The Closest Microphone (CM) recording is used as a reference for all three. Statistical analyses on the results demonstrated superior performance for the CAICA with TFM. The algorithms were applied to experimental recordings to support the conclusions of the simulations. These techniques can be deployed in mobile platforms, used in surveillance for capturing human speech and potentially adapted to biomedical fields.

Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted. A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region. The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell. Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.

Mestrado em Engenharia Electrónica e Telecomunicações<br>O objectivo principal da presente tese de mestrado centrou-se no desenho e construção de uma unidade de efeitos de áudio (Audio Effects Unit -AEU), cuja função consiste em processar sinais áudio em tempo real. O propósito central foi desenvolver uma unidade de processamento áudio genérica, cuja função de processamento, implementada no domínio digital, pode ser facilmente especificada pelo utilizador via uma aplicação de software implementada num computador. A primeira etapa deste projecto consistiu na implementação completa do hardware que constitui o AEU. É importante acrescentar que esta concepção teve em conta a inclusão desse hardware numa caixa apropriada. Este método de projecto e implementação constituiu uma experiência muito interessante e útil. A próxima etapa consistiu no desenvolvimento de algoritmos matemáticos a ser implementados no microcontrolador do AEU e que geram os efeitos sonoros desejados por processamento dos sinais áudio originais. Estes algoritmos foram inicialmente testados através do Matlab. Para controlar os efeitos sonoros produzidos foi ainda criada uma aplicação de computador que permite a intervenção, de forma muito simples, do utilizador. A referida aplicação assegura a comunicação entre o microcontrolador do AEU e o computador através de uma ligação USB. O dispositivo, na sua versão final, foi testado em laboratório e através do Matlab. Cada bloco do dispositivo, e o dispositivo completo, foi testado individualmente. Com base nessa avaliação foram desenhadas as respectivas características na frequência e analisada a qualidade do dispositivo de áudio. Para além da experiência adquirida em concepção de hardware, este projecto permitiu-me alargar o meu conhecimento em programação de microcontroladores e na optimização de código, um requisito do processamento de sinal em tempo real. Também me deu a oportunidade de utilizar a ferramenta comercial MPLAB para programação de microcontroladores.<br>The main aim of this master thesis was to design and build an Audio Effects Unit (AEU), whose function is to process, a particular audio signal in real time. The objective was to develop a general purpose audio processing unit where the processing function, implemented in the digital domain, can be easily specified by the user by means of a software application running on a computer. The first stage of this project consisted on the full design and implementation of the hardware that constitutes the AEU. It is worth adding that such design also considered that the layout could be placed in an enclosure. Such way of designing was a great new experience. The next stage was to prepare the mathematical algorithms to be implemented in the AEU microcontroller which create the sound effects by processing the original audio signal. These algorithms were first tested in MatLab. To control the produced sound effects a computer program was created which allows the user intervention in a straightforward way. This program ensures communication between the AEU microcontroller and PC software using an USB connection. The completed device was tested in laboratory and with Matlab. The individual blocks of the AEU, and the whole device, were tested. On the basis of these tests frequency characteristics were drawn and the quality of the audio device was analyzed. Besides acquiring expertise in hardware design, this project has broadened my knowledge on microcontroller programming and code optimization, a requirement for real time signal processing. It also gave me the opportunity to use the commercial MPLAB programming environment.<br>Głównym celem tej pracy magisterskiej było zaprojektowanie i zbudowanie układu do generowania efektów dźwiękowych (Audio Effects Unit - AEU) służącego do przetwarzania sygnału dźwiękowego w czasie rzeczywistym. Zadaniem autora było skonstruowanie ogólnego zastosowania układu przetwarzającego sygnał dźwiękowy, w którym funkcja przetwarzania, zaimplementowana w sposób cyfrowy, może być łatwo określona przez użytkownika poprzez zastosowanie odpowiedniego oprogramowania komputerowego. Pierwszy etap projektu polegał na szczegółowym zaprojektowaniu i zbudowaniu warstwy sprzętowej tworzącej AEU. W projekcie przewidziano tez możliwość umieszczenia układu w obudowie, co było dla autora nowym doświadczeniem projektowym. Kolejnym etapem było opracowanie algorytmów matematycznych, zaimplementowanych w mikrokontrolerze AEU, które tworzą efekty dźwiękowe poprzez przetwarzanie oryginalnego sygnału dźwiękowego. Te algorytmy zostały najpierw przetestowane w programie MatLab. Do kontrolowania wytworzonych efektów dźwiękowych, został napisany program komputerowy, który pozwala na prostą interakcje z użytkownikiem. Ten program zapewnia komunikację między mikrokontrolerem AEU i oprogramowaniem komputerowym poprzez złącze USB. Gotowe urządzenie zostało zbadane w laboratorium oraz za pomocą programu Matlab. Poszczególne bloki AEU jak i całe urządzenie zostały przetestowane, co pozwoliło na wykreślenie charakterystyk częstotliwościowych i umożliwiło analizę jakości wykonanego urządzenia audio. Oprócz zdobywania doświadczenia w projektowaniu sprzętu, udział w projekcie poszerzył moją wiedzę o programowaniu mikrokontrolerów i optymalizacji kodu, potrzebną dla przetwarzania sygnału w czasie rzeczywistym. Ponadto miałem możliwość zapoznania się z komercyjnym środowiskiem programistycznym MPLAB.

Orientador: Oseas Valente de Avilez Filho<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação<br>Made available in DSpace on 2018-07-22T00:41:17Z (GMT). No. of bitstreams: 1 Castro_JoseEduardoGarcia_M.pdf: 3681554 bytes, checksum: 3f4b9397fc9994dd2fabcf11eed7aec2 (MD5) Previous issue date: 1997<br>Resumo: Este trabalho objetiva o estudo de técnicas para os vários blocos funcionais de um amplificador comutado em áudio. A faixa de aplicação a que se direciona este estudo compreende os seguintes (baixas tensões, médias requisitos: potências). Aplicação Automotiva baixo custo e médio desempenho. Neste estudo, faz-se a classificação das topologias interessantes para a faixa definida; comentam-se as mais convenientes, de aplicação e determina-se uma para projeto. O trabalho compreende ainda, como objeto de estudo, o projeto e a realização de ensaios com um amplificador comutado, sem a preocupação nem objetivo de construir um amplificador de alto desempenho. São apresentados e discutidos as formas de onda e os resultados das medidas realizadas a partir do protótipo do amplificador comutado desenvolvido<br>Abstract: Not informed.<br>Mestrado<br>Mestre em Engenharia Elétrica

El presente trabajo de título tuvo como objetivo crear un sistema embebido capaz de transmitir y recibir audio profesional AES3 a través de Internet tolerando eventuales problemas en la red. La razón de realizar este sistema está fundada en el creciente surgimiento de la tecnología Audio sobre IP que permite transmitir y reproducir audio de alta fidelidad usando redes de computadores. Para desarrollar el sistema fue necesario adquirir previamente todos los conocimientos prácticos y teóricos que lo fundamentan, como son los principios acústicos, los sistemas embebidos, el procesamiento digital, las redes de computadores y el audio sobre IP. Una vez obtenidos los conocimientos, el desarrollo del sistema se llevó a cabo usando una metodología en cascada específica para sistemas embebidos. Esta metodología se basó en seis etapas secuenciales; especificación, diseño, implementación, pruebas, integración y validación. En la especificación se definieron todos los procesos que debían efectuarse dentro del sistema para conseguir su funcionalidad. Luego, en la etapa siguiente se diseñó el sistema con todos los bloques que debía tener para implementar los procesos especificados. En la implementación se llevó a cabo la creación, la codificación y la síntesis de los componentes diseñados, los que se fueron probando a medida que se iban desarrollando. Una vez que las pruebas terminaron de forma exitosa los componentes se integraron para formar el sistema embebido final. Posterior a la integración el sistema embebido se validó en su funcionalidad dando por terminado el proceso de desarrollo. La tecnología empleada para desarrollar el dispositivo fue una FPGA a la cual se le monto un procesador embebido. En la misma FPGA se desarrollaron todos los módulos HDL que realizan el procesamiento de audio del sistema. En cuanto al procesador embebido, éste se utilizó junto a un sistema operativo Linux para ejecutar rutinas programadas de difícil implementación en lógica digital. De esta forma el desarrollo de todo el sistema embebido involucró la creación de hardware electrónico, hardware HDL y software. Gracias al sistemático cumplimiento de los objetivos propuestos la creación del sistema embebido finalizó de forma exitosa. Además, dado que el trabajo fue patrocinado por una empresa chilena especializada en radiodifusión, el sistema desarrollado establece las bases de un primer prototipo industrial fabricado en Chile capaz de transmitir y recibir audio profesional AES3 sobre IP.

This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.

We investigated two design strategies that would allow us to efficiently process audio signals on embedded systems such as mobile phones and portable electronics. In the first strategy, we exploit properties of the human auditory system to process audio signals. We designed a sound enhancement algorithm to make piezoelectric loudspeakers sound "richer" and "fuller," using a combination of bass extension and dynamic range compression. We also developed an audio energy reduction algorithm for loudspeaker power management by suppressing signal energy below the masking threshold. In the second strategy, we use low-power analog circuits to process the signal before digitizing it. We designed an analog front-end for sound detection and implemented it on a field programmable analog array (FPAA). The sound classifier front-end can be used in a wide range of applications because programmable floating-gate transistors are employed to store classifier weights. Moreover, we incorporated a feature selection algorithm to simplify the analog front-end. A machine learning algorithm AdaBoost is used to select the most relevant features for a particular sound detection application. We also designed the circuits to implement the AdaBoost-based analog classifier.

Les microphones sont des capteurs qui permettent à nos systèmes électroniques de prendre connaissance de notre environnement acoustique en fournissant un signal électrique représentatif des vibrations de l’air. Ils sont employés dans la plupart des systèmes multimédia, mais aussi dans les appareils auditifs. Dans l’implant auditif, le microphone se substitue à l’oreille humaine capable de détecter des pressions acoustiques variants de quelque μPa à quelques Pa. Les microphones, sont en général accompagnés d’un circuit électronique spécifique qui permet leur exploitation au coeur d’un système hétérogène. Depuis les toutes premières transductions acoustique-électriques, le microphone a été perfectionné avec la mise en oeuvre de nouveau principes de transduction et l’élaboration de circuit de conditionnement plus performants. Dernièrement, l’introduction de la technologie MEMS (Micro Electro Mechanical Systems) a permis de réaliser des microphones extrêmement compacts et peu couteux. Ces travaux de recherches concernent la réalisation d’un circuit électronique dédié à l’exploitation d’un transducteur M&amp;NEMS (Micro &amp; Nano Electro Mechanical Systems) survenant comme une évolution du MEMS. Pour commencer l’étude, le principe de transduction et l’application du microphone sont étudiés. Les circuits existants sont examinés en détail et adaptés au transducteur M&amp;NEMS. Les résultats potentiels sont discutés et situés dans l’application. Dans un second temps, un circuit de conditionnement spécifique est proposé. Les résultats sont présentés puis le circuit électronique dédié est intégré sur silicium. Les performances des blocs fonctionnels intégrés sont mesurées et présentées<br>Microphones are sensors which allow gauging acoustic environment through an electric representation of vibrations in the air. They can be found in most multimedia equipment and in hearing aids. In this particular application, microphone substitutes a human ear which is able to sense pressure level of sound ranging from a μPa to few Pa. The read-out circuit of microphones converts physical signal from transducer into electronic signals that can be used in any heterogeneous system involving audio processing. Transducers of microphones have known successive generation of improvement. The latest refinement is related to the emergence of MEMS (Micro Electro Mechanical Systems) technology which is suitable to build compact sensor. This thesis explores the design of a readout-circuit using an innovative M&amp;NEMS (Micro &amp; Nano Electro Mechanical Systems) technology derived from MEMS. The thesis is structured beginning with review of existing circuits for M&amp;NEMS microphone. A comparative study is reported considering the proposed technical specifications using simulations and a prototype was realized using discrete components. In the second phase, an innovative circuit was proposed as an ASIC solution targeting M&amp;NEMS technology developed at CEA-LETI. The performance evaluation and the physical measurements of the proposed ASIC are detailed

The thesis describes different between any signal and audio signal from the used amplifier´s quality point of view. There are mentioned ways of origin of distortions and their effect on the audio signal quality. There is also described in detail the principal of operational amplifier, it´s circuit realization and ways to improve the circuit topology in order to reach the best qualities. Choice of parts used for discreet realization of operational amplifier is consulted. Last but not least the thesis contents the practical part, stating the reasons for realization of operational amplifiers from discreet parts and also describing two most commonly used topologies of operational amplifiers. Their discreet version is designed and there are compared the different between the manufacturer’s data and the data measured during the simulation.

Spårledning används inom järnvägen för att lokalisera var tåg befinner sig. Detta examensarbete behandlar en modell av tonfrekvensspårledningar från Alstom. Teoridelen behandlar de båda modellerna DTC – 921 och DTC- 24 medan uträkningarna enbart behandlar den tidigare. Tonfrekvensspårledningar separeras med elektroniska skarvar genom förbindningar i spåret. Den förbindning som examensarbetet undersökt är av typ S-förbindning som idag består av en kopparkabel. Arbetet gick ut på att undersöka hur funktionen är uppbyggd och hur den skulle påverkas vid ett byte av material då koppar är stöldbegärligt. Undersökningar har gjorts på tre olika alternativ: aluminium, järn och safecable från safetrack.  Genom att studera S-förbindningens funktion och hur den agerar med tillhörande tuningbox har materialets eventuella påverkan utvärderats. Med teoretiska uträkningar har parametrarna räknats ut för de olika materialen. För att bekräfta funktionen har simuleringar i Pspice utförts.<br>Track circuits are used to detect where the trains are along the railway. This report contains a study of two models of audio frequency track circuit from Alstom called DTC – 921 and DTC - 24. The calculations made in the result section are made on only DTC-921. The different frequencies between two track circuits are divided by an S-bond. The S-bond is made of cupper which is a material that is theft-prone. The purpose of the project was to investigate the functionality of the S-bond and how  a cable with a different kind of material would affect the function. Three different kinds of materials have been investigated: aluminum, iron and safecable from safetrack.   By studying the function of the S-bond and how it interacts with the tuning box the affect off the different materials have been evaluated. The parameters of the materials have been calculated and the function has been simulated in Pspice.

This work deals with the design of a 10-zones equalizer with optimized frequency characteristics with a spectrum audio analyzer. In this work the problem of processing audio signals using equalization for filtering the interference frequencies, correction of frequency cover signal boost or suppression of the required zones of the audible spectrum are also analyzed. The influence of subjective perception of sound intensity of the audio signals reproduction and its use in working with equalizer is discussed too. The work describes the principles and usage of the audio-analyzer as a tool for the optimization of the audio equalization setting when ensuring the appropriate listening conditions of music reproduction, spoken word, sounds, etc. It also focuses on the signal source for testing audio-chains, their generation and measurement using the audio analyzer. The equalizer equipment, audio-analyzer generator of reference signals equipment and power supply are designed as a single unit.

This master´s thesis deals with a design and simulation of an audio power phono amplifier using vakuum tubes. The frequency response of suggested solution should comply with the norm specified by RIAA. It also describes a vacuum tube basic description and also its advantages for audio applications and principle of usage a magnetodynamic pick-up. Last part contains a design of microprocessor system and power supply.

This work deals with module of the FITkit platform, which makes it able to play sound files like mp3, ogg, etc. The module also adds to FITkit some new peripherals: color LCD display with touch screen and USB interface, by which we can connect flash drive.

在過去的十年裡，隨著便攜式通訊，電腦與消費電子市場的快速發展，以及在超大規模積體電路中，越來越多的功能實現被轉移到數字領域中，這些都引起了人們對模數轉換器研究的極大關注。<br>基於過採樣與量化誤差整形技術，ΣΔ模數轉換器對與類比電路中的非理想特性具有很強的容忍度。然而，爲了優化其在功耗，硅片面積與上市時間等方面的性能，ΣΔ模數轉換器的設計需要對眾多實際問題做出折中考慮。本文在不同的設計層次上提出了一些創新，包括算法，架構及電路設計，從而提升其在通訊，語音與傳感等應用領域中的性能指標。<br>本文第一部份提出的新技術主要解決運用於低中頻無線接收器中開關電容型正交帶通ΣΔ模數轉換器的I/Q通道的不匹配問題。這些I/Q通道的不匹配將導致位於臨近信道的鏡像信號，自鏡像信號及量化噪聲混疊至輸入信道，從而降低模數轉換器的動態範圍。為此，本文提出了一種新的動態單元匹配技術與一種雙線性技術來解決上述問題。同時通過在I/Q信道間複用運算放大器，比較器與數模轉換器，芯片的面積得到了大幅的降低。基於以上技術，在0.18微米CMOS工藝上設計實現了開關電容型正交帶通ΣΔ模數轉換器的測試樣片，其鏡像抑制比可達到73dB，這是迄今為止公開發表論文中報告的最高值。<br>在本文的第二部份，我們關注ΣΔ模數轉換器在音頻領域的應用。其對動態範圍與功耗提出的較高要求為級聯型連續時間ΣΔ模數轉換器帶來了機遇。然而，相比于單環型，級聯型連續時間ΣΔ模數轉換器對於電阻-電容時間常數的偏離及有限的運放低頻增益等非理想特性表現得更加敏感，因為這些不理想因素將影響量化噪聲在模擬與數字路徑中的精確抵消。為此，我們提出了使用脈寬調製技術來對片上的電阻-電容時間常數進行自動調整。基於脈寬調製技術，我們可以使用在離散時間電路中常用的相關雙採樣技術來提高運放的有效低頻增益。同時我們提出了一種有限運放帶寬補償技術來節省芯片的功耗。另外，本文對基於連續時間ΣΔ模數轉換器的脈寬調製技術，相關雙採用技術，反混疊濾波，噪聲與抖動效應等方面均做出了詳盡的仿真與分析。最後我們對一顆基於0.18微米CMOS工藝設計的樣片進行了測試。測試結果表明，採用本文提出的技術可以將ΣΔ模數轉換器的動態範圍提高28dB以上。<br>本文的第三部份展示了一種可用於單端或差分電容傳感器的高精度電容-數字轉換器。在傳統的電容-數字轉換器中，由電容底板開關引入的電荷注入與數字輸出結果及被感知電容的容值有關。當被感知電容的容值變化範圍較大時，這些電荷注入將產生很大的非線性。對此本文提出了一種新的開關控制與校準算法。我們對一顆基於0.18微米CMOS工藝設計的二階電容-數字轉換器樣片進行了測試。測試結果表明，其在0.5毫秒的測試時間內可達到53.2aFrms的精度。同時本文提出的技術可以在0.5pF至3.5pF的較寬電容範圍內，使得電容-數字轉換器在單端電容傳感模式下的線性度（準確度）從9.3位提高至12.3位；在差分電容傳感模式下的線性度（準確度）從10.1位提高至13.3位。最後，本文對連接微機電電容型壓力傳感器和加速度傳感器的實際應用情境進行了測試。<br>The rapid growth of the market for portable, battery operated systems for communications, computer and consumer electronics (3C), and the trend of moving functionality to the digital domain in very large scale integration (VLSI) systems have resulted in an enormously increasing interest in analog-to-digital converter (ADC) design.<br>Combining both oversampling and quantization error shaping techniques, delta sigma (ΔΣ) ADCs achieve a high degree of insensitivity to analog circuit imperfections. Nevertheless, the design of CMOS ΔΣ ADCs involves a number of practical issues and trade-offs that must be taken into account in order to optimize their performance in terms of power consumption, silicon area, and time-to-market deployment. This thesis proposes a number of novel performance-enhancement techniques on different design levels, including algorithm, architecture and circuit level, for ΔΣ ADCs in various application circumstances, such as telecom, audio, sensor, and so on.<br>First, novel techniques are proposed to mitigate I/Q mismatches in switched-capacitor quadrature bandpass Delta-Sigma modulators (DSMs) used in low-IF wireless receivers. The I/Q mismatches result in a nearby channel at the image frequency, the mirrored image of the desired signal around its center frequency (self-image) and the quantization noise to corrupt the desired signal, degrading the dynamic range of the modulator. A dynamic element matching scheme and a bilinear scheme are the proposed solution to reduce all the above-mentioned I/Q mismatch effects. Furthermore, a multiplexing scheme for the sharing of op-amps, quantizers and DACs between the I and Q channels is investigated for smaller chip area. A prototyping DSM was designed and fabricated in a 0.18 ưm CMOS, measuring an image rejection ratio of 73 dB, being the best reported.<br>Second, a pulse-width-modulation (PWM) technique is proposed for on-chip automatic RC time constant tuning for cascaded continuous-time (CT) DSMs for audio application. The demand for high signal-to-noise-plus-distortion ratio (SNDR) and low power brings a wealth of opportunities to the CT DSMs. In CT DSMs, cascading low-order stages provides an effective way to achieve stable high-order modulation. However, compared to CT single-loop modulators, CT cascaded modulators are more sensitive to variation of RC time constant and finite dc gain of the opamps as these nonidealities affect the precise cancellation of the quantization noises between the analog and digital paths. In the CT cascaded modulator presented here, we propose to apply a PWM technique for on-chip automatic RC time constant tuning. The application of PWM in turn enables the use of the correlated double sampling (CDS) technique, which is conventionally confined to discrete-time circuits, to boost the effective dc gain. The PWM further allows the use of a finite-opamp-bandwidth compensation technique for power saving. Analysis on PWM tuning, CDS, anti-aliasing filtering, noise and jitter in the CT modulator are presented and verified with extensive simulations. Measurement results on a prototype CT cascaded 2-2 DSM in a 0.18ưm CMOS show that the proposed techniques can improve the dynamic range (DR), SNDR and spurious-free dynamic range (SFDR) of the modulator by at least 28 dB.<br>Third, a high-precision capacitance-to-digital converter (CDC) is proposed, which can be configured to interface with single-ended or differential capacitive sensors. In the conventional CDC, charge injection from bottom-plate switches depends on the digital output and the value of the sensing capacitor. Nonlinearity is resulted especially when the varying ranging of the sensing capacitor is wide. In this thesis, new switching and calibration schemes are proposed to reduce these charge injection. A prototyping 2nd order CDC employing the proposed techniques is fabricated in a 0.18ưm CMOS process and achieves a 53.2aFrms resolution in a 0.5ms measuring time. The proposed techniques improve the CDC's linearity from 9.3 bits to 12.3 bits in the single-ended sensing mode, and from 10.1 bits to 13.3 bits in the differential sensing mode, with a wide sensing capacitor range from 0.5 to 3.5pF. The CDC is also demonstrated with real-life pressure (single-ended) and acceleration (differential) sensors.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Li, Bing.<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.<br>Includes bibliographical references.<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Abstracts also in Chinese.<br>Abstracts of thesis entitled: --- p.I<br>摘 要 --- p.V<br>Contents --- p.VII<br>List of Figures --- p.XI<br>List of Tables --- p.XVI<br>Acknowledgement --- p.XVII<br>Chapter CHAPTER 1. --- Introduction --- p.1<br>Chapter 1.1 --- Motivation --- p.1<br>Chapter 1.2 --- Original contributions and outline of the thesis --- p.2<br>References --- p.1<br>Chapter CHAPTER 2. --- A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers --- p.3<br>Chapter 2.1 --- Mismatch in Complex Gain Blocks --- p.6<br>Chapter 2.2 --- Mismatches in QBDSM --- p.8<br>Chapter 2.3 --- Proposed High Image-Rejection QBDSM --- p.13<br>Chapter 2.3.1 --- Technique to remove I/Q mismatches in the first complex resonator (for P1 in Fig. 2.6) --- p.13<br>Chapter 2.3.2 --- Technique to remove I/Q mismatches in the Feedback DAC (for B in Fig. 2.6) --- p.19<br>Chapter 2.3.3 --- Technique to remove I/Q mismatches in the Input Coefficient (for A1 in Fig. 2.6) --- p.20<br>Chapter 2.3.4 --- Summary and Simulation Results --- p.27<br>Chapter 2.4 --- I/Q Multiplexing Schemes and Circuit Implementation of the QBDSM --- p.34<br>Chapter 2.5 --- Measurement Results Analysis --- p.40<br>Chapter 2.6 --- Conclusions --- p.47<br>Chapter APPENDIX I: --- I/Q MISMATCHES IN LOW-IF RECEIVERS --- p.48<br>Chapter A. --- I/Q Mismatch in Mixer --- p.48<br>Chapter B. --- I/Q Mismatch in Polyphase Filter --- p.49<br>Chapter C. --- I/Q Mismatch in QBDSM --- p.50<br>Chapter D. --- I/Q Imbalance Analysis for whole receiver --- p.51<br>Chapter APPENDIX II: --- IRR Measurement Method --- p.52<br>References --- p.56<br>Chapter CHAPTER 3. --- A Continuous-time Cascaded Delta-Sigma Modulator with PWM-Based Automatic RC Time Constant Tuning and Correlated Double Sampling --- p.59<br>Chapter 3.1 --- PWM for on-chip RC Time Constant Tuning --- p.61<br>Chapter 3.1.1 --- Integrator Gain Error --- p.64<br>Chapter 3.1.2 --- Automatic Generation of PWM Clock --- p.65<br>Chapter 3.1.3 --- Modulator Architecture --- p.66<br>Chapter 3.1.4 --- Anti-aliasing Filtering --- p.68<br>Chapter 3.1.5 --- Noise Analysis --- p.69<br>Chapter 3.2 --- Proposed SRMC Integrator with CDS --- p.71<br>Chapter 3.2.1 --- Analysis on the opamp gain enhancement --- p.73<br>Chapter 3.2.2 --- Simulation Results --- p.75<br>Chapter 3.3 --- Compensation for Finite-Opamp-Bandwidth-Induced Error --- p.76<br>Chapter 3.3.1 --- Compensation for fininte opamp bandwidth --- p.77<br>Chapter 3.3.2 --- Behavorial Simulation Results --- p.79<br>Chapter 3.4 --- Jitter Analysis --- p.80<br>Chapter 3.4.1 --- Jitter on Rising Edges --- p.81<br>Chapter 3.4.2 --- Duty cycle jitter --- p.84<br>Chapter 3.5 --- Prototyping Modulator Design --- p.85<br>Chapter 3.6 --- Measurement Results --- p.89<br>Chapter 3.7 --- Summary --- p.95<br>References --- p.97<br>Chapter CHAPTER 4. --- A High-Linearity Capacitance to Digital Converter with Techniques Suppressing Charge Injection from Bottom-Plate Switches --- p.105<br>Chapter 4.1 --- Introduction --- p.105<br>Chapter 4.2 --- Proposed CDC Switching and Calibration Schemes --- p.107<br>Chapter 4.2.1 --- Single-Ended Sensing Mode --- p.107<br>Chapter 4.2.2 --- Differential Sensing Mode --- p.111<br>Chapter 4.3 --- Circuit Implementation --- p.114<br>Chapter 4.4 --- Measurement Results --- p.117<br>Chapter 4.5 --- Conclusion --- p.125<br>Chapter APPENDIX: The cross section of NPN transistor in triple-well CMOS process --- p.126<br>References --- p.127<br>Chapter CHAPTER 5. --- Conclusions and future works --- p.129<br>Chapter 5.1 --- Conclusions --- p.129<br>Chapter 5.2 --- Future works --- p.130<br>Chapter APPENDIX: --- A typical CMOS fabrication process flow (1 poly/2 M, twin well CMOS) --- p.131

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance.

碩士<br>中華科技大學<br>電子工程研究所碩士班<br>100<br>This thesis implements an oversampling analog to digital converter(ADC), applied for audio applications, with optimized design on overall circuits. This ADC, using delta sigma modulation technique, can achieve higher resolution with relaxed requirement on analog circuit specifications and less circuit power consumption, compared with other types of ADCs. This thesis presents the design of the core of the ADC, the second-order fully differential delta sigma modulator circuits, in detail. The modulator architecture is designed by behavioral simulation tool, MATLAB, next from a top-down design approach is adopted to determine the optimized values of analog circuits such as switch sizes, minimal input capacitor values, and operational amplifier and quantizer specifications. The AD modulator is designed with TSMC 0.18μm single-poly six-metal process. With sampling frequency of 6.4MHz, oversampling rate of 128, input amplitude of -3 dB of the full swing, the signal to noise ratio (SNR) is simulated as 92 dB from behavioral simulations and as 89 dB from the circuit simulations. Both are equivalent to 15 bits for resolution.

碩士<br>中原大學<br>機械工程研究所<br>98<br>The objective of this research is to design a driving circuitry of power amplifier for application to piezoelectric actuators. The circuit design consists of the Voltage Control Amplifier (VCA) circuit, the class-D amplifier circuit, and the direction selection circuit. The VCA circuit consists of the full-wave rectifier, the square wave generator, and the integrator. The range of control signal of VCA is greater than that of the previous designed audio amplification Integrated Circuit (IC). The power amplifier is designed base upon a class-D amplifier. The pulse width modulation (PWM) of the class-D amplifier is generated by a single chip. LC filter is used and implemented in the Back amplifier so that matching impedance between the piezoelectric capacitance and the circuit becomes easier and more efficient. MOSFET is used for the direction selection circuit to replace TRIAC for the purpose of simplifying the circuit design. Finally, via the experimental test, the design of the driving circuitry is verified to be able to improve accuracy as well as reduce circuit complexity and energy consumption.

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>94<br>The Class-D amplifier, for its high efficiency, has drawn much attentions recently. However, due to its switching operation, the linearity is needed to be improved by comparing with conventional linear amplifiers. Therefore, the negative feedback is applied in this thesis to reduce the harmonic distortion for better linearity. In addition, to avoid the shoot through current due to both power transistors are switched on at the same time, the dead time control is adopted. The over-current protection circuit is also added to prevent the short circuit by poor wire connection. The large current induced by the short circuit would destroy the overall system potentially. 　A single-ended input, differential output Class-D audio amplifier with pulse-width modulation (PWM) is implemented with TSMC 0.35um 2P4M 3.3V/5V Mixed Signal CMOS process. The active area of the amplifier is around 0.99 x 0.93 mm2, and the total area is 1.3 x 1.3 mm2. The simulation results show 90dB of SNR and 82% of efficiency can be achieved. THD is around 0.045% while Class-D amplifier deliver 240mW.

博士<br>國立成功大學<br>電機工程學系碩博士班<br>96<br>The system design and circuit implementation of digital-input class-D audio amplifiers (digital amplifiers) are presented in this dissertation. Due to the high power efficiency of class-D amplifiers, conventional class-A and class-AB amplifiers are gradually being replaced. Digital amplifiers that can achieve high power efficiency and can directly amplify digital audio signals will eventually become the design trend of audio amplifiers. In this dissertation, the design of delta-sigma modulators (DSMs), power MOSFET drivers, and the over-current protection for a 5.1-channel single-chip digital amplifier with 100W root-mean-square (RMS) total output power is presented. To the best of our knowledge, it is the first highly integrated 5.1-channel single-chip digital amplifier. In addition, this dissertation proposes a novel DSM design method to increase the linear output power for future digital amplifier designs. In the 5.1-channel digital amplifier, DSMs with a low over-sampling ratio (OSR) are used in circuits that convert pulse-code-modulation signals into pulse-width-modulation signals. A modified DSM structure is adopted to avoid the degradation of signal-to-noise ratio (SNR) and the maximum stable input magnitude. The improvement is especially obvious under low OSR conditions. For large power MOSFET drivers, driver circuits with unequal slopes of rising and falling edges are proposed to reduce the imperfection of power stage outputs. To protect this amplifier from short circuits and improper loads, a new over-current protection circuit with high supply-noise rejection and low sensitivity to parameter variation of devices is proposed. This single-chip amplifier is fabricated with a 0.35 um 1P3M 3.3/18-V C/D-MOS process. The total chip area is about 50 mm2. Both peak SNR and dynamic range are 84 dB with an A-weighted function compared to the output noise at full scale input. Both peak SNR and dynamic range are 92 dB compared to the output noise at zero input. The RMS output power of five normal channels on five 8 ohm loads and a subwoofer channel on a 3 ohm load are 13WX5 and 35W, respectively. The total RMS output power is 100W @ a 0.3 % total-harmonic-distortion-plus-noise (THD + N) ratio. The measured minimum THD + N ratio is 0.045 %. The measured maximum power efficiency is 88 %. A 128-pin QFP package with an exposed thermal pad is used. With high power efficiency and the exposed thermal pad, no extra heatsinks are necessary. A low cost 5.1-channel high power amplifier system with a small volume is possible. This is a big design breakthrough in high power 5.1-channel Hi-Fi audio amplifier systems. In addition to the aforementioned circuit implementations, this dissertation proposes a novel method for increasing linear output power under the same VDD and loads. This method can save power module costs and can be used in future designs. In digital amplifiers, the linear output power range is usually dominated by DSMs. In a conventional single-stage high-order DSM, part of its root locus is outside the unit circle so the stable input range is limited. A new method is proposed for designing a DSM with its root locus inside the unit circle (RLiUC DSM). The RLiUC DSM can maintain a high signal-to-noise plus distortion ratio (SNDR) at the full scale input magnitude. An RLiUC DSM designed using the proposed method with full scale stable input magnitude and a conventional DSM designed with high peak SNDR are combined to extend the linear output power range of digital amplifiers. Methods to implement this combination are also presented. Compared to the digital amplifiers with conventional DSMs, the maximum linear output power is increased by 20 %. Compared to the state-of-the-art design, the output power region which has very low THD + N ratio is extended 160 % by the proposed method.

碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>99<br>This paper presents a robust power supply circuit for multilevel converter of class-D audio amplifier. Based on pulse-width-modulation buck converter, we develop a sliding-switching technique comprises a loading monitor and a voltage level controller. The loading monitor continuously checks the internal control signal of multilevel class-D amplifier to identify whether the loading is light or heavy. The voltage level controller then feedbacks corresponding voltage level to modulate pulse width of control signal in buck converter and adjust supplying current and power delivery. The proposed sliding-switching technique stabilizes the voltage variation of power supply under the situation of alternating light and heavy loading and consequently enhances the performance of total-harmonic-distortion. To demonstrate the practicability, an integrated multilevel class-D amplifier with proposed power supply circuit is implemented under TSMC 0.35μm process. The simulation results show that the total-harmonic-distortion is improved more than 11dB without increasing power consumption of circuit.

碩士<br>國立交通大學<br>電機學院IC設計產業專班<br>97<br>In this thesis, we use inverter amplifiers to replace fully differential ones to implement a high dynamic range fully differential sigma delta modulator. Because the electron stethoscope and hearing aids are portable and using batteries to provide supply voltage, low-voltage and low power consumption are the key design consideration. In our structure, we use tri-state inverter amplifiers and four nonoverlapping phases to deal with the differential input signals. A sample and hold circuit used to separate the differential output signal of the integrator. Finally, we use a dynamic comparator and latch to compose the quantizer. This chip is designed in TSMC 0.18μm CMOS process, and the chip area is about 0.35mm2. Our design is in the biomedical audio frequency, from 20Hz to 20 kHz. The power supply voltage is 1.2V, and the sampling frequency is 2.56MHz. The sigma delta modulator has a SNR of 87dB, a SNDR of 81dB, a dynamic range of 93dB. It consumes 144.36μW of power.

碩士<br>國立交通大學<br>電機與控制工程系<br>87<br>In this thesis, we design the peripheral circuit of Wavelet-Based audio process system, with the personal computer, FPGA (Field Programmable Gate Array), and microcontroller AT89C51. We sample stereo audio signals , by CODEC , and send the signals to the part of DWT (Discrete Wavelet Transform). Then, we save the transformed data to SRAM buffers, and wait for the host to read data. Finally, we save data in Hard-disk, that can be read and write as we wish. Hardware description language is the new trend in IC design. In this thesis, we use VHDL ( Very High Speed ICs Hardware Description Language ) to design the controller of CODEC、SRAM and EPP transmission mode.

Due to the lack of feedback networks, digital class D amplifiers operating in open loop typically have inferior performance when compared to analog class D amplifiers in closed loop configuration. This thesis presents an integrated distortion suppression circuit design for digital class D amplifiers, which forms a feedback loop around the output stage. This circuit suppresses the output stage distortion and noise by equalizing the modulator effective duty ratio and the output stage effective duty ratio. The suppression circuit is integrated with the class D modulator. An integrated class D amplifier output stage is implemented separately using a 0.35μm HV-CMOS technology. Experimental results confirm that the closed loop PSRR is improved by 15dB. The THD+N value is reduced by a factor of 2 to 30. The minimum THD+N is 0.03%, which is among the state of the art class D amplifiers.

碩士<br>國立交通大學<br>電機與控制工程系所<br>96<br>IC processing technologies have a great improvement recently. There are more transistors per unit area. Therefore, applications are more and more extensive. Battery device products for audio applications, such as hearing aids, stethoscope, etc, hope circuits to operate at 1ow voltage, low area, and low power. In this thesis, a low-voltage low-area low-power digital automatic gain control (AGC) with a sigma-delta modulator for audio front-end circuit is realized. This thesis utilizes a direct feedback at the sigma-delta modulator output to design the digital AGC. It does not go through a decimation filter. Thus it decreases the area, power consumption, and latency of the AGC loop. To decrease the power consumption of the modulator, inverter operational transconductance amplifiers (OTA) are used and a pure dynamic comparator is designed. To rectifier a bit stream of the modulator output, a bit-stream rectifier is presented. In terms of digital to analog converter, a low area recurring DAC is presented. The proposed circuit is designed in TSMC 1P6M 0.18 m CMOS process. Its active die area is 0.347um*0.429um. The signal bandwidth is designed in an audio bandwidth from 250Hz to 10 kHz, and the resolution is 12bit. The dynamic range(DR) is 87dB. The supply voltage is 1.0V. The total power consumption of the proposed circuit is 42.3 μW.

碩士<br>中原大學<br>電機工程研究所<br>100<br>The audio frequency(600Hz) signal is transmitted by the signalling system on the high speed track circuit, which can specify whether the track circuit being occupied. If any, the next train can not enter the occupied track circuit(about one kilometer) to prevent from the head-on collision. When the rail fastening assembly(RFA) is polluted badly or is covered with heavy rain, the audio frequency signal may leak out of the RFA as to the signalling system making the incorrect judgement that the track circuit were occupied. This thesis intends to simulate the leakage of audio frequency signal from the RFA and analyze the leakage route and the audio frequency voltage and current on the track circuit with comparison to the measurement results. Two models are built in this study. The first model is used for simulating the signal voltage and current in whole track circuit; the second model for simulating the potential distribution and the leakage current of one RFA. We also design the data exchange interface between the two models. Then the track circuit model uses the RFA model results to analyze the leakage resistance, based on which to evaluate the whole track circuit voltage and leakage current. The developed models to analyze the audio frequency signal’s leakage of high speed track circuit, can be an important evaluation tool to prevent the leakage of audio frequency signal from the track circuit.

碩士<br>國立成功大學<br>電機工程學系<br>88<br>This thesis describes the design of a 2.5V 1.5GHz CMOS RF receiver front-end for Digital Audio Broadcasting(DAB) system. The receiver front-end combines a balanced low noise amplifer (LNA), quadrature downconversion mixers, an LO quadrature generator , LO input buffers, IF gain stages , a polyphase filter, second gain stages, and output buffers all in one single CMOS IC. Using polyphase image-reject architecture, CMOS RF circuits, and on-chip filtering, the receiver is fully integrated and eliminates off-chip SAW filters often seen in heterodyne receivers. Down to the signal path of this front-end design, the low noise amplifier is a differential, cascode common-source with inductive source degeneration type. The planar spiral inductor used in LNA boost the gain performance and enable low voltage RF circuits to be monolithically integrated. Combined with the current-reused architecture and power-constrained noise optimization techniques, the LNA can achieve 29.4dB voltage gain, -29.2dB S11, 25mW power consumption, and 2.38 dB NF, obtained from simulation. The down-conversion mixer employs a double balanced Gilbert Cell type mixer with common mode feedback circuit. Simulation shows it can achieve 7.5dB conversion gain and -5dBV IIP3. This RF receiver front-end is designed in TSMC 0.25$\mu$m single-poly, five-metal mixed-signal CMOS process, operated with 2.5V power supply. The spiral inductor and MOS RF model, from the TSMC process, are adopted in the receiver design.

碩士<br>淡江大學<br>電機工程學系碩士在職專班<br>100<br>Audio power amplifiers play an important role in the audio system.Compared by power efficiency,Class-D power amplifiers have better performance.The theoretical maximum efficiency of Class-D designs is 100%,and over 90% is attainable in practice. Use the self-oscillation Class D audio power amplifiers IC chip&apos;&apos;s internal circuit is designed to be used on dual or several multi independent audio channel, and when dual audio channel transmit output power,PWM signal osc frequency is nonsynchronous and result the Beat Frequency. If the difference of sound frequency is within the range for ear&apos;&apos;s frequency, IC work tends to occur the situation of the Beat Frequency when there is no sound source&apos;&apos;s signal output at this time. Although the sound is weak, people can still hear it clearly and which will cause persecution when using IC.In order to solve such problem, this theory is aimed at the problem of the Beat Frequency which is caused from dual audio channel Class D and designs the applied test circuit for discuss and study.

碩士<br>國立交通大學<br>電機學院電信學程<br>102<br>This ground line of the earphone audio circuit also doubles as the FM antenna of a smart phone. Its use, between, was found to caucal the phone to fail the radiaed and conducted susceptibility (RS/CS) tests per EN301489 standard in the frequency range 8MHz~108MHz. It was found that the ferrite bead used to connect the earphone to PCB ground should be replaced by an ofen bead with more appropriate DC resistance and RF impedance profile. A series of experiments were conducted to pick beads tha enable the phone to pass the RS and CS tests, while not compromise its FM neception, audio, and radiated emission (RE) performance.

碩士<br>長庚大學<br>電子工程學系<br>101<br>This thesis adopts a variety of amplifier structures in textbooks to design and construct a multi-stage, high fidelity audio amplifier. After the initial framework project plan has been done, we used the commercial circuit simulators ORCAD and Advance design system (ADS) to verify the preliminary amplifier design and modify the circuit operating points of transistors in order to obtain the desired amplifier’s characteristics such as high efficiency, low distortion and the best temperature stability. After the computer-aided design simulation of the overall amplifier is completed we assemble the practical components on the PCB according to the design that is obtained from the simulation to fabricate a prototype of the audio amplifier. And then, we go through the several measurements to make sure the properties of the amplifier. The measurement results show the practical amplifier do satisfied the required specifications and very close to the computer simulation results. Eventually, the amplifier is practically applied in the audio system for ensuring its performance. The overall amplifier circuit architecture includes three stage amplifiers. The first stage is an active-load differential amplifier that mainly uses transistors as active loading ,which can provide an effective loading close to-open-circuit and to raise the voltage gain and avoid the traditional bipolar transistor class A amplifier design that cannot uses high impedance loading for the consideration of the requirement of the appropriate operation point. The second stage of the amplifier is a single-ended amplifier that is still use a current mirror as the active load to enhance the voltage gain. The third stage design is a power stage, so that we should take the power efficiency and the temperature effects into consideration. Usually, a high efficiency class B amplifier structure is selected. However, the class B amplifier must consider the effect of crossover distortion, therefore the complementary feature with Class AB biasing condition are chosen as the final feature for final stage of the audio amplifier. So that this approach can provide better power amplifier efficiency, and eliminate the crossover distortion. While transistors are processing for providing high power output, their semi-conductor junction temperature will rise and affect the voltage-current characteristics of the transistor, and the vicious cycle can even causes the permanent damage of the transistors. So we intend to adopt a manner that can provide a negative feedback to compensate temperature effect in the practical circuit. The temperature compensation circuit is confirmed their feasibility in the computer simulation and then we could observe the improvement of the temperature stability in the practical measurement results. The good properties of the experimental prototype shown in measurement results could show the promise the amplifier in the future commodity applications.

碩士<br>國立成功大學<br>電機工程學系碩博士班<br>94<br>An audio receiver is essential in mostly audio systems. It has two fundamental components to cope with audio signals. One is a front-end clock and data recovery (CDR) circuit and the other is a back-end decoder. The frond-end CDR circuit is used to extract the clock and retime the data from the input data. The back-end decoder is used to decode the bitstreams of the retimed data generated by the font-end CDR circuit into stereo audio streams or 5.1-channel audio streams. Then speakers or headphones play sound or music according to these audio streams. Moreover, digital interfaces such as S/PDIF are adopted in audio transceivers in order to improve the anti-noise capability of an audio signal during transmission. In this thesis, a continuous-rate CDR architecture satisfying all S/PDIF audio applications is proposed. The proposed CDR architecture adds an extra loop into the traditional CDR circuit to support a wide and continuous range of data rates, 128 times sampling frequencies, from 4.096Mb/s to 24.576Mb/s. It can also achieve the frequency acquisition automatically without the reference clock or the microcontroller. The whole performance of the CDR circuit can be enhanced greatly due to its architecture. The CDR circuit has been fabricated in a TSMC 0.35μm 2P4M mixed signal CMOS process. Its total area is about 1.73mm2. The measured root-mean-square jitters and the measured peak-to- peak jitters of output clocks are all under 13.53ps and 91ps respectively over all the input data rates. All measured bit error rates are less than 10-10 for a random S/PDIF data. The maximum power consumption is 10.79mW from a 3.3V supply when receiving a 25Mb/s S/PDIF data. In addition to the font-end CDR circuit, the back-end decoder designed in this thesis can provide nine different output modes satisfying the serial audio interface formats. This decoder can also automatically detect a change in the input data rate and demand that the front-end CDR circuit reacquire the new data rate. The decoder is burned into the Alter FLEX10KE emulation board for emulation and verification.

碩士<br>靜宜大學<br>大眾傳播學系<br>104<br>Music in the human society has been existed for so long. With the development of audiovisual technology, music can not only be appreciated from the form of live performance, but it can also be recorded and preserved as a cultural heritage. However, under the impact of digital technology, music industry, nowadays, has faced the challenge from illegal piracy and downloading. Making records and selling CDs cannot guarantee profits for artists and record companies. As a result, live concert becomes of a savior for music industry. During the live performance, audience is not just "listening to music", all the visual and lighting effects combined can offer audience unique sensory stimulation, which cannot be experienced from listening to CDs or music files. Walter Benjamin has proposed the "authenticity" concept. He states that traditional art performance has a unique "Aura", which cannot be copied or substituted. Live performance is the art of “presence in time and space”. Therefore, this study uses music texts from Mayday as the case studied. By employing the concept of “circuit of culture”, proposed by Stuart Hall and Paul du Gay, along with the concept of “authenticity”, this thesis tries to analyze pop music industry in Taiwan, with focus on the changes of music production, music merchandise and the cultural perspective associated with the flourish of live concert performance and live concert movie in the era of media digitalization.