Artículos de revistas sobre el tema "ANALYSIS OF CMOS"
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LIAO, HAIFANG, WAYNE WEI-MING DAI y RUI WANG. "A NEW CMOS DRIVER MODEL FOR TRANSIENT ANALYSIS AND POWER DISSIPATION ANALYSIS". International Journal of High Speed Electronics and Systems 07, n.º 02 (junio de 1996): 269–85. http://dx.doi.org/10.1142/s0129156496000116.
Texto completoCheyette, Oren. "OAS Analysis for CMOs". Journal of Portfolio Management 20, n.º 4 (31 de julio de 1994): 53–66. http://dx.doi.org/10.3905/jpm.1994.409485.
Texto completoJomaah, Jalal, Majida Fadlallah y Gerard Ghibaudo. "Low Frequency Noise Analysis in Advanced CMOS Devices". Advanced Materials Research 324 (agosto de 2011): 441–44. http://dx.doi.org/10.4028/www.scientific.net/amr.324.441.
Texto completoSheikh, Shireen T. "Comparative Analysis of CMOS OTA". IOSR journal of VLSI and Signal Processing 1, n.º 3 (2012): 01–05. http://dx.doi.org/10.9790/4200-0130105.
Texto completoSchmitt-Landsiedel, D. "Yield Analysis of CMOS Ics". Solid State Phenomena 57-58 (julio de 1997): 327–36. http://dx.doi.org/10.4028/www.scientific.net/ssp.57-58.327.
Texto completoDimitrijev, S. y N. Stojadinović. "Analysis of CMOS transistor instabilities". Solid-State Electronics 30, n.º 10 (octubre de 1987): 991–1003. http://dx.doi.org/10.1016/0038-1101(87)90090-6.
Texto completoGajare, Milind y Shedge D.K. "CMOS Trans Conductance based Instrumentation Amplifier for Various Biomedical Signal Analysis". NeuroQuantology 20, n.º 5 (30 de abril de 2022): 53–60. http://dx.doi.org/10.14704/nq.2022.20.5.nq22148.
Texto completoYao, Hong Tao, Zi Qiang Wang, Yuan Bao Gu y Zhen Gang Jiang. "Analysis of Black Level Calibration Algorithm for CIS". Applied Mechanics and Materials 599-601 (agosto de 2014): 1397–402. http://dx.doi.org/10.4028/www.scientific.net/amm.599-601.1397.
Texto completoPrajapati, Pankaj P., Anilkumar J. Kshatriya, Sureshbhai L. Bharvad y Abhay B. Upadhyay. "Performance analysis of CMOS based analog circuit design with PVR variation". Bulletin of Electrical Engineering and Informatics 12, n.º 1 (1 de febrero de 2023): 141–48. http://dx.doi.org/10.11591/eei.v12i1.4357.
Texto completoCho, Won-ho y Ki-sang Hong. "Affine Motion Based CMOS Distortion Analysis and CMOS Digital Image Stabilization". IEEE Transactions on Consumer Electronics 53, n.º 3 (agosto de 2007): 833–41. http://dx.doi.org/10.1109/tce.2007.4341553.
Texto completoXiong, Qi, Shao Hua Zhou y Jiang Ping Zeng. "The Analysis of Device Model in CMOS Integrated Temperature Sensor". Advanced Materials Research 986-987 (julio de 2014): 1600–1605. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1600.
Texto completoProf. Nikhil Surkar. "Design and Analysis of Optimized Fin-FETs". International Journal of New Practices in Management and Engineering 4, n.º 04 (31 de diciembre de 2015): 01–06. http://dx.doi.org/10.17762/ijnpme.v4i04.39.
Texto completoMun, Hye Jin, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae y In Man Kang. "Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary". Journal of Nanoscience and Nanotechnology 20, n.º 11 (1 de noviembre de 2020): 6616–21. http://dx.doi.org/10.1166/jnn.2020.18769.
Texto completoLe, H. P., A. Zayegh y J. Singh. "Performance analysis of optimised CMOS comparator". Electronics Letters 39, n.º 11 (2003): 833. http://dx.doi.org/10.1049/el:20030546.
Texto completoZhao, Zhixing, Sebastian Magierowski y Leonid Belostotski. "Linearity Analysis of CMOS Parametric Upconverters". IEEE Access 8 (2020): 190906–21. http://dx.doi.org/10.1109/access.2020.3032397.
Texto completoVerhelst, M. y B. Murmann. "Area scaling analysis of CMOS ADCs". Electronics Letters 48, n.º 6 (2012): 314. http://dx.doi.org/10.1049/el.2012.0253.
Texto completoKress, Rainer, Elmar Melcher, Reiner Hartenstein y Michel Dana. "CMOS interconnect modelling for timing analysis". Microprocessing and Microprogramming 37, n.º 1-5 (enero de 1993): 7–10. http://dx.doi.org/10.1016/0165-6074(93)90004-5.
Texto completobin Rosly, Hasrul Nisham, Mamun bin Ibne Reaz, Noorfazila Kamal y Fazida Hanim Hashim. "Design and Analysis of CMOS Linear Feedback Shift Registers for Low Power Application". Applied Mechanics and Materials 833 (abril de 2016): 111–18. http://dx.doi.org/10.4028/www.scientific.net/amm.833.111.
Texto completoSharma, Prakash. "Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology". International Journal for Research in Applied Science and Engineering Technology 10, n.º 1 (31 de enero de 2022): 732–37. http://dx.doi.org/10.22214/ijraset.2022.39908.
Texto completoLee, Sangho y Edwin W. Greeneich. "CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization". VLSI Design 15, n.º 3 (1 de enero de 2002): 619–28. http://dx.doi.org/10.1080/1065514021000012237.
Texto completoPatel, Ambresh y Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits". SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, n.º 01 (30 de enero de 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
Texto completoLi, Ming Jing, Yu Bing Dong y Guang Liang Cheng. "Multiple CMOS Intersection Measuring System Modeling and Analysis". Advanced Materials Research 614-615 (diciembre de 2012): 1299–302. http://dx.doi.org/10.4028/www.scientific.net/amr.614-615.1299.
Texto completoZhang, Yichen. "Comparative analysis of logic gates based on CMOS, FINFET, and CNFET: Characteristics and simulation insights". Theoretical and Natural Science 26, n.º 1 (20 de diciembre de 2023): 44–53. http://dx.doi.org/10.54254/2753-8818/26/20241011.
Texto completoAnusha, N. y T. Sasilatha. "Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies". Journal of Computational and Theoretical Nanoscience 13, n.º 10 (1 de octubre de 2016): 6999–7008. http://dx.doi.org/10.1166/jctn.2016.5660.
Texto completoChen, Jiahao. "Integrated circuit design based on CMOS technology principle and its application in GPU". Theoretical and Natural Science 12, n.º 1 (17 de noviembre de 2023): 141–46. http://dx.doi.org/10.54254/2753-8818/12/20230454.
Texto completoPanwar, Shikha, Mayuresh Piske y Aatreya Vivek Madgula. "Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits". VLSI Design 2014 (15 de julio de 2014): 1–5. http://dx.doi.org/10.1155/2014/380362.
Texto completoKAKKAR, VIPAN. "PERFORMANCE ANALYSIS OF CMOS FOR HIGH SPEED MIXED SIGNAL CIRCUITS". Journal of Circuits, Systems and Computers 20, n.º 06 (octubre de 2011): 1067–74. http://dx.doi.org/10.1142/s0218126611007761.
Texto completoR.Rajprabu, R. Rajprabu. "Performance Analysis of CMOS and FinFET Logic". IOSR journal of VLSI and Signal Processing 2, n.º 1 (2013): 01–06. http://dx.doi.org/10.9790/4200-0210106.
Texto completoZHANG Jing-shui, 张镜水, 孔令琴 KONG Lingqin, 董立泉 DONG Li-quan y 赵跃进 ZHAO Yue-jin. "Terahertz CMOS transistor model and experimental analysis". Optics and Precision Engineering 25, n.º 12 (2017): 3128–36. http://dx.doi.org/10.3788/ope.20172512.3128.
Texto completoWang, Fei y Albert Theuwissen. "Linearity analysis of a CMOS image sensor". Electronic Imaging 2017, n.º 11 (29 de enero de 2017): 84–90. http://dx.doi.org/10.2352/issn.2470-1173.2017.11.imse-191.
Texto completoSanghoon Kang, Byounggi Choi y Bumman Kim. "Linearity analysis of CMOS for RF application". IEEE Transactions on Microwave Theory and Techniques 51, n.º 3 (marzo de 2003): 972–77. http://dx.doi.org/10.1109/tmtt.2003.808709.
Texto completoPinto, M. R. y R. W. Dutton. "Accurate trigger condition analysis for CMOS latchup". IEEE Electron Device Letters 6, n.º 2 (febrero de 1985): 100–102. http://dx.doi.org/10.1109/edl.1985.26057.
Texto completoRangavajjhala, V. S., B. L. Bhuva y S. E. Kerns. "Statistical degradation analysis of digital CMOS IC's". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, n.º 6 (junio de 1993): 837–44. http://dx.doi.org/10.1109/43.229759.
Texto completoChao, H. J. y C. A. Johnston. "Behavior analysis of CMOS D flip-flops". IEEE Journal of Solid-State Circuits 24, n.º 5 (octubre de 1989): 1454–58. http://dx.doi.org/10.1109/jssc.1989.572637.
Texto completoDogan, Hakan, Robert G. Meyer y Ali M. Niknejad. "Analysis and Design of RF CMOS Attenuators". IEEE Journal of Solid-State Circuits 43, n.º 10 (octubre de 2008): 2269–83. http://dx.doi.org/10.1109/jssc.2008.2004325.
Texto completoFinvers, I. G. y I. M. Filanovsky. "Analysis of a source-coupled CMOS multivibrator". IEEE Transactions on Circuits and Systems 35, n.º 9 (1988): 1182–85. http://dx.doi.org/10.1109/31.7584.
Texto completoSamanta, Jagannath y Bishnu Prasad De. "Delay analysis of UDSM CMOS VLSI circuits". Procedia Engineering 30 (2012): 135–43. http://dx.doi.org/10.1016/j.proeng.2012.01.844.
Texto completoPittet, P., J. M. Galvan, G. N. Lu, L. J. Blum y B. D. Leca-Bouvier. "CMOS LIF detection system for capillary analysis". Sensors and Actuators B: Chemical 97, n.º 2-3 (febrero de 2004): 355–61. http://dx.doi.org/10.1016/j.snb.2003.09.021.
Texto completoSharroush, Sherif M. "Analysis of the subthreshold CMOS logic inverter". Ain Shams Engineering Journal 9, n.º 4 (diciembre de 2018): 1001–17. http://dx.doi.org/10.1016/j.asej.2016.05.005.
Texto completoKim, Kyung Ki. "Analysis of Electromigration in Nanoscale CMOS Circuits". Journal of the Korea Industrial Information Systems Research 18, n.º 1 (28 de febrero de 2013): 19–24. http://dx.doi.org/10.9723/jksiis.2013.18.1.019.
Texto completoShan, Yu, Zhang Dingkang y Huang Chang. "0.8μm LDD CMOS reliability experiments and analysis". Journal of Electronics (China) 12, n.º 1 (enero de 1995): 84–89. http://dx.doi.org/10.1007/bf02684572.
Texto completoG, Minikumari. "Performance Analysis of Deep Sub Micron Two Quadrant Analog Divider Circuits". International Journal for Research in Applied Science and Engineering Technology 11, n.º 5 (31 de mayo de 2023): 663–68. http://dx.doi.org/10.22214/ijraset.2023.51561.
Texto completo., Gudala Konica y Sreenivasulu Mamilla . "Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling". Volume 4,Issue 5,2018 4, n.º 5 (5 de enero de 2019): 575–79. http://dx.doi.org/10.30799/jnst.187.18040530.
Texto completoJeong, Sang-Hun, Nam-Ho Lee, Min-Woong Lee y Seong-Ik Cho. "Analysis of Radiation Effects in CMOS 0.18um Process Unit Devices". Transactions of The Korean Institute of Electrical Engineers 66, n.º 3 (1 de marzo de 2017): 540–44. http://dx.doi.org/10.5370/kiee.2017.66.3.540.
Texto completoEsonu, M. O., D. Al-Khalili y C. Rozon. "Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits". VLSI Design 1, n.º 4 (1 de enero de 1994): 261–76. http://dx.doi.org/10.1155/1994/70696.
Texto completoKamde, Shilpa, Jitesh Shinde, Sanjay Badjate y Pratik Hajare. "Comparative Analysis Domino Logic Based Techniques For VLSI Circuit". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, n.º 8 (21 de marzo de 2014): 3803–8. http://dx.doi.org/10.24297/ijct.v12i8.2998.
Texto completoMačaitis, Vytautas y Romualdas Navickas. "Analysis of Main LC-VCO Parameters for Multistandard Tranceivers". Mokslas - Lietuvos ateitis 9, n.º 3 (4 de julio de 2017): 324–28. http://dx.doi.org/10.3846/mla.2017.1043.
Texto completoWagaj, S. C. y S. C. Patil. "Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor". International Journal of Engineering and Advanced Technology 10, n.º 6 (30 de agosto de 2021): 1–10. http://dx.doi.org/10.35940/ijeat.e2576.0810621.
Texto completoHuang, Peihao. "Design and optimization of CMOS layout structure for improved semiconductor device performance". Journal of Physics: Conference Series 2649, n.º 1 (1 de noviembre de 2023): 012040. http://dx.doi.org/10.1088/1742-6596/2649/1/012040.
Texto completoLazzaz, Abdelaziz, Khaled Bousbahi y Mustapha Ghamnia. "Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM,7 NM and 5 NM node technologies". Facta universitatis - series: Electronics and Energetics 36, n.º 1 (2023): 1–16. http://dx.doi.org/10.2298/fuee2301001l.
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