Tesis sobre el tema "Analogue sensor"
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Ahmed, M. "A plant analogue sensor for irrigation scheduling". Thesis, University of Newcastle Upon Tyne, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.378303.
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Nairac, Alexandre L. "An analogue visual velocity sensor for robot navigation". Thesis, University of Oxford, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.339084.
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Jafaripanah, Mehdi. "Analogue adaptive techniques for dynamic sensor frequency compensation". Thesis, University of Southampton, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.419164.
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Coulson, Michael P. "Precision analogue techniques for a silicon on glass ambient light sensor". Thesis, University of Oxford, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.711607.
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Hamilton, Tony. "An analogue model for the simulation of earthquake rupture and stick-slip". Thesis, University of Ulster, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.326325.
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Kitchen, Alistair J. "CMOS digital pixel sensor array with time domain analogue to digital conversion". Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/765.
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This thesis presents a digital pixel sensor array, which is the first stage of an ongoing project to produce a CMOS image sensor with on-chip image processing. The analogue to digital conversion is performed at the pixel level, with the result stored in pixel memory. This architecture allows fast, reliable access to the image data and simplifies the integration of the image array and the processing logic. Each pixel contains a photodiode sensor, a comparator, memory and addressing logic. The photodiode sensor operates in integrating mode, where the photodiode junction capacitance is first charged to an initial voltage, and then discharged by the photodiode leakage current, which is comprised mainly of optically generated carriers. The analogue to digital conversion is performed by measuring the time taken for the photodiode cathode voltage to fall from its initial voltage, to the comparator reference voltage. This triggers the 8-bit pixel memory, which stores a data value representative of the time. The trigger signal also resets the photodiode, which conserves the charge stored in the junction capacitance, and also prevents blooming. An on-chip control circuit generates the digital data that is distributed globally to the array. The control circuit compensates for the inverse relationship between the integration time and the photocurrent by adjusting the data clock timing. The period of the data clock is increased at the same rate as the integration time, resulting in a linear relationship between the digital data and the photocurrent. The design is realised as a 64 x 64 pixel array, manufactured in O.35µm 3.3 V CMOS technology. Each pixel occupies an area of 45µm x 45µm with a 12.3% fill factor, and the entire pixel array and control circuit measures 3.7mm x 3.9mm. Experimental results confirm the operation of the digital pixel, and the linearising control circuit. The digital pixel has a dynamic range of 85dB, and can be adapted to different lighting conditions by varying a single clock frequency. The data captured by the array can be randomly accessed, and is read from the array nondestructivcly.
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Choubey, Bhaskar. "On wide dynamic range logarithmic CMOS image sensors". Thesis, University of Oxford, 2006. http://ora.ox.ac.uk/objects/uuid:f2d8ea6d-6b71-45bf-80dc-7dadb1421e3b.
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Logarithmic sensors are capable of capturing the wide dynamic range of intensities available in nature with minimum number of bits and post-processing required. A simple circuit able to perform logarithmic capture is one utilising a MOS device in weak inversion. However, the output of this pixel is crippled due to fixed pattern noise. Technique proposed to reduce this noise fail to produce high quality images on account of unaccounted high gain variations in the pixel. An electronic calibration technique is proposed which is capable of reducing both multiplicative as well as additive FPN. Contrast properties matching that of human eye are reported from these sensors. With reduced FPN, the pixel performance at low intensities becomes concerning. In these regions, the high leakage current of the CMOS process affects the logarithmic pixel. To reduce this current, two different techniques using a modified circuit and another with modified layout are tested. The layout technique is observed to reduce the leakage current. In addition, this layout can be used to linearise the output of logarithmic pixel in low light regions. The unique linear response at low light and logarithmic pixel at high light is further investigated. A new model based on the device physics is derived to represent this response. The fixed pattern noise profile is also investigated. An intelligent iterative scheme is proposed and verified to extract the photocurrent flowing in the pixel and correct the fixed pattern noise utilising the new model. Future research ideas leading to better designs of logarithmic pixels and post-processing of these signals are proposed at the end of the thesis.
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Lefebvre, Arnaud. "Contribution à l'amélioration de la testabilité et du diagnostic de systèmes complexes : application aux systèmes avioniques". Grenoble 1, 2009. https://theses.hal.science/tel-00555683.
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L'objet des travaux de cette thèse est de proposer de nouveaux processus de définition de tests (testabilité), de nouvelles méthodes de tests, ainsi que de nouvelles méthodes d'interprétation des tests (diagnostic). Ces travaux ont été menés dans le cadre de l'aéronautique et ont porté dans un premier temps sur l'identification des besoins en diagnostic des hélicoptères. Les problématiques liées au test et au diagnostic des hélicoptères portaient sur : - La non-détection de certaines défaillances - L'occurrence de nombreuses fausses alarmes - L'ambiguïté de localisation de défaillances Dans un premier temps nous avons réalisé l'état de l'art des recherches en diagnostic, ceci afin de sélectionner les technologies et méthodologies permettant de répondre aux problématiques identifiées. Les technologies candidates ont ensuite été architecturées afin de proposer un traitement intégré permettant de répondre à l'ensemble des besoins identifiés. Ainsi nous avons travaillé sur les méthodologies de définition du test, aux moyens d'outils de simulation de la testabilité. Nous avons aussi défini de nouvelles méthodes de test permettant de déterminer l'état de capteurs analogiques aux moyens d'algorithmes basés sur des évaluateurs de calcul de variation de l'écart type, du facteur de forme et du rapport signal sur bruit. Nous avons ensuite travaillé sur l'amélioration du diagnostic au niveau système à l'aide d'automates temporisés afin de simuler le fonctionnement des arbres de tests élémentaires. Ces travaux ont ensuite conduit à la modélisation et au diagnostic des systèmes complexes à l'aide des diagrammes d'état, des arbres de défaillances dynamiques, ainsi que leur simulation à l'aide des réseaux de Petri. Les modèles utilisés ont été complétés au moyen de nouvelles portes dynamiques. Ces travaux ont été appliqués au monde aéronautique, sur plusieurs hélicoptères et ont fait l'objet de deux brevetsThe object of the work of this thesis is to propose new processes of definition of tests (testability), new methods of tests, as well as new methods of tests interpretation (diagnosis). This work was carried out in the framework of aeronautics. It first intends to identify the needs of the helicopter diagnosis. The identified problems, related to the test and the diagnosis of the helicopters, were: - Non-detection of failures - Occurrence of many false alarms - Failure localisation ambiguity We first achieved the state of the art of research in diagnosis, in order to select technologies and methodologies allowing to answer the problematic. Candidate technologies were then structured in order to propose an integrated treatment. Thus we worked on methodologies of definition of the test, with testability simulation tools. We also defined new methods of test which allows determining the status of analogue sensors with the means of algorithms based on the calculus of variation of the standard deviation, form factor and noise-signal ratio. We then worked on the improvement of the diagnosis at system level using timed automata in order to simulate the operation of the tests tree. This work then led to the modelling of the complex systems using state diagram, dynamic fault trees, as well as their simulation with Petri networks. Additional doors were defined to complete the existing algorithms. Finally, this work was applied to the aeronautical world, to several helicopters and was the subject of two patents
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Cederlund, Jacob. "Radiated Susceptibility Measurements on Analogue Temperature Sensors". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279959.
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The need for electromagnetic compatibility is growing steadily as the usage of electronics in our daily lives is increasing more than ever. A common issue encountered in electromagnetic compatibility testing is analogue sensors that fail when exposed to electromagnetic fields. Testing how well electronics do when exposed to electromagnetic fields is called susceptibility testing, and standards for how to do these tests have been developed to ensure that the results of the tests can be reproduced. In this thesis work, analogue temperature sensors have been shielded using a few common techniques. The susceptibility of the sensors has been analysed by looking at their output voltage when the sensors were exposed to electro- magnetic fields of different field strengths. The output of the sensors was read by an Arduino that was shielded and tested to make sure it would not be affected by the electromagnetic fields used in the sensor tests. The result of the first set of sensor tests shows that shielding the cables running to the analogue temperature sensors and filtering away disturbances using ferrites gives a considerable decrease in susceptibility against electro- magnetic fields, while twisted cables and RC-filters did not. The results also showed that the introduction of a ground plane increased the susceptibility of the sensors, which most likely was due to it not providing the current with a path of less impedance and only served to increase the length of the unintentional antenna, which made it couple to the electromagnetic field more easily. However, during a second round of testing, the results of all the tests were hard to reproduce exactly, which calls into question how trustable the results of standardised susceptibility tests are. Therefore, when designing for the electromagnetic susceptibility of a product, a rather wide margin should be used in order to make sure that the product can reliably pass susceptibility tests.Användningen av elektronik ökar i samhället och därför även nödvändigheten för testning av elektromagnetisk kompatibilitet. Ett vanligt problem inom elektromagnetisk kompatibilitet är att analoga sensorer lätt blir utstörda av elektromagnetiska fält. Hur man ska testa en elektronisk produkts känslighet mot elektromagnetiska fält styrs av standarder som ser till att resultaten av testerna går att återskapa. I detta examensarbete har analoga temperatursensorer skärmats med ett par vanliga metoder. Sensorernas känslighet har analyserats genom att undersöka hur deras utspänning påverkas när sensorn blir utsatt för elektromagnetiska fält med olika fältstyrkor. Sensorernas utspänning lästes av en Arduino som skärmades och testades för att se till all att den inte påverkades av de elektromagnetiska fälten som användes under testandet av sensorerna. Resultaten från de första sensortesterna visar att använda skärmade kablar till de analoga temeperatursensorerna och att filtrera bort störningar med ferriter sänkte sensorernas känslighet mot elektromagnetiska fält betydligt medan tvinnade kablar och RC filter inte gjorde det. Testerna visade också att jord- plan i detta fall ökade sensorernas känslighet då de inte erbjöd en bättre väg för strömmen att gå utan endast skapade en längre oavsiktlig antenn, vilket gjorde att den lättare kunde koppla till det elektromagnetiska fältet. Däremot visade det sig i en andra testomgång, att resultaten inte gick att återskapa ex- akt. Detta ifrågasätter hur tillförlitliga dessa standardiserade tester är och visar att man bör ha en ganska bred marginal när man designar för att minska en produkts känslighet mot elektromagnetiska fält, så att den på ett tillförlitligt sätt kommer kunna klara av känslighetstester.
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Latzel, Stephan. "Test und Selbsttest von analogen Auswerteelektroniken bei Sensorsystemen in der Betriebsphase". Berlin Logos, 2008. http://d-nb.info/990541894/04.
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Lin, Jenn-Yu Gary. "Sensor compatible digitizing techniques for integrated microsensors". Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/22215.
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Kubáč, Stanislav. "Návrh digitálního optického výstupu". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217762.
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This work descibes general principles of measuring the alternating current and voltage using conventional and unconventional sensors.This work shows specific parmeters conected with principles of the measurement, advantages and disadvantages of individual measuring procedures, types of output signals, precisions, limitations, ways of power and so on. Part of the work is to find optimal measurement procedure, which can be aplicated to practical measuring of alternating currents and voltage. Main part of the work concerns the realisation of optimal method of measuring alternating current.
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Fracalossi, Ivanilde Aparecida Vieira Cardoso. "A universalidade subjetiva do juízo de gosto em Kant". Universidade de São Paulo, 2008. http://www.teses.usp.br/teses/disponiveis/8/8133/tde-04062008-102933/.
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A universalidade do juízo de gosto não tem um princípio objetivo porque não pretende determinar nenhum objeto. Mas para assegurar sua necessidade e escapar da contingência da experiência, ela se ampara no princípio exemplar do senso comum (Gemeinsinn), ou seja, num princípio subjetivo que determina apenas por sentimento, e não por conceito, aquilo que apraz ou não apraz. No entanto, sob a pressuposição de um assentimento universal a respeito do que é belo, a necessidade neste juízo adquire uma representação objetiva baseada no fundamento de nosso sentimento. É na dedução deste fundamento do sensus communis que se concentra nosso esforço nesta dissertação, pois tentaremos mostrar que ela percorre toda a Crítica da Faculdade de Julgar Estética.The universality of judgement of taste has none objective principle because does not intend to determine any object. Nevertheless, in order to assure its necessity and to escape from the experience\'s contingency, this universality supports itself in exemplary principle of common sense (Gemeinsinn), in other words, in a subjective principle which determines what is pleasure or not, only by feeling and not by concept. Although, under the presupposition of a universal agreement regarding what is beautiful, the necessity in this judgement acquires an objective representation based on our feeling\'s ground. It is in this deduction of this ground of sensus communis that concentrates our effort in this dissertation, because we will try to demonstrate that it courses through the entire Critique of Aesthetic Judgement.
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Tavakoli, Dastjerdi Maziar 1976. "Analog VLSI circuits for inertial sensory systems". Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86766.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (leaves 67-68).
by Maziar Tavakoli Dastjerdi.
S.M.
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Bonnard, Rémi. "Burst CMOS image sensor with on-chip analog to digital conversion". Thesis, Strasbourg, 2016. http://www.theses.fr/2016STRAD006/document.
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Ce travail vise à étudier l’apport des technologies d’intégration 3D à l’imagerie CMOS ultra-rapide. La gamme de vitesse d’acquisition considérée ici est du million au milliard d’images par seconde. Cependant au-delà d’une dizaine de milliers d’images par seconde, les architectures classiques de capteur d’images sont limitées par la bande passante des buffers de sortie. Pour atteindre des fréquences supérieures, une architecture d’imageur burst est utilisée où une séquence d’une centaine d’images est acquise et stockée dans le capteur. Les technologies d’intégration 3D ont connu un engouement depuis une dizaine d’années et sont considérées comme une solution complémentaire aux travaux menés sur les dispositifs (transistors, composants passifs) pour améliorer les performances des circuits intégrés. Notre choix s’est porté sur une technologie où les circuits intégrés sont directement empilés avant la mise en boitier (3D-SIC). La densité d’interconnexions entre les différents circuits est suffisante pour permettre l’implémentation d’interconnexions au niveau du pixel. L’intégration 3D offre d’intéressants avantages à l’imagerie intégrée car elle permet de déporter l’électronique de lecture sous le pixel. Elle permet ainsi de maximiser le facteur de remplissage du pixel tout en offrant une large place aux circuits de conditionnement du signal. Dans le cas de l’imagerie burst, cette technologie permet de consacrer une plus grande surface aux mémoires dédiées au stockage de la séquence d’image et ce au plus proche des pixels. Elle permet aussi de réaliser sur la puce la conversion analogique numérique des images acquisesThis work aims to study the inflows of the 3D integration technology to ultra-high speed CMOS imaging. The acquisition speed range considered here is between one million to one billion images per second. However above ten thousand images per second, classical image sensor architectures are limited by the data bandwidth of the output buffers. To reach higher acquisition frequencies, a burst architecture is used where a set of about one hundred images are acquired and stored on-chip. 3D integration technologies become popular more than ten years ago and are considered as a complementary solution to the technological improvements of the devices. We have chosen a technology where integrated circuits are stacked on the top of each other (3D-SIC). The interconnection density between the circuits is high enough to enable interconnections at the pixel level. The 3D integration offers some significant advantages because it allows deporting the readout electronic below the pixel. It thus increases the fill factor of the pixel while offering a wide area to the signal processing circuit. For burst imaging, this technology provides more room to the memory dedicated to the image storage while staying close to the pixel. It also allows implementing analog to digital converter on-chip
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Sůkalová, Kateřina. "Faktory ovlivňující senzorickou jakost analogů tavených sýrů". Doctoral thesis, Vysoké učení technické v Brně. Fakulta chemická, 2021. http://www.nusl.cz/ntk/nusl-438508.
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The presented thesis deals with the monitoring sensory quality of processed cheese analogues, focusing mainly on the taste (flavour) and related content of volatile (aroma active) substances. Model samples of analogues were produced by a standard procedure at Tomas Bata University in Zlín. The experimental part was divided into two experiments, which differed in the composition of model samples of analogues. In the first experiment, the traditional fat (butter) was completely replaced by selected vegetable fats (palm, coconut, mixed), in the second experiment only a part (1% w/w - expressed on the total weight of the sample) of butter was replaced by vegetable oils (apricot, flax seed, currant, grape seed). Solid phase microextraction in conjunction with gas chromatography with flame ionization detection was used to determine volatiles. Methods based on valid international standards were used to evaluate the sensory quality of samples, focusing mainly on flavor, namely evaluation using scales (ISO 4121), profile test (EN ISO 13299) and ranking test (ISO 8587). The aim of the work was to assess the effect of the addition of various vegetable fats/oils on the above parameters, at the same time their changes were monitored during 6 months of storage (at 6 ° C). The results showed that the vegetable oil used affects both the sensory quality and the content and composition of volatile substances of analogues. Significant differences between samples were mainly in taste, aroma and overall acceptability. The decreasing overall acceptability of the samples can be expressed in experiment I by the order: product with butter coconut palm mixed fat; in the case of experiment II: product with butter apricot = flax = grape currant oil. Mixed fat, currant and grape seed oil proved to be unsuitable for the production of analogues, on the contrary, analogues with coconut fat and apricot oil were evaluated best. Based on the results of sensory analyses, it was shown that the samples maintain a good sensory quality min. for 3 months while maintaining a low storage temperature ( 6 ° C). An analogue with coconut fat, whose taste, aroma and acceptability were rated as very good, and apricot oil, whose taste, aroma and acceptability were even rated as excellent, could enrich the food offer on the market.
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Solda', Silvia. "Design of low-power analog circuits for analog decoding and wireless sensors nodes". Doctoral thesis, Università degli studi di Padova, 2009. http://hdl.handle.net/11577/3426488.
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The first part of this work concerns analog decoding. It presents the design of the I/O interface for a fully analog iterative decoder for a serially concatenated convolutional code and of a fully analog Trellis Coded Modulation (TCM) decoder for error correction in multi-level (ML) flash memories. The iterative decoder represents a significant step ahead in the evolution of analog decoders due to its reconfigurability in both block length and code rate. Moreover, with an efficiency of 2.1nJ/bit, it outperforms digital decoders with the same block length of a factor up to 50. The potential performance and limitations of the analog approach for a TCM decoder have been investigated considering a 4-state and an 8-state decoder, both developed in a 0.18um standard CMOS process.
In the second part of the thesis, the design of a low-power transceiver chipset for ultra wideband impulse radio (UWB-IR) is presented, with particular emphasis on the transmitter design. In particular, the transmitter uses a novel combined mixer and power amplifier to generate a Gaussian pulse with 1.25GHz bandwith and center frequency of 7.875GHz. The combined MRX-PA includes a monolithic transformer to reach a maximum output voltage swing of 3.2Vpp, necessary to ensure the required link distance of 10 meters. The transformer has been designed in order to maximize the power efficiency and at the same time to realize a fourth-order ladder filter, so as to reduce the transmitter out-of band emissions. The efficiency of this design has been compared with state-of-the-art UWB-IR transmitters, showing how the proposed solution leads to an improvement in the transmitter efficiency of a factor of almost 10.La prima parte di questo lavoro di tesi e' dedicata alla decodifica analogica e presenta la progettazione di un'interfaccia di I/O per un decodificatore iterattivo completamente analogico per un codice convoluzionale concatenato in serie e di un decoder analogico per Trellis Coded Modulation (TCM) per la correzione degli errori in memorie Flash multi-livello. Il decodificatore iterattivo rappresenta un grosso passo avanti nell'evoluzione dei decodificatori analogici in quanto e' possibile riconfigurarne sia la lunghezza di blocco che il rate del codice. Per di piu', con un'efficienza di 2.1nJ/bit, migliora fino a 50 volte le prestazioni in termini di efficienza dei decodificatori digitali con la stessa lunghezza di blocco. Le potenziali prestazioni e le limitazioni dell'approccio analogico per un decodificatore per TCM sono state investigate considerando due diversi decodificatori, uno a 4 stati ed uno ad 8 stati, entrambi sviluppati in un processo CMOS standard con una lunghezza di canale di 0.18um. Nella seconda parte della tesi viene presentato il design di un transciver per una radio ad impulsi a banda larga (UWB-IR), con particolare enfasi sulla progettazione del trasmettitore. Il trasmettitore utilizza una nuova combinazione di mixer e amplificatore di potenza per generare un impulso gaussiano con una larghezza di banda di 1.25GHz ed una frequenza centrale di 7.875GHz. Il nuovo circuito, inoltre, include un trasformatore monolitico in modo tale da generare una tensione di uscita di 3.2Vpp, necessaria per garantire la distanza di connessione richiesta di almeno 10 metri. Il trasformatore e' stato progettato in modo da massimizzare l'efficienza in termini di potenza e, allo stesso tempo, realizzare un filtro ladder del quarto ordine al fine di ridurre le emissioni fuori banda del trasmettitore stesso. Confrontando l'efficienza di questo design con trasmettori per UWB-IR allo stato dell'arte si e' visto come la soluzione da noi proposta porti ad un miglioramento dell'efficienza del trasmettitore di un fattore pari a 10.
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Lin, Shyh-Hsiang. "Meat analog development and physical, chemical, and sensory properties /". free to MU campus, to others for purchase, 1998. http://wwwlib.umi.com/cr/mo/fullcit?p9924899.
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Peng, Sheng-Yu. "Charge-based analog circuits for reconfigurable smart sensory systems". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29655.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Degertekin, F.; Committee Member: Ghovanloo, Maysam; Committee Member: Minch, Bradley. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Bechen, Benjamin. "Systematischer Entwurf analoger Low-Power-Schaltungen in CMOS anhand einer kapazitiven Sensorauslese". Stuttgart Fraunhofer-IRB-Verl, 2007. http://d-nb.info/988795590/04.
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Sweeney, Paul. "FROM 0.5% TO 0.05%: ACHIEVING NEW LEVELS OF SENSOR ACCURACY IN AN AIRBORNE ENVIRONMENT". International Foundation for Telemetering, 2004. http://hdl.handle.net/10150/605805.
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International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, CaliforniaWith recent improvements in data acquisition technology, it is now possible to use an FTI data acquisition system to measure analog signals with a total error from all sources of less than 0.05% - over an extended temperature range - and at high sample rates. This accuracy is better than one count of an old 10-bit system and includes non-linearities, initial errors (in gain, offset and excitation) and drift errors, simplifying the task of interpreting data acquisition system performance specifications. This paper looks at some practical steps taken to achieve this accuracy, from a hardware design and signal processing perspective. This leads to a discussion of implications for the FTI system designer, including: sensor and wiring specifications, sample rate, filtering specifications, and a discussion of implications for the data processing engineers.
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Fisher, Kim Noël. "Behavioural and physiological effects of two aniracetam analogues". Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22585.
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The behavioural and electrophysiological consequences of two newly developed aniracetam analogues were investigated in male Long-Evans rats. Results indicate that an intraperitoneal (i.p.) injection of LD38.2 significantly improved retention in a two odour olfactory discrimination task. However, three different dosages of LN1 did not facilitate memory in the task. In rats with chronically implanted electrodes, both compounds rapidly crossed the blood brain barrier (BBB) after an i.p. injection and influenced several parameters of the field excitatory postsynaptic potential (EPSP) in the CA1 and dentate gyrus regions of the hippocampus. The enhancement of the field EPSP following LD38.2 administration may be related to the drug's ability to facilitate memory in the olfactory discrimination task. Compounds, like LD38.2, that enhance both hippocampal transmission and performance in learning/memory tasks in laboratory rodents may have implications for the treatment of clinical memory disorders.
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Salehi-Abari, Omid. "Building compressed sensing systems : sensors and analog-to-information converters". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78472.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 93-96).
Compressed sensing (CS) is a promising method for recovering sparse signals from fewer measurements than ordinarily used in the Shannon's sampling theorem [14]. Introducing the CS theory has sparked interest in designing new hardware architectures which can be potential substitutions for traditional architectures in communication systems. CS-based wireless sensors and analog-to-information converters (AIC) are two examples of CS-based systems. It has been claimed that such systems can potentially provide higher performance and lower power consumption compared to traditional systems. However, since there is no end-to-end hardware implementation of these systems, it is difficult to make a fair hardware-to-hardware comparison with other implemented systems. This project aims to fill this gap by examining the energy-performance design space for CS in the context of both practical wireless sensors and AICs. One of the limitations of CS-based systems is that they employ iterative algorithms to recover the signal. Since these algorithms are slow, the hardware solution has become crucial for higher performance and speed. In this work, we also implement a suitable CS reconstruction algorithm in hardware.
by Omid Salehi-Abari.
S.M.
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Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors". Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.
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The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.
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Zhang, Chenglong. "LOW-POWER LOW-VOLTAGE ANALOG CIRCUIT TECHNIQUES FOR WIRELESS SENSORS". OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/982.
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This research investigates lower-power lower-voltage analog circuit techniques suitable for wireless sensor applications. Wireless sensors have been used in a wide range of applications and will become ubiquitous with the revolution of internet of things (IoT). Due to the demand of low cost, miniature desirable size and long operating cycle, passive wireless sensors which don't require battery are more preferred. Such sensors harvest energy from energy sources in the environment such as radio frequency (RF) waves, vibration, thermal sources, etc. As a result, the obtained energy is very limited. This creates strong demand for low power, lower voltage circuits. The RF and analog circuits in the wireless sensor usually consume most of the power. This motivates the research presented in the dissertation. Specially, the research focuses on the design of a low power high efficiency regulator, low power Resistance to Digital Converter (RDC), low power Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with parasitic error reduction and a low power low voltage Low Dropout (LDO) regulator. This dissertation includes a low power analog circuit design for the RFID wireless sensor which consists of the energy harvest circuits (an optimized rectifier and a regulator with high current efficiency) and a sensor measurement circuit (RDC), a single end sampling SAR ADC with no error induced by the parasitic capacitance and a digital loop LDO whose line and load variation response is improved. These techniques will boost the design of the wireless sensor and they can also be used in other similar low power design.
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Canu, Antoine. "Conversion Analogique / Numérique versatile dans un environnement avionique contraint". Thesis, Supélec, 2013. http://www.theses.fr/2013SUPL0004/document.
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Les systèmes électroniques embarqués à bord des aéronefs rassemblent des informations sur l’environnement qui les entourent au moyen de différents types de capteurs. À l’heure actuelle, l’acquisition des signaux générés par ces capteurs se fait au moyen de circuits électroniques d’interfaçage dédiés à un type de capteur en particulier, ce qui limite les possibilités d’évolution des calculateurs de bord.Nos travaux visent à remplacer ces circuits d’interfaçage par une interface dite versatile, capable de faire l’acquisition de signaux issus de différents types de capteurs. L’environnement dans lequel les systèmes avioniques sont amenés à fonctionner est particulièrement difficile, notamment par la présence de modes communs parasites importants, supérieures à plusieurs dizaines de volts. Après une exploration détaillée de cet environnement, nous proposons une architecture d’interface versatile, basée sur un ASIC mixte et un FPGA. L’ASIC est chargé du conditionnement analogique des signaux et de leur conversion dans le domaine numérique, et peut-être configuré à plusieurs niveaux (gains, offsets, impédances...). Le FPGA comprend les différents traitements numériques nécessaires à l’extraction de l’information contenue dans les signaux. Nous proposons de plus une méthode mixte permettant de corriger les imprécisions analogiques, telles que les défauts d’appairage, souvent critiques dans l’acquisition de signaux différentiels. Un circuit de test a été réalisé dans une technologie CMOS High Voltage 0.35µm afin de valider les différents principes proposés dans nos travauxAvionic embedded systems sense their environment through the use of various sensors. Currently, the electrical signals generated by these sensors are acquired by dedicated interface circuits, which limits the functionalities that can be implemented in the computer and slows down their evolution.Our work aims at replacing these interfacing circuits by a more flexible interface, called versatile interface, which has the ability to acquire different kind of signals. Avionic embedded systems usually operate in a pretty harsh environment, in which important common mode voltages of more than thirty volts can superimpose to useful signals. After a thorough exploration of this environment and its specifities, we propose an architecture of the versatile interface, based on a mixed signal ASIC and a FPGA. The ASIC includes a programmable analog signal conditioning stage which is able to withstand the high voltages present in the harsh avionic environment. The FPGA processes the different signals and extract the useful information from them. We also propose method which allows to correct the analog imprecisions due to mismatch or temperature drifts. This method uses analog and digital processing, and allow our versatile interface to be immune to process or temperature variations. A test circuit has been realized in a high voltage 0.35µm CMOS technology, in order to validate the different principles that we propose in this work
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Graupner, Achim. "Robuster Entwurf und statistische Modellierung für Bildsensoren mit hochparalleler analoger Bildverarbeitungseinheit". Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-108459.
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Die gemeinsame Integration von Bildsensor und analoger hochparalleler Verarbeitungseinheit stellt eine Möglichkeit zur Realisierung von leistungsfähigen ein-chip Bildaufnahmesystemen dar. Die vorliegende Arbeit liefert Beiträge zum systematischen Entwurf von derartigen Systemen und analysiert bekannte und neuartige Schaltungstechniken bezüglich ihrer Eignung für deren Implementierung. Anhand des vom Autor mitentwickelten CMOS-Bildsensors mit hochparalleler analoger Bildverarbeitungseinheit werden die vorgestellten Methoden und Schaltungstechniken demonstriert. Die Problematik beim Entwurf hochparalleler analoger Systeme besteht in der im Vergleich zu digitalen Systemen geringen Automatisierbarkeit. Es ist kein top-down-Entwurf möglich, da nicht jede beliebige Funktion mit beliebiger Genauigkeit realisierbar ist. Um die jeweilige Genauigkeit der Funktionsblöcke bei der Analyse des hochparallelen Systems berücksichtigen zu können, sind rechenaufwendige Simulationen nötig. Um diesen Rechenaufwand zu senken, wird vorgeschlagen, für die Simulation des Gesamtsystems einen angepaßten Simulator und für die Analyse der schaltungstechnischen Realisierung der Funktionsblöcke konventionelleWerkzeuge für elektrische Netzwerke zu verwenden. Die beiden Simulationsdomänen werden mit Hilfe von numerischen Verhaltensmodellen verbunden. Durch diese Trennung wird die Simulation des Gesamtsystems als Bestandteil des Entwurfsflusses praktikabel. Für die Bewertung, inwieweit die zufälligen Schwankungen der Bauelementeparameter das Verhalten von Baublöcken beeinflussen, wird die Varianzanalyse als Alternative zur konventionellen Monte-Carlo-Analyse vorgeschlagen. Die Varianzanalyse ist wesentlich weniger rechenaufwendig und liefert genaue Resultate für alle Schaltungseigenschaften mit hinreichend glatten Parameterabhängigkeiten, wenn die Bauelementeparameter als normalverteilt und statistisch unabhängig angenommen werden können. Sie hat darüberhinaus den Vorteil, das Schaltungsverständnis für den Entwerfer zu erhöhen, da sofort die Bauelementeparameter mit dem größten Einfluß auf das Schaltungsverhalten identifiziert werden können. Der Vergleich verschiedener Schaltungstechniken hat gezeigt, daß zeitdiskrete wertkontinuierliche Verfahren, bei denen die Information als Strom repräsentiert wird, für die Realisierung von hochparallelen analogen Systemen besonders geeignet sind. Als besonderer Vorteil ist die weitestgehende Unabhängigkeit des Verhaltens derartiger Schaltungen von Bauelementeparametern hervorzuheben.Weitere Schaltungstechniken, deren Verhalten von zufälligen Parameterabweichungen nur wenig beeinflußt werden, sind in einer Taxonomie zusammengefaßt. Es wurde ein CMOS-Bildsensor mit hochparalleler analoger Bildverarbeitungseinheit und digitaler Ausgabe realisiert. Der current-mode-Bildsensor ist separat von der Verarbeitungseinheit angeordnet. Es wurden vier verschiedene Realisierungsmöglichkeiten untersucht und eine konventionelle integrierende voltage-mode Pixelzelle mit nachfolgendem differentiellen Spannungs- Strom-Wandler realisiert. Das Rechenfeld ist für die räumliche Faltung oder lineare Transformation von Bilddaten mit digital bereitzustellenden Koeffizienten ausgelegt. Dessen Operation basiert auf einer bit-weisen analogen Verarbeitung. Der Schaltkreis wurde erfolgreich getestet. Die nachgewiesene Bildqualität deckt sich in guter Näherung mit den bei der Simulation des Gesamtsystems getroffenen VorhersagenThe joined implementation of an image sensor and a highly parallel analog processing unit is an advantageous approach for realizing efficient single-chip vision systems. This thesis proposes a design flow for the development of such systems. Moreover known and novel circuit techniques are analysed with respect for their suitability for the implementation of highly parallel systems. The presented methodologies and circuit techniques are demonstrated at the example of a CMOS image sensor with an embedded highly parallel analog image processing unit in whose design the author was involved. One of the major problems in designing highly parallel analog circuits is the low automation compared to the design of digital circuits. As not every function can be realized with arbitrary accuracy top-down-design is not feasible. So, when analysing the system behaviour the respective precision of each function block has to be considered. As this is a very demanding task in terms of computing power, it is proposed to use a dedicated tool for the simulation of the system and conventional network analysis tools for the inspection of the circuit realizations. Both simulation domains are combined by means of numerical behavioural models. By using separate tools system-simulations of highly parallel analog systems as a part of the design flow become practicable. Variance analysis basing on parameter sensitivities is proposed as an alternative to the conventional Monte-Carlo-analysis for investigating the influence of random device parameter variations on the system behaviour. Variance analysis requires much less computational effort while providing accurate results for all circuit properties with sufficiently smooth parameter dependencies if the random parameters can be assumed normally distributed and statistically independent. Additionally, variance analysis increases the designer’s knowledge about the circuit, as the device parameters with the highest influence on the circuit performance can immediately be identified. The comparison of various circuit techniques has shown, that sampled-time continuous-valued current-mode principles are the best choice for realizing highly parallel analog systems. A distinctive advantage of such circuits is their almost independence from device parameters. A selection of further circuit techniques with low sensitivity to random device parameter variations are summarized in a taxonomy. A CMOS image sensor with embedded highly parallel analog image processing unit has been implemented. The image sensor provides a current-mode output and is arranged separate from the processing unit. Four different possibilities for realizing an image sensor have been analysed. A conventional integrating voltage-mode pixel cell with a succeeding differential voltage- to-current-converter has been selected. The processing unit is designed for performing spatial convolution and linear transformation with externally provided digital kernels. It operates in bit-wise analog manner. The chip has been tested successfully. The measured image quality in good approximation corresponds with the estimations made with system simulations
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Best, Quinn Adams. "XANTHENE AND SILICON ANALOGS OF XANTHENE FLUOROPHORES AS CHEMICAL SENSORS FOR pH AND HYPOCHLOROUS ACID". OpenSIUC, 2013. https://opensiuc.lib.siu.edu/dissertations/662.
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Chemical sensors capable of detecting a specific atom or molecule under various conditions have been utilized in biological and environmental analyses. Fluorescence based sensors are particularly advantageous in these studies because of their high sensitivity, relative ease in handling, and low technical costs. This dissertation focuses on the detection of two analytes, H+ and hypochlorous acid, which are of interest in biology because the presence of abnormal quantities of these analytes may be indicative of disease. We have established a new platform for which sensitive changes in various regions of pH can be detected using fluorescence. The aminomethylrhodamine (AMR) scaffold is highly versatile, i.e. the pH range in which the sensor is active can be tuned by introducing different substituents on the amine moiety. Overall this systematic approach to the design of pH sensitive fluorophores has allowed for a library of compounds that are responsive over a broad range of pH (pH 3 - 10) by simply changing the substituent on the amino group. We report the synthesis and characterization of a silicon analog of rhodamine for the fluorescence based detection of hypochlorous acid. This fluorophore exhibits a 90 nm bathochromic shift in its absorption and emission, relative to its oxygen counterpart. Hypochlorous acid is a biological agent linked to certain diseases. Therefore, the longer wavelength properties of the this far-red fluorescent sensor will be of significant benefit to imaging experiments of this analyte in biological media and tissue due to its spectral proximity of the so called NIR optical window. Furthermore, the novel synthetic methodology of this sensor possesses a key intermediate, which could potentially lead to future fluorescence based sensors. The characterization of a fluorescent probe designed for the detection of hypochlorous acid (HOCl) using a silicon analog of fluorescein (SiF) was also reported. Over a range of pHs, the probe reacts with a stoichiometric amount of HOCl resulting in a mixture of two pH dependent fluorescent species, a SiF disulfide product and a SiF sulfonate product. The unique colorometric properties of the individual SiF fluorophores were utilized to perform simultaneous detection of HOCl and pH. When an excess of HOCl is present, the SiF fluorophores become chlorinated, via an intermediate halohydrin, resulting in a more pH independent and red-shifted fluorophore. Finally, an attempt was made at developing a pH responsive photodynamic therapy agent. This system was designed to target the relatively low extracellular pH found around tumors. A di-bromohydroxymethylrhodamine system was synthesized and the photophysical properties were characterized. This system absorbs weakly under acidic conditions (ca. pH 3), however was shown to be a moderate photosensitizer under acidic conditions.
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Parmesan, Luca. "Photon efficient, high resolution, time resolved SPAD image sensors for fluorescence lifetime imaging microscopy". Thesis, University of Edinburgh, 2018. http://hdl.handle.net/1842/33171.
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FLIM is branch of microscopy mainly used in biology which is quickly improving thanks to a rapid enhancement of instrumentation and techniques enabled by new sensors. In FLIM, the most precise method of measuring fluorescent decays is called TCSPC. High voltage PMT detection devices together with costly and bulky optical setups which scan the sample are usually required in TCSPC instrumentation. SPADs have enabled a big improvement in TCSPC measurement setup, providing a CMOS compatible device which can be designed in wide arrays format. However, sensors providing in-pixel TCSPC do not scale in size and in large array like the time-gated SPAD pixel sensors do. Time-gated pixels offer a less precise lifetime estimation, discarding any photon information outside a given time window, but this loss in photon-efficiency is offset by gains in pixel size. This work is aimed at the development of a wide field TCSPC sensor with a pixel size and fill factor able to reduce the cost of such devices and to obtain a high resolution time-resolved fluorescence image in the shortest time possible. The study focuses on SPAD and pixel design required to maximise the fill factor in sub 10 μm pixel pitch. Multiple pixel designs are proposed in order to reduce pixel area and so enable affordable wide array TCSPC systems. The first proposed pixel performs the CMM lifetime estimation in order to reduce the frame rate needed to stream the data out of the SPAD array. This pixel is designed in a 10 μm pitch and attains with the most aggressive design a fill factor of 10:17 %. A second design proposes an analogue TCSPC which consists in a S/H TAC circuitry. This simpler pixel can achieve a higher fill factor of 19:63% as well as smaller pitch of 8 μm thanks to the adoption of SPAD n-well and electronics area sharing. This last design is implemented in a 320 x 256 SPAD array in which is included part of a novel ADC aimed at reduction of the processing time required to build a TCSPC histogram. A more conventional analogue readout is used to evaluate the pixel performance as well as a more fine TCSPC histogram. The device was used to measure the fluorescence lifetime of green micro-spheres while the 2b flash ADC is used to demonstrate rapid resolution and separation of two different fluorescence decays.
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Zamba, Martin. "Návrh adaptivního systému na rekonfigurovatelné platformě s využitím vestavěného analogově číslicového převodníku". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-236144.
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This thesis has its main subject pointed on possibilities of exploiting reconfigurable digital systems on FPGA basis in mixed signal applications. Description of reconfigurable and adaptive systems in general and summary of known architectures is presented in first part of this work. Next, possibilities of exploiting configurability of FPGAs in conjunction with XADC digital to analog converter are examined. These converters are provided in 7-series FPGAs and Zynq-7000 systems from Xilinx. Concept of exploiting XADC for inductance measurements is presented as alternative to existing solution - LDC1000 integrated circuit provided by Texas Instruments. Such system utilizing FPGA and XADC would come with a lot of benefits: better system integration, better signal processing options, possibility of constructing adaptive system with numerous sensory elements and last but not least, lower system cost. Advantages and disadvantages of such approach are analyzed in the very final part of this work and possible options for extension of this work are presented.
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Hrycík, Tomáš. "Porovnání použití přístrojových transformátorů a senzorů v aplikacích s ochranou REF 542plus". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218429.
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The aim of this Master´s thesis is use of instrument transformers and sensors on field of industry protection. We will compare current and voltage transformers, current sensor – based on Rogowski coil, voltage sensor – based on voltage divider. By this measure devices, we can monitoring values of analog quantities in medium voltage switchgear. It is impossible to compare, measure and analyze without this measure devices. There is protection terminal REF542plus, which can compile this values. The REF542plus ability are measuring, monitoring, remote control and protection. First, we will discuss about theory of sensors and convential instrument transformers and analysis of analog signal. We will compare analog input channel on sensor´s analog module and transformer´s analog module. There are few differences between type of analog modules. For analog signal analysis are important frequency filters and Analog/ Digital Convertor (sigma-delta). We will describe functions and options of REF542plus. In practical part of this project, we will test protection functions of protection terminal. First, protection terminal will be connected to sensors. Second protection terminal will be connected to transformers. For testing we chose Earth-fault directional protection and differential protection. We will make only secondary tests. That´s mean, input analog quantities to REF542plus will be simulated by tester. In all we will verify quality of protection. We will focus on lower settings of protection and we will inject protection by low current. Objectives are testing of trip characteristics and measuring of trip time.
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Johansson, Robert. "Implementation of an Active Pixel Sensor with Shutter and Analog Summing in a 0.35um Process". Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1927.
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An integrated circuit for evaluation of APS technology has been implemented in a 0.35 um process. The APS features snapshot operation and the readout circuitry can carry out: CDS, DS, and analog summing all in one circuit that is fully programmable. The output from the chip is a differential analog signal, intended to be connected to a high-speed ADC on an evaluation board. The sensor is fully compatible with current IVP camera systems, hence, the evaluation board should be easy to design.
Several small code snippets that illustrate different modes of readout have been outlined, to aid the evaluation of the chip. It should be fairly straightforward to convert these code snippetsinto actual camera code. Furthermore, some code to illustrate a possible application and a faster mode of CDS have been indicated.
Six types of APs have been implemented. They differ regarding diode type and implementation of the sampling capacitor. Design instructions and models for hand calculation have been described. The models have in most cases been validated by simulations and it has been shown that a readout speed of 8 MHz is possible to obtain, even for a larger sensor than this test chip. The desired resolution of 8 bits cannot be obtained for high levels of illumination. However, for low levels of illumination a resolution as high as 10 bits is possible.
The chip layout has been validated to a large extent and should result in a fully functional chip, if manufactured. However, in the eventuality that IVP decides to manufacture this chip it is recommended to use the newer CAD tools, not available to the author at the time of implementation, to check the chip design for DRC and LVS errors.
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Cho, Sunghwan. "Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks". Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42915.
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For large multihop networks, the time synchronization (TS) error accumulates as the hop number increases with conventional methods, such as Timing-sync Protocol for Sensor Networks (TPSN), Reference Broadcast Synchronization (RBS), and Flooding Time Synchronization Protocol (FTSP). In this paper, to reduce the number of hops to cover the large network and exploit the spatial averaging of TS error between clusters, a novel method combining Concurrent Cooperative Transmission (CCT) and Semi-Cooperative Spectrum Fusion (SCSF) is proposed.
This novel method named Cooperative Analog and Digital (CANDI) Time Synchronization protocol consists of two phases: The digital stage and the analog stage. The digital stage uses CCT to broadcast TS packet containing the time information. Cooperating nodes transmit the digitally encoded message in orthogonal channels simultaneously, so the receiver combines the multiple packet to acheive significant SNR advantage.
In the analog stage, the cooperating nodes simultaneously transmit their slightly different individual estimates of the propagation time by using frequency shift modulation. Nodes receiving this signal combat fading and reduce estimation error in one step through the averaging inherent in diversity combining. Simulation results for two-dimension (2-D) networks are given to evaluate the performance of CANDI, and CANDI is compared with TPSN.
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Helmisaari, Tina. "Overheat protection for immersion heaters : Analysis of analog and digital temperature sensors". Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-34041.
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Immersion heaters are used by industries to heat fluids. The element of an immersion heater need to be fully immersed into the heated liquid, otherwise it could be subject to overheat. The main purpose of this thesis is to find a temperature sensor, which could signal in case the immersion heater is at risk to suffer from overheat due to low liquid level. A comparison of accuracy, size and cost between an analog and a digital sensor is held, to conclude whether either one is at an advantage for this application.An immersion heater with ceramic element and quartz glass tube and a water tank, both provided by Scandymet, is used during experiments. First, the position for the sensor inside the heater was examined, by placing the sensor at different positions. Next, measurements of the operating temperature of the immersion heater were made at different liquid levels. This resulted in a placement for the sensor near the head of the immersion heater and an approximate temperature range from 41 ℃ to 58 ℃. Both the analog and digital sensors is chosen with measurable ranges to match the result from previous experiments. A thermistor along with a linearizing series resistor make the analog design and a DS18B20+ with a pull-up resistor the digital design. The microcontroller for both designs is Adafruit Feather Adalogger M0, which is programmed in C/C++ using Arduino IDE software. It is concluded that it is possible to signal in case liquid level decrease below minimum level, by inserting a temperature sensing device into the immersion heater. The sensor should be placed above the maximum liquid level mark, close to the head of the heater. The analog design would be recommended as overheat protection, due to its smaller size, less expensive and, with further calibration, accurate response.
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Mitra, Michal. "Charakterizace sýrových analogů vyrobených s přídavkem ořechového oleje". Master's thesis, Vysoké učení technické v Brně. Fakulta chemická, 2020. http://www.nusl.cz/ntk/nusl-413559.
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This thesis deals with the production and characterization of cheese analogues, i.e. products where some of the dairy components are partially or completely replaced by a non-dairy component. Model samples – Eidam type cheese and analogue with the addition of pistachio oil, were produced by a conventional technological process at MENDELU in Brno. Free and bound fatty acids, volatile substances and sensory quality were selected and monitored as the main characterizing parameters of the sample quality. The aim was to characterize the differences between the samples caused by the addition of nut oil in the monitored parameters. The HS-SPME-GC-MS method was used for the identification and semi-quantification of volatiles. The extraction of fats from the samples was performed with a mixture of solvents (diethyl ether, petroleum ether), fatty acids were converted to methyl esters by acid esterification with methanolic solution of boron trifluoride as a catalyst and subsequently identified and quantified by GC-FID. Descriptive scales and comparisons with standard were used to sensory evaluate the appearance, color, texture, odor, taste, and overall acceptability of the samples. The structure was monitored by electron microscopy. The results show that the addition of pistachio oil affects the sensory properties, the maturation process (higher content of volatile substances), the nutritional value (increased content of unsaturated fatty acids) and the stability of the product.
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Levski, Deyan. "Investigations of time-interpolated single-slope analog-to-digital converters for CMOS image sensors". Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:31b9426f-8a7c-4c86-9471-32431f33ebe7.
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This thesis presents a study on solutions to high-speed analog-to-digital conversion in CMOS image sensors using time-interpolation methods. Data conversion is one of the few remaining speed bottlenecks in conventional 2D imagers. At the same time, as pixel dark current continues to improve, the resolution requirements on imaging data converters impose very high system-level design challenges. The focus of the presented investigations here is to shed light on methods in Time-to-Digital Converter interpolation of single-slope ADCs. By using high-factor time-interpolation, the resolution of single-slope converters can be increased without sacrificing conversion time or power. This work emphasizes on solutions for improvement of multiphase clock interpolation schemes, following an all-digital design paradigm. Presented is a digital calibration scheme which allows a complete elimination of analog clock generation blocks, such as PLL or DLL in Flash TDC-interpolated single-slope converters. To match the multiphase clocks in time-interpolated single-slope ADCs, the latter are generated by a conventional open-loop delay line. In order to correct the process voltage and temperature drift of the delay line, a digital backend calibration has been developed. It is also executed online, in-column, and at the end of each sample conversion. The introduced concept has been tested in silicon, and has showed promising results for its introduction in practical mass-production scenarios. Methods for reference voltage generation in single-slope ADCs have also been looked at. The origins of error and noise phenomenona, which occur during both the discrete and continuous-time conversion phases in a single-slope ADC have been mathematically formalized. A method for practical measurement of noise on the ramp reference voltage has also been presented. Multiphase clock interpolation schemes are difficult for implementation when high interpolation factors are used, due to their quadratic clock phase growth with resolution. To allow high interpolation factors a time-domain binary search concept with error calibration has been introduced. Although the study being conceptual, it shows promising results for highly efficient implementations, if a solution to stable column-level unit delays can be found. The latter is listed as a matter of future investigations.
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Sutula, Stepan. "Low-power high-resolution cmos switched-capacitor delta-sigma analog-to-digital converters for sensor applications". Doctoral thesis, Universitat Autònoma de Barcelona, 2015. http://hdl.handle.net/10803/667348.
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Aquesta tesi doctoral explora mètodes per augmentar tant l'eficiència energètica com la resolució de convertidors analògic-digital (ADCs) Delta-Sigma de condensadors commutats mitjançant innovadors circuits CMOS de baix consum. En aquest sentit, s'ha prioritzat un alt rendiment, fiabilitat i baixos costos de fabricació dels circuits, així com un flux de disseny simple per ser reutilitzat per la comunitat científica.
S'ha escollit l'arquitectura Delta-Sigma per la seva simplicitat i la tolerància a les imperfeccions dels seus blocs bàsics. La recerca de circuits presentada utilitza tècniques de condensadors commutats per aconseguir un aparellament adequat entre els dispositius i per tenir dependència només de la fluctuació del rellotge extern.
Les tècniques de disseny de circuits analògics de baix corrent desenvolupades tenen com a objectiu l'eficiència energètica, aprofitant les regions d'inversió feble i moderada d'operació del transistor MOS.
També s'investiguen nous amplificadors operacionals Classe AB com a elements actius, tractant d'utilitzar energia només durant les transicions dinàmiques, el que redueix el consum de potència a nivell de circuit. Els circuits no utilitzats durant un determinat període de temps es desactiven, reduint així el consum de potència a nivell de sistema i minimitzant el nombre de dispositius de commutació en el camí de senyal.
S'ha millorat la fiabilitat dels circuits proposats evitant els elevadors de tensió o altres tècniques que poden incrementar els voltatges d'operació més enllà del d'alimentació nominal de la tecnologia CMOS utilitzada. A més, per incrementar el rendiment de producció dels ADCs resultants, s'ha enfocat la recerca de disseny sobre noves topologies de circuits amb una baixa sensibilitat a les variacions tant del procés de fabricació com de la temperatura.
Un modulador Delta-Sigma de 96.6 dB de SNDR, 50 kHz d'ample de banda, 1.8 V i 7.9 mW per a ADCs s'ha implementat en una tecnologia estàndard CMOS de 0.18 µm basat en les novetats proposades. Els resultats de les mesures indiquen la millora de l'estat de l'art d'ADCs d'alta resolució sense elevadors de tensió del senyal de rellotge, calibratge o compensació digital, fet que beneficia una àmplia gamma d'aplicacions de sensors intel·ligents.
Una altra contribució en el marc d'aquest treball de recerca és la millora dels amplificadors operacionals de Classe AB d'una sola etapa exclusivament MOS. Els amplificadors commutats de mirall variable desenvolupats, amb la seva remarcable eficiència de corrent i compensació intrínseca de freqüència juntament amb un fons d'escala i un guany de llaç obert grans, són adequats per a un ample ventall d'aplicacions de baix consum i d'alta precisió més enllà de l'àmbitThis PhD thesis explores methods to increase both the power efficiency and the resolution of switched-capacitor Delta-Sigma analog-to-digital converters (ADCs) by employing novel CMOS low-power circuits. A high circuit performance, reliability, low manufacturing costs and a simple design flow to be reused by the scientific community are prioritized. The Delta-Sigma architecture is chosen because of its simplicity and tolerance for its basic block imperfections. The presented circuit research makes use of switched-capacitor techniques to achieve an appropriate matching between the devices and to be dependent only on the external clock jitter. The developed low-current analog circuit techniques target power efficiency, taking advantage of the weak- and moderate-inversion regions of the MOS transistor operation. Novel Class-AB operational amplifiers are also investigated as active elements, trying to use energy only for dynamic transitions, thus reducing power consumption at the circuit level. The circuits unused during a certain period of time are switched off, thus reducing power consumption at the system level and minimizing the number of signal-path switching devices. The circuit reliability is improved by avoiding bootstrapping or other techniques which may increase the operation voltages beyond the nominal supply of the target CMOS technology. Furthermore, the design research also focuses on new circuit topologies with a low sensitivity to both process and temperature deviations in order to increase the yield of the resulting ADCs. A 96.6-dB-SNDR 50-kHz-BW 1.8-V 7.9-mW Delta-Sigma modulator for ADCs is implemented in a standard 0.18-µm CMOS technology based on the proposed novelties. The measurement results indicate the improvement of the state of the art of high-resolution ADCs without clock bootstrapping, calibration or digital compensation, benefiting a wide range of smart sensing applications. Another contribution made in the scope of this research work is the improvement of MOS-only single-stage Class-AB operational amplifiers. The developed switched variable-mirror amplifiers, with their remarkable current efficiency and intrinsic frequency compensation together with high full-scale value and open-loop gain, are suitable for low-power high-precision applications extending beyond the specific area of ADCs, such as digital-to-analog converters (DACs), filters or generators.
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Tanacharoenwat, Watchanun. "Design of test hardware for characterization of key parameters of analog gas sensors". Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71209.
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Hydrogen sensors are essential to facilitate the detection of accidental hydrogenreleases wherever hydrogen will be produced, distributed, stored, and used. Comparedto the helium detection: hydrogen is cheaper than helium, no need for avacuum and the lower cost of producing the instruments. Thus, hydrogen leakdetectors are used in variety of applications such as localization of telephony cabledamages, finding leaks in fuel tanks and quality control in heating, ventilating, andair conditioning (HVAC) and refrigeration systems. This thesis work combines thedesign and implentation of test hardware, software programming and the characterizationof critical parameter of analog hydrogen sensor for leak detecion systemdevelopment.Controller area network (CAN) protocol for data communication is used in theproject work. With the benefit of CAN over multiple device communication, thetest hardware is designed for multichannel testing. Graphical LabVIEW software isdeveloped and programmed basically for instrumental control and sensor responseacquisition. Finally, a few experiments have been conducted to estimate some keyparameters of the gas sensors such as a sensor noise level and sensor responsesover different hydrogen concentrations.
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Grimes, Todd S. "Adaptive Power Analog-to-Digital Interface for Digital Systems". Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1483366560887816.
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Bhatnagar, Purva. "Multi-Frequency and Multi-Sensor Impedance Sensing Platform for Biosensing Applications". University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1543999395772179.
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Bhattacharya, Soumendu. "Alternate Testing of Analog and RF Systems using Extracted Test Response Features". Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7200.
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Testing is an integral part of modern semiconductor industry. The necessity of test is evident, especially for low-yielding processes, to ensure Quality of Service (QoS) to the customers. Testing is a major contributing factor to the total manufacturing cost of analog/RF systems, with test cost estimated to be up to 40% of the overall cost. Due to the lack of low-cost, high-speed testers and other test instrumentation that can be used in a production line, low-cost testing of high-frequency devices/systems is a tremendous challenge to semiconductor test community. Also, simulation times being very high for such systems, the only possible way to generate reliable tests for RF systems is by performing direct measurements on hardware. At the same time, inserting test points for such circuits while maintaining signal integrity is a difficult task to achieve.
The proposed research develops a test strategy to reduce overall test cost for RF circuits. A built-in-test (BIT) approach using sensors is proposed for this purpose, which are designed into high-frequency circuits. The work develops algorithms for selecting optimal test access points, and the stimulus for testing the DUT. The test stimulus can be generated on-chip, through efficient design reuse or using custom built circuits. The test responses are captured and analyzed by on-chip sensors, which are custom designed to extract test response features. The sensors, which have low silicon area overhead, output either DC or low frequency test response signals and are compatible to low-speed testers; hence are low-cost. The specifications of the system are computed using a set of nonlinear models developed using the alternate test methodology. The whole approach has been applied to a RF receiver at 1 GHz, used as a test vehicle to prove the feasibility of the proposed approach. Finally, the method is verified through measurements made on a large number of devices, similar to an industrial production test situation. The proposed method using sensors estimated system-level as well as device-level specifications very accurately in the emulated production test environment with a significantly smaller test cost than existing production tests.
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Zhao, Wei. "Development of CMOS sensor with digital pixels for ILD vertex detector". Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAE004/document.
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La thèse présente le développement de CPS (CMOS Pixel Sensors) intégré avec CAN au niveau du pixel pour les couches externes du détecteur de vertex de l’ILD (International Large Detector). Motivé par la physique dans l’ILC (International Linear Collider), une précision élevée est nécessaire pour les détecteurs. La priorité des capteurs qui montre sur les couches externes est une faible consommation d’énergie en raison du rapport élevé de couverture de la surface sensible (~90%) dans le détecteur de vertex. Le CPS intégré avec CAN est un choix approprié pour cette application. L’architecture de CAN de niveau colonne ne fournit pas une performance optimisée en termes de bruit et la consommation d’énergie. La conception de CAN au niveau du pixel a été proposée. Bénéficiant des sorties de pixels tout-numérique, CAN au niveau des pixels présentent les mérites évidents sur le bruit, la vitesse, la zone sensible et la consommation d’énergie. Un prototype de capteur, appelé MIMADC, a été implémenté par un processus de 0.18 μm CIS (CMOS Image Sensor). L’objectif de ce capteur est de vérifier la faisabilité du CPS intégré avec les CAN au niveau des pixels. Trois matrices sont incluses dans ce prototype, mais avec deux types différents de CAN au niveau de pixel: une avec des CAN à registre à approximations successives (SAR), et les deux autres avec des CAN à une seule pente (Single-Slope, SS) CAN. Toutes les trois possédant les pixels de la même taille de 35×35 μm2 et une résolution de 3-bit. Dans ce texte, des analyses théoriques et le prototype sont présentés, ainsi que la conception détaille des circuitsThis thesis presents the development of CMOS pixel sensors (CPS) integrated with pixel-level ADCs for the outer layers of the ILD (International Large Detector) vertex detector. Driven by physics in the ILC (International Linear Collider), an unprecedented precision is required for the detectors. The priority of the sensors mounted on the outer layers is low power consumption due to the large coverage ratio of the sensitive area (~90%) in the vertex detector. The CPS integrated with ADCs is a promising candidate for this application. The architecture of column-level ADCs, exists but do not provide an optimized performance in terms of noise and power consumption. The concept of pixel-level ADCs has been proposed. Benefiting from the all-digital pixel outputs, pixel-level ADCs exhibit the obvious merits on noise, speed, insensitive area, and power consumption. In this thesis, a prototype sensor, called MIMADC, has been implemented by a 0.18 μm CIS (CMOS Image Sensor) process. The target of this sensor is to verify the feasibility of the CPS integrated with pixel-level ADCs. Three matrices are included in this prototype but with two different types of pixel-level ADCs: one with successive approximation register (SAR) ADCs, and the other two with single-slope (SS) ADCs. All of them feature a same pixel size of 35×35 μm2 and a resolution of 3-bit. In this thesis, the prototype is presented for both theoretical analyses and circuit designs. The test results of the prototype are also presented
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O'Brien, Geoffrey William. "The Development and Implementation of a Multimedia Program that Uses Analogies in Senior High School Chemistry to Enhance Student Learning of Chemical Equilibrium". Thesis, Curtin University, 2002. http://hdl.handle.net/20.500.11937/2106.
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In this thesis, you will find a review the development process of a multimedia presentation designed to assist the teaching of chemical equilibrium using analogies. The objective of this thesis is to report on the process of designing animated analogies and the subsequent employment of these analogies in a teaching program for grades 11 and 12 students. This thesis describes a case study in the effective use of technology in the classroom based on established research in the field of analogical thinking. The work begins with a review of relevant literature from the fields of constructivism, collaborative learning and multimedia in education. The design phase of the research sought to discover if analogies for chemical equilibrium could be successfully transferred to a multimedia presentation on a computer. The subsequent testing of the software endeavoured to discover the most appropriate teaching strategies and if the use of such a program could enhance the learning process for students. The work resulted in a completed CDROM with full teaching program included which you will find attached to this thesis. The results indicate that the experience was a positive one and that there is some evidence to show increased ability in the students in their attempts to understand a conceptually difficult area of chemistry theory.
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Pastorelli, Cédric. "Conception d'un convertisseur Analogique-numérique à rampe par morceaux pour capteur d'image avec techniques de calibration". Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT083/document.
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Le travail de cette thèse vise la réalisation d’un nouveau capteur d’images pour mobile en technologie CMOS (Complementary Metal Oxide Semiconductor). Ce capteur a été développé en vue de répondre à une forte demande du marché. Les prochaines générations de produits, nécessitent des capteurs d’image avec des performances agressives. Par exemple, le niveau de qualité d’image peut être fortement amélioré avec des architectures faible bruit, ou l’utilisation de nouvelles technologies, pour augmenter le niveau du signal ou diminuer la consommation. L’augmentation de la qualité d’image entraîne un agrandissement de la taille des matrices de pixels, et de la résolution des données. La vitesse de conversion devient donc critique. Le sujet de cette thèse porte sur l’amélioration de ce dernier point. Une étude comparative a été réalisée pour étudier différentes architectures. Le convertisseur à rampe est le mieux adapté pour les petits pixels. Toutefois, son principal inconvénient est son temps de conversion qui nécessite 2N cycles d’horloge. Afin d’obtenir un frame rate plus élevé, une méthode tirant profit du bruit photonique a été proposée. Ce circuit de lecture est fondé sur un convertisseur à rampe par morceaux, et un algorithme qui permet la linéarisation des données. Afin de réduire le bruit, cette nouvelle architecture doit prendre en compte le double échantillonnage corrélé digital. Durant la période de conception, des modes de test ont été mis en place pour permettre la caractérisation du circuit. L’innovation se trouve dans le développement d’une rampe par morceaux qui réduit le temps de lecture d’une ligne de 1us. Cependant, ce développement a besoin d’une calibration adaptée. Un prototype de capteur d’image CMOS de 13Mpixel a été fabriqué en 65 nm, 5 niveaux de métaux, et 1 seul niveau de poly en technologie CMOS standard. Les mesures ont montré que l’INL et DNL du convertisseur étaient aussi performantes qu’avec une rampe linéaire classique. Une attention particulière a été apportée sur la mesure du bruit. Malheureusement, le bruit s’est montré plus élevé qu’avec un capteur « classique ». Cependant, la consommation reste identique en ayant une vitesse de conversion plus rapide. Les solutions proposées sont simples à intégrer structurellement, et faciles à mettre en œuvre. Elles ont l’avantage de ne pas impacter la surface du pixel et préservent donc les performances de ce dernier. Les résultats issus des mesures sur silicium sont très encourageants, car on obtient un gain de presque 20% sur le temps de lectureThe aim of this thesis is the implementation of new image sensors for mobile in CMOS (Complementary Metal Oxide Semiconductor) technology to meet strong market demand. Next generations of products require image sensors with high performances.These improvements would change the image quality with low noise architecture in one hand, and the use of new technologies to increase the signal level, or reduce the power consumption in the other hand. The gain in image quality leads to increase the size of the pixel’s array, and the resolution of the data -the conversion speed becoming critical-. The subject of this thesis focuses on improving this latter point. A comparative study has been made between several architectures to find the best solution that would fit our needs.The ramp converter is the most suitable for small pixels, but his main drawback is the conversion time that requires 2N clock cycles. To obtain a higher frame rate, a method taking advantage of the photon noise has been presented. This readout circuit is based on a piecewise linear ramp converter and an algorithm that allows the linearization of the data. Furthermore, for noise reduction, the new architecture must take into account the digital correlated double sampling. During the period of design, test modes have also been designed and implemented to allow characterization of the circuit.The innovative part is the use of a piecewise linear ramp, which in simulation, reduces the readout time of 1us per row. However, this element needs calibration. A CMOS image sensor prototype of 13Mpixel has been made in 65 nm, 5 levels of metals, and 1 level of poly standard CMOS technology. Measurements showed that the INL and DNL of the converter were as good as with a conventional linear ramp. A careful consideration has been given to the measurement of noise, which unfortunately is higher than a "conventional" sensor. However, the consumption remains the same while having a faster conversion speed. The solutions are simple to integrate structurally and easy to implement. They have the advantage of not affecting the surface of the pixel, thus preserve the performance of the latter. The results found from the silicon-on measures are very encouraging, we gain almost 20% of the conversion time
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Thiele, Rodney B. "Textbook authors', teachers' and students' use of analogies in the teaching and learning of senior high school chemistry". Thesis, Curtin University, 1995. http://hdl.handle.net/20.500.11937/2190.
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This thesis reports a series of studies into textbook authors', teachers' and students' use of analogies to improve students' understanding of abstract chemistry concepts. The five research problems considered: (a) the nature and extent of analogy use in textbooks; (b) the views of textbook authors and editors concerning analogies; (c) how, when, and why analogies were used by experienced chemistry teachers; (d) the development of an instrument to determine chemistry students' understanding of analogies; and (e) how chemistry students use the analogies presented as part of their chemistry instruction.Study One reports the findings of an investigation of ten chemistry textbooks used by Australian students for the nature and extent of analogy inclusion. The study found that, while used sparingly, analogies were employed more frequently in the beginning of textbooks and that the analogies used concrete analog domains to describe abstract target concepts. There was considerable use of pictorial-verbal analogies although simple analogies comprised a substantial proportion and stated limitations or warnings were infrequently employed.Study Two involved interviews with the authors of eight of the above mentioned textbooks to determine authors' views on analogies and their use in textbooks and teaching. The study identified a relationship between how frequently analogies were used by the author and what he or she considered to be the characteristics of a good chemistry teacher. Each author had a good understanding of the nature of analogy and each sought a flexible environment for its use - most arguing that analogies are better used by teachers than printed in textbooks. They appeared to favour analogies embedded in text or placed in margins rather than as post-synthesisers or advance organisers.Study Three reports an investigation into six chemistry teachers' use of analogies in Western Australia and England. This study found that the teachers drew upon their experiences and professional reading as sources of the analogies that tended to be spontaneously used when they felt their students had not understood an explanation. The analogies tended to map functional attributes of abstract target concepts with some teachers using the blackboard to illustrate pictorial analogies and some including statements of limitations.Study Four describes the development of analogy maps - instruments used to determine the effectiveness with which students map given analogies. The iterative development process engaged classroom-based research methods to develop an instrument of value both for teaching and for school-related research. A rating system enables researchers to compare students' effectiveness at mapping analogies with variables such as analogy type.Studies Five and Six describe how a combination of interviews and analogy map surveys were used to investigate how students used analogies in chemistry. The study found that students felt more confident with pictorial-verbal analogies although they were not necessarily able to map these analogies better than verbal (only) analogies. Also, student mapping confidence appeared not to depend upon the level of enrichment supplied and added enrichment did not necessarily aid mapping performance. Further, the analogy maps were useful as a means to identify alternative conceptions and there was little evidence that the analogy maps contributed to the formation of alternative conceptions in the learners.The final chapter draws together and discusses the assertions made in all of the previous studies before considering the contribution of the thesis to theory building. The implications of the research are discussed and suggestions made for future research on analogies in chemistry education. The chapter concludes by outlining examples of how and where the findings of this research have begun to be disseminated.
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Tompkins, Nicholas William. "Design of a Machine Condition Monitoring System with Bluetooth Low Energy". Thesis, University of North Texas, 2017. https://digital.library.unt.edu/ark:/67531/metadc984239/.
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Sicard, Gilles. "DDe la biologie au silicium : une retine bio-inspiree analogique pour un capteur de vision "intelligent" adaptatif". Grenoble INPG, 1999. http://www.theses.fr/1999INPG0020.
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Dans les systemes de traitement d'images, le capteur de vision est un composant de phototransduction dont le role est de convertir un signal lumineux en un signal electrique. L'evolution des technologies micro-electroniques permet actuellement d'integrer un ensemble de transistors autour de l'element photosensible. Ceci est le fondement architectural du capteur de vision intelligent qui associe phototransduction et traitement d'images dans le plan focal. Ce circuit est compose d'une matrice de cellules de traitement photosensibles ou pixels, interconnectes entre proches voisins, qui forment un reseau qui effectue des taches de vision precoce, dites aussi de bas-niveau. Notre reseau est inspire d'un modele electrique analogique de la retine des vertebres. Celui-ci est un filtre spatiotemporel analogue a celui releve en biologie. Il effectue une extraction de contours et une detection des objets en mouvement. Le pixel integre un systeme bio-inspire d'adaptation aux conditions lumineuses. En fonction de la luminosite moyenne, il optimise la phototransduction et adapte la fonction de transfert du filtre. Il en resulte une sensibilite aux contrastes amelioree et une robustesse au bruit accrue dans des conditions de faibles luminosites. Une matrice de 64 64 pixels a ete concue en technologie cmos 0. 5um. Ce capteur de vision analogique de 70mm#2 permet, en temps reel, une extraction de contours efficace et une detection de mouvement sur une large gamme de vitesse. Un circuit de test a permis de montrer l'apport de l'adaptation aux conditions lumineuses. Ces capteurs de vision, utilises dans une camera, montrent l'interet et l'efficacite de leur filtrage. Les interfaces de la matrice ont ete concus de maniere a faciliter l'emploi de ces circuits dans des systemes de vision artificielle. Cela permettra de mettre en evidence les avantages lies a leur utilisation dans des applications de teledetection, de reconnaissance de formes, de visiophonie, de conduite de robot
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Holík, Tomáš. "Distribuované optické vláknové senzory". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-377017.
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The thesis deals with the possibility of using optical fiber as a sensor. The introduction of the thesis is devoted to the foundations of optics. In addition, the thesis deals with optical interferometry, polarization and dispersion in optical fiber. The main output of the thesis is the comparison of acoustic vibration measurements using interferometric and polarization methods and further measurements on the real route in Brno.
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PICCOLO, LORENZO. "An Analog Pixel Front-End for High Granularity Space-Time Measurements". Doctoral thesis, Politecnico di Torino, 2022. https://hdl.handle.net/11583/2975704.
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Ben, aziza Sassi. "Etude d'un système de conversion analogique-numérique rapide de grande résolution adapté aux nouvelles générations de capteurs d'images CMOS". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT056.
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Les technologies CMOS représentent aujourd’hui plus de 90% du marché des capteurs d’images : elles permettent d’intégrer des systèmes intelligents dans une seule puce (SoC = System-On-Chip) et ouvrent la voie à l’intégration d’algorithmes de plus en plus complexes dans les dernières générations de capteurs. Des techniques telles que la reconstruction grande dynamique nécessitent d’acquérir plusieurs images avec un même capteur et de les recombiner. Ces nouvelles contraintes nécessitent d’augmenter drastiquement le débit d’images pour des capteurs de tailles conséquentes (Jusqu'à 30 Mpixels), ainsi que d’augmenter la résolution du convertisseur analogique numérique (jusqu’à 14 bits). Cela crée une demande forte en techniques de conversion analogique-numérique. Ces techniques doivent obéir en même temps aux contraintes de performance notamment la vitesse, la résolution, le faible bruit, la faible consommation et l'intégrabilité mais aussi aux contraintes de qualité d'image impactées directement par la chaine de conversion analogique-numérique en plus de la technologie du pixel. D'ici découle une double problématique pour le sujet:- Etudier et déterminer les limites atteignables en termes de performance sur les différents axes précités.- Gestion du fonctionnement massivement parallèle lié à la structure inhérente des capteurs d'image en vue d'avoir une qualité d'image irréprochableCMOS technologies represent nowadays more than 90% of image sensors market given their features namely the possibility of integrating entire intelligent systems on the same chip (SoC = System-On-Chip). Thereby, allowing the implementation of more and more complex algorithms in the new generations of image sensors.New techniques have emerged like high dynamic range reconstruction which requires the acquisition of several images to build up one, thus multiplying the frame rate.These new constraints require a drastic increase of image rate for sensors ofconsiderable size (Up to 30 Mpix and more). At the same time, the ADCresolution has to be increased to be able to extract more details (until 14 bits).With all these demanding specifications, analog-to-digital conversion capabilities have to be boosted as far as possible.These capabilities can be distinguished into two main research axes representing the pillars of the PhD work, namely:+ The study of the reachable limits in terms of performance: Speed, Resolution,Low Noise, Low power consumption and small design pitch.+ The management of the highly parallel operation linked to the structure of animage sensor. Solutions have to be found so as to avoid image artefacts andpreserve the image quality