Tesis sobre el tema "Amplificateur à gain variable"
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Fechine, Sette Elmo Luiz. "Circuits intégrés millimétriques en bande Ka pour une antenne à pointage électronique pour les télécommunications avec des satellites géostationnaires ou des constellations de satellites". Electronic Thesis or Diss., Limoges, 2024. http://www.theses.fr/2024LIMO0002.
Texto completoThis work presents the design of active integrated circuits intended for integration into an electronically steered antenna for Ka-band satellite communications. Firstly, the manuscript introduces the context of the study, discussing the main concepts and characteristics of this type of antenna. Subsequently, two key blocks of the transmission chain are studied in detail and designed: a variable gain power amplifier and three controllable phase shifters. The circuits are implemented using two SiGe BiCMOS technologies: BiCMOS9MW and SG13G2. Finally, the post-layout simulation results are presented and compared to the project specifications as well as the state of the art
Deza, Julien. "Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm". Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0680/document.
Texto completoThis thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation
Haghighitalab, Delaram. "Récepteur radio-logicielle hautement numérisé". Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066443.
Texto completoNowadays there is an increase in the number of standards being integrated in mobile devices. The main issues are battery life and the size of the device. The idea of a Software Defined Radio is to push the digitization process as close as possible to the antenna. Having most of the circuit in the digital domain allows it to be reconfigurable thus requiring less area and power consumption. In this thesis, we present the first implementation of a complete SDR receiver based on RF bandpass Sigma-Delta including a Variable-Gain LNA (VGLNA), an RF subsampled Sigma-Delta ADC, an RF digital down-conversion mixer and a polyphase multi-stage multi-rate decimation filter. VGLNA enlarges the dynamic range of the multi-standard receiver to achieve the requirements of the three targeted wireless standards. Also a mixed architecture, using both Source-Coupled Logic (SCL) and CMOS circuits, is proposed to optimize the power consumption of the RF digital circuits. Moreover, we propose a multi-stage comb filter architecture with polyphase decomposition to reduce the power consumption. The receiver is measured for three different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79 dB, 73 dB and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply. Compared to other SDR receivers, the proposed circuit consumes 30% less power, the DR is 21 dB higher, IIP3 is 6 dB higher and the overall Figure of Merit is 24 dB higher
Haghighitalab, Delaram. "Récepteur radio-logicielle hautement numérisé". Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066443.
Texto completoNowadays there is an increase in the number of standards being integrated in mobile devices. The main issues are battery life and the size of the device. The idea of a Software Defined Radio is to push the digitization process as close as possible to the antenna. Having most of the circuit in the digital domain allows it to be reconfigurable thus requiring less area and power consumption. In this thesis, we present the first implementation of a complete SDR receiver based on RF bandpass Sigma-Delta including a Variable-Gain LNA (VGLNA), an RF subsampled Sigma-Delta ADC, an RF digital down-conversion mixer and a polyphase multi-stage multi-rate decimation filter. VGLNA enlarges the dynamic range of the multi-standard receiver to achieve the requirements of the three targeted wireless standards. Also a mixed architecture, using both Source-Coupled Logic (SCL) and CMOS circuits, is proposed to optimize the power consumption of the RF digital circuits. Moreover, we propose a multi-stage comb filter architecture with polyphase decomposition to reduce the power consumption. The receiver is measured for three different standards in the 2.4 GHz ISM-band. Measurement results show that the receiver achieves 79 dB, 73 dB and 63 dB of dynamic range for the Bluetooth, ZigBee and WiFi standards respectively. The complete receiver, implemented in 130 nm CMOS process, has a 300 MHz tunable central frequency and consumes 63 mW under 1.2 V supply. Compared to other SDR receivers, the proposed circuit consumes 30% less power, the DR is 21 dB higher, IIP3 is 6 dB higher and the overall Figure of Merit is 24 dB higher
Dasgupta, Abhijeet. "High efficiency S-Band vector power modulator design using GaN technology". Thesis, Limoges, 2018. http://www.theses.fr/2018LIMO0021/document.
Texto completoThe evolution of telecommunications systems, linked to a constantly increasing demand in terms of data rate and volume, leads to the development of systems offering very wide bandwidths, modulations with very high spectral efficiencies, increased power and frequency flexibilities in transmitters. Moreover, the implementation of such systems must be done with a permanent concern for energy saving, hence the recurring goal of the RF power amplification which is to combine the best efficiency, linearity and bandwidth. Conventional architectures of RF emitter front-ends consist in a first step in performing the frequency modulation-conversion operation (IQ Modulator) and then in a second step the DC-RF energy conversion operation (Power Amplifier), these two steps being usually managed independently. The aim of this thesis is to propose an alternative approach that consists in combining these two operations in only one function: a high efficiency vector power modulator. The core of the proposed system is based on a two-stage GaN HEMT circuit to obtain a variable power gain operating at saturation. It is associated with a specific multi-level bias modulator also design using GaN technology. The fabricated device generates, at a frequency of 2.5 GHz, a 16QAM modulation (100Msymb/s) with 13W average power, 25W peak power, with an overall efficiency of 40% and 5% EVM
Ayad, Mohammed. "Etude et Conception d’amplificateurs DOHERTY GaN en technologie Quasi - MMIC en bande C". Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0027.
Texto completoThis work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier
Lablonde, Laurent. "Etude des non-linéarites de gain d'un amplificateur optique à semi-conducteur". Limoges, 1996. http://www.theses.fr/1996LIMO0029.
Texto completoOksasoglu, Ali 1960. "GAIN-BANDWIDTH EFFECTS IN THE STATE-VARIABLE FILTERS". Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276419.
Texto completoRahmatian, Behnoosh. "A 75-dB digitally programmable CMOS variable gain amplifier". Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/32248.
Texto completoApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Jha, Nand Kishore. "Design of a complementary silicon-germanium variable gain amplifier". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.
Texto completoMoreau, Aurélie. "Réseaux de Bragg intracavité en milieu amplificateur". Phd thesis, Télécom ParisTech, 2006. http://pastel.archives-ouvertes.fr/pastel-00001975.
Texto completoKrishnanji, Sivasankari. "Design of a variable gain amplifier for an ultrawideband receiver". Texas A&M University, 2005. http://hdl.handle.net/1969.1/2576.
Texto completoBohémond, Christian. "Mélangeur de signaux hyperfréquences basé sur la modulation croisée du gain d’un amplificateur optique à semi-conducteurs". Brest, 2010. http://www.theses.fr/2010BRES2023.
Texto completoThe Semiconductor Optical Amplifier (SOA) is a multifunctional device that can be integrated into a Radiofrequency-optical link and carry out all-optical functions. In this study, the SOA is used as a hyperfrequency (HP) converter based on Cross Gain Modulation (XGM). Two architectures have been studied: an SOA is firstly used as an all-optical microwave mixer and secondly as an electro-optical mixer. This study is realized both experimentally and theoretically both with small-signal modelling and a model developed under ADS software (Agilent Technologies). The theoretical results have been compared to the simulation results obtained with the aid of ADS and to the experimental results. All the obtained results are in good agreernent and the SOA model developed under ADS has been validated and uses throughout this study. We have measured the static and dynamic performances and the linearity of the all-optical mixer. The conversion gain has been studied with different parameters of the mixer and we have proved that it is directly related to the optical gain of SOA. The Amplified Spontaneous Emission (ASE) generated by the SOA acts as an optical modulated source participing in mixing phenomenon. The phase noise of the converted signal has been also analyzed. The two mixers allow the conversion of digital signals with complex modulation formats (QPSK, 16 and 64 QAM). An effective conversion with a positive conversion gain, without significant distortion or degradation of the converted numerical data, has been found, proving the ability of our mixers to be used as a part of a complete communication system
Feng, Mabel Y. "Frequency translation method for low frequency variable gain amplification and filtering". Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/41642.
Texto completoIncludes bibliographical references (leaves 75-78).
This thesis discusses an innovative solution to an industry challenge. A frequency translation method is designed to shift low frequency signals to intermediate frequencies in order to utilize higher-frequency components. This solution, appropriate for applications involving 1-10MHz signals, can provide continuously variable gain and filtering at little cost in dynamic performance. The working system converts the low frequency signals up to the 70MHz band to achieve up to 28dB attenuation and 60-86MHz variable filtering. A Single Side Band system has a Signal-to-Noise Ratio (SNR) of 71dB with a 73dB SNR Analog-to-Digital Converter (ADC), 44 dB Output Third-Order Intercept Point (OIP3), and a Noise Figure (NF) of 14dB. Ultrasound and other applications in the 1-10MHz range benefit greatly from this upconversion scheme.
by Mabel Y. Feng.
M.Eng.
Diab-el-Arab, Hilda. "Conception et réalisation d'un filtre actif de type RC utilisant un amplificateur de gain fini en technologie MMIC". Paris 11, 2001. http://www.theses.fr/2001PA112330.
Texto completoThis work deals with the design of analog biquadratic filters using voltage amplifiers. This study results from the transposition of such filter into microwaves. At first the filter was studied in its holistic struture in order to obtain its optimal configuration. By choosing wisely passive elements values of the later a band-pass filter was realized, which is stable accordable and simple to integrate in other cellular elements. However, this filter is highly sensitive to its constitutive elements. Among the elements that might influence the filter performance is the no-ideality of the amplifier. These things were examined and it was revealed that the no-ideality impair the filter fonction. Furthermore, a major part of this study focused on searching for a topology of a finite gain amplifier based on a feedback principle. .
Lo, Keng Wai. "Wideband active-balun variable-gain low-noise amplifier for mobile-TV applications". Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2148237.
Texto completoDe, Souza Marcelo. "Conception d'amplificateur faible bruit reconfigurable en technologie CMOS pour applications de type radio adaptative". Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0295/document.
Texto completoMobile communication systems allow exploring information in complex environments by means of portable devices, whose main restriction is battery life. Once battery development does not follow market expectations, several efforts have been made in order to reduce energy consumption of those systems. Furthermore, radio-frequency systems are generally designed to operate as fixed circuits, specified for RF link worst-case scenario. However, this scenario may occur in a small amount of time, leading to energy waste in the remaining periods. The research of adaptive radio-frequency circuits and systems, which can configure themselves in response to input signal level in order to reduce power consumption, is of interest and importance. In a RF receiver chain, Low Noise Amplifier (LNA) stand as critical elements, both on the chain performance or power consumption. In the past some techniques for reconfigurable LNA design were proposed and applied. Nevertheless, the majority of them are applied to gain control, ignoring the possibility of linearity and noise figure adjustment, in order to save power. In addition, those circuits consume great area, resulting in high production costs, or they do not scale well with CMOS. The goal of this work is demonstrate the feasibility and advantages in using a digitally controlled LNA in a receiver chain in order to save area and power
Os sistemas de comunicação móveis permitem a exploração da informação em ambientes complexos através dos dispositivos portáteis que possuem como principal restrição a duração de suas baterias. Como o desenvolvimento da tecnologia de baterias não ocorre na velocidade esperada pelo mercado, muitos esforços se voltam à redução do consumo de energia dos circuitos eletrônicos destes sistemas. Além disso, os sistemas de radiofrequência são em geral projetados para funcionarem de forma fixa, especificados para o cenário de pior caso do link de comunicação. No entanto, este cenário pode ocorrer em uma pequena porção de tempo, resultando assim no restante do tempo em desperdício de energia. A investigação de sistemas e circuitos de radiofrequência adaptativos, que se ajustem ao nível de sinal de entrada a fim de reduzir o consumo de energia é assim de grande interesse e importância. Dentro de cadeia de recepção de radiofrequência, os Amplificadores de Baixo Ruído (LNA) se destacam como elementos críticos, tanto para o desempenho da cadeia como para o consumo de potência. No passado algumas técnicas para o projeto de LNA reconfiguráveis foram propostas e aplicadas. Contudo, a maioria delas só se aplica ao controle do ganho, deixando de explorar o ajuste da linearidade e da figura de ruído com fins de economia de energia. Além disso, estes circuitos ocupam grande área de silício, resultando em alto custo, ou então não se adaptam as novas tecnologias CMOS de baixo custo. O objetivo deste trabalho é demonstrar a viabilidade e as vantagens do uso de um LNA digitalmente configurável em uma cadeia de recepção de radiofrequência do ponto de vista de custo e consumo de potência
Ehteshamuddin, Mohammed. "Design of a High Temperature GaN-Based Variable Gain Amplifier for Downhole Communications". Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/74958.
Texto completoMaster of Science
Richard, Gaetan C. y Daniel G. Gonzales. "A NEW VARIABLE BEAMWIDTH ANTENNA FOR TELEMETRY TRACKING SYSTEMS". International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/608402.
Texto completoThis paper presents a new variable beamwidth antenna designed for use in telemetry tracking systems when a high gain/low gain antenna configuration is required. This antenna can be commanded to continuously vary its beamwidth between a high gain/narrow beamwidth mode of operation and a low gain/ wide beamwidth mode of operation. A design goal of a 4:1 increase in beamwidth has been set and a 3.0:1 increase has been achieved without causing any significant degradation in the shape of the antenna patterns and without generating exceedingly high sidelobes in the low gain setting. The beamwidth variation occurs continuously without any loss of data, boresight shift or jitter such as experienced with the operation of conventional implementations of the high gain/low gain antenna technique.
Al-Sweiti, Yousef M. "Modeling and control of an elastic ship mounted crane using variable gain model based controller". [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=980984157.
Texto completoChen, Lin. "A low power, high dynamic-range, broadband variable gain amplifier for an ultra wideband receiver". Texas A&M University, 2003. http://hdl.handle.net/1969.1/5843.
Texto completoAmaya, Mohammad. "Amélioration des performances d'un amplificateur optique à semi-conducteurs par injection optique à la transparence du gain pour les réseaux de télécommunications optiques". Brest, 2006. http://www.theses.fr/2006BRES2025.
Texto completoSemiconductor optical amplifier (SOA) is an attractive component for future metropolitan multicolor all-optical telecommunication networks. This work focuses on the theoretical and experimental study of the SOA static and dynamic performances, when injecting a continuous wave (CW) high power as a holding beam (HB) at the gain transparency wavelength into its cavity with the aim of pointing out the interesting effects of this technique. Our work has shown that employing the holding beam, improves the soa saturation output power, the carrier lifetime and the device gain recovery time, over a wideband of incident signal wavelengths and powers without sacrificing the amplifier gain level neither degrading its noise figure (NF). Our theoretical and experimental results point out that injecting the holding beam in counter-propagative configuration with respect to the optical incident signal is more efficient than that in co-propagative one. We have employed the holding beam injection in an SOA based WDM multichannel transmission system with the purpose of reducing the cross-gain modulation (XGM) induced inter-channel crosstalk, hence, of improving the signals bit error rate (BER). Finally, a simulation model which gives results close to the measured ones has been obtained during this work as well
Azmat, Rehan. "Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers". Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449.
Texto completoMitra, Dipankar. "A Variable High Gain and High Dynamics Range CMOS Phase Shifter for Phased Array Antenna Applications". Thesis, North Dakota State University, 2016. https://hdl.handle.net/10365/28033.
Texto completoND NASA EPSCoR under the agreement FAR0020852
Zhou, Hao. "Numerical Investigation of the Nonlinear Dynamics of a Hybrid Acousto-Optic Bragg Cell with a Variable Feedback Gain". University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1406666390.
Texto completoMimeche, Naamane. "Conception assistée par ordinateur de circuits translinéaires analogiques à gain controlé et applications au filtrage". Châtenay-Malabry, Ecole centrale de Paris, 1994. http://www.theses.fr/1994ECAP0343.
Texto completoHäkkinen, J. (Juha). "Integrated RF building blocks for base station applications". Doctoral thesis, University of Oulu, 2003. http://urn.fi/urn:isbn:951426908X.
Texto completoPATEL, PRERNA D. "DESIGN OF A PIXEL SCALE OPTICAL POWER METER SUITABLE FOR INCORPORATION IN A MULTI-TECHNOLOGY FPGA". University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1066421274.
Texto completoLind, Fredrik y Escalante Andrés Diaz. "Maximizing performance gain of Variable Rate Shading tier 2 while maintaining image quality : Using post processing effects to mask image degradation". Thesis, Blekinge Tekniska Högskola, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-21868.
Texto completoBakgrund. Prestandaoptimering är väldigt viktigt för spel eftersom det kan begränsa möjligheterna av innehåll eller komplexitet av system. Moderna spel stödjer rendering för höga upplösningar men höga upplösningar kräver beräkningar för mera pixlar och lösningar behövs för att minska arbetsbördan. Metoder som för närvarande används omfattar bland annat enhetlig sänkning av skuggningsförhållande över hela skärmen för att minska antalet pixlar som behöver beräkningar. Variable Rate Shading är en ny hårdvarustödd teknik med flera funktionalitetsnivåer. Nivå 1 är likt tidigare metoder eftersom skuggningsförhållandet enhetligt sänks över hela skärmen. Nivå 2 stödjer skärmrymdsbildskuggning. Med skärmrymdsbildskuggning kan skuggningsförhållanden varieras utspritt över skärmen vilket ger utvecklare valmöjligheter att bestämma var och när specifika skuggningsförhållanden ska sättas. Syfte. Syftet med examensarbetet är att undersöka hur nära Variable Rate Shading nivå 2 skärmrymdsbildskuggning kan komma prestandavinsterna av Variable Rate Shading nivå 1 samtidigt som bildkvaliteten behålls acceptabel med hjälp av vanligt använda efterbearbetningseffekter. Metod. En simpel scen skapades och metoder för Variable Rate Shading nivå 2 sattes till en acceptabel bildkvalitet som utgångspunkt. Utvärdering av prestanda gjordes genom att mäta tiderna för specifika pass som behövdes för och påverkades av Variable Rate Shading. Bildkvalitet mättes genom att spara bildsekvenser utan Variable Rate Shading på som referensbilder, sedan med Variable Rate Shading nivå 1 och flera metoder med nivå 2 för att jämföras med Structural Similarity Index. Resultat. Högsta uppmätta prestandavinsten från nivå 2 var 28.0%. Resultatet kom ifrån kantdetektering för skapandet av skuggningsförhållandebilden, med upplösningen 3840x2160. Det motsvarar 36.7% av prestandavinsten för nivå 1 men med mycket bättre bildkvalitet med SSIM-värde på 0.960 gentemot 0.802 för nivå 1, vilka motsvarar bra och dålig bildkvalitet. Slutsatser. Variable Rate Shading nivå 2 visar stor potential i prestandavinster med bibehållen bildkvalitet, speciellt med kantdetektering. Efterbearbetningseffekter är effektiva på att upprätthålla en bra bildkvalitet. Prestandavinster skalar även bra då de ökar vid högre upplösningar.
Chen, Yun-ju y 陳韻如. "Design of CMOS Variable Gain Amplifier". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/47315197247618226962.
Texto completo逢甲大學
電子工程所
97
A CMOS variable gain amplifier (VGA) is presented, which consists of exponential control circuit, amplifier circuit and buffer circuit. The exponential control circuit adopts an approximate exponential equation. The amplifier circuit includes a common mode feedback circuit, the common mode feedback is required in order to prevent any of the transistors from entering linear mode operation and to maintain a specific dc value for the biasing of the next stage. The VGA is implemented in 0.35um CMOS technology and total power dissipation is 58mW at 3.3V supply. The chip size is 0.93mm2.
Wu, Wei-ruen y 吳威潤. "Voltage-Controlled Variable-Gain Optical Receiver". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/78197469140607056041.
Texto completo國立雲林科技大學
電子與資訊工程研究所
99
A Voltage-controlled variable-gain optical receiver for optical wireless communication is described. Under a photodiode capacitance of 5pF, the transimpedance gain, bandwidth, and power consumption of the optical receiver are 77dBΩ, 103MHz, and 34 mW respectively. A CMOS voltage-control resistor is adopted in the feedback transimpedance amplifier. The receiver is designed and implemented using a 0.35μm 2P4M CMOS technology with 3.3V supply voltage. The final implementation occupies a total area of 825um × 666um.
Lai, Bing-Jiun y 賴炳均. "Integrated Radio Frequency Variable Gain Amplifier". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/79487323239286597680.
Texto completo國立中正大學
電機工程所
96
The first stage of a receiver is typically a low noise amplifier, whose main features are to provide enough gain and minimize the influence to subsequent stages due to the noise generated in itself. In general, variable gain amplifier is employed for automatic gain control, which is used for automatically adjusting gain of the receiver path, so that the received RF signal can be easily processed by subsequent circuits. The requirements for the tuner front-ends are low power consumption, dB-linear, dynamic range, linearity and gain performance. The first part of this thesis is devoted itself abut the variable gain amplifier which was manufactured by the TSMC 0.18 μm CMOS process. It is applied to WiMAX system. The first one is the variable gain low noise amplifier in which the differential topology being used due to its inherent feature of low interference. The second is the variable gain amplifier, which is addressed on the high tunable gain range. It can be use in the transmitter just before the power amplifier or used in receiver after the low noise amplifier. The second part of this thesis is the wideband variable gain low noise amplifier which was fabricated by a standard TSMC 0.35 μm SiGe BiCMOS technology. In order to improve the bandwidth, two types of feedback are employed, and then using the Darlington pair to double the cutoff frequency.
Liu, Hung-Hsi y 劉洪禧. "FPGA implements variable gains control of the variable gain amplifier". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/01974566430523855947.
Texto completo中原大學
電子工程研究所
97
Field Programmable Gate Array (FPGA) can be used to implement complex logic function and provide rapid field re-programmable ability in a single chip design application. This thesis describes the use of hardware design language Verilog and the implementation of a variable gain controller in a Variable Gain Amplifier. A top-down methodology is applied in this design to make the design clearer and easier for maintenance. A look up table (LUT) mechanism is applied to realize faster computing and simplify the design complexity. The design is simulated by Modelsim and implemented by Altera FPGA EP1C6.
Wang, Lin-Sen y 王林森. "Designs of CMOS Variable Gain Amplifiers for Wide-Gain-Range Applications". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/t67e96.
Texto completo國立臺灣大學
電子工程學研究所
105
Several gain control mechanisms for the design of programmable gain amplifier (PGA) and variable gain amplifier (VGA) are presented in this thesis. In RF wireless receivers, an accurate decibel (dB)-linear PGA or VGA is required to convert the dynamic range of received signal into an acceptable range for the analog-to-digital converter (ADC). Several variable gain amplifier architectures and exponential-approximation functions are discussed and analyzed in this thesis. In order to obtain a wide dB-linear gain range, a cascading gain-error-shifting and a single-stage gain-shifting technique are proposed and adopted in the PGA and VGA, respectively. Both PGA and VGA are fabricated in the 0.18-μm CMOS process for comparison. The cascading PGA can achieve a small gain error characteristic, while the single-stage VGA can provide a better area and power performance.
Ko, Po-Ting y 柯柏廷. "Designs of CMOS Variable Gain Amplifiers for Low-Gain-Error Applications". Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bknnkc.
Texto completo國立臺灣大學
電子工程學研究所
107
Several gain control mechanisms for the design of programmable gain amplifier (PGA) and variable gain amplifier (VGA) are presented in this thesis. In wireless communication systems, the received signal changes significantly. Therefore, an accurate decibel (dB)-linear PGA or VGA is required to convert the dynamic range of received signal into an acceptable range for the analog-to-digital converter (ADC). Several variable gain amplifier architectures and exponential-approximation functions are discussed and analyzed in this thesis. In order to obtain the characteristics of wide dB-linear gain range and small gain error, the gain-range-compensating technique and a pseudo-exponential approximation method are proposed and adopted in the cascading PGA and the single-stage VGA, respectively. Both PGA and VGA are fabricated in the 0.18-μm CMOS process. The cascading PGA occupies an area of 0.08 mm2, consuming a dc power of 3.83 mW. A gain range of 69.9 dB with 0.21 dB gain error is achieved. The 3-dB bandwidth is measured from 19 MHz to 315 MHz in the maximum and minimum gain setting, respectively. The single-stage VGA occupies an area of 0.035 mm2. The power consumption of the core circuit is 0.92 mW. A gain range of 40.2 dB with 0.35 dB gain error is achieved. The 3-dB bandwidth is measured from 20.9 MHz to 240 MHz in the maximum and minimum gain setting, respectively.
Chen, Hsin-Hao y 陳信豪. "Variable Gain Amplifier for Ultrasound Imaging Receiver". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/26783570570803995937.
Texto completo陳東山. "Radio frequency heterojunctio bipolar transistor variable frequency oscillator and variable gain amplifier". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/93466629235737130612.
Texto completo國立中興大學
電機工程學系
91
Fabricated through a GaInP/GaAs HBT technology, a monolithic variable frequency oscillator (VFO) and a monolithic variable gain amplifier (VGA) were measured and reported in this thesis. A number of issues on the VFO and VGA were detailed as well. A new circuitry, called a Variable Impedance Converter (VIC), was adopted to mimic a variable capacitor, which was essentially an important element for frequency tuning in a LC-based oscillator design.A negative-impedance converter not only provides the necessary negative resistance for oscillation, but also functions as the voltage level shifters for the VIC. A classic circuit, called a translinear circuit, makes full advantage of the exponential I-V characteristic to linearize the tuning curve of the VFO. No external but two on-chip inductors were used in the VFO. Several operating principles for a VGA were explored in the VGA chapter. Based these principles we discussed, a wide gain control range VGA was achievable. The designed VGA consisted of a fixed gain preamplifier, a variable attenuator, and a tunable transconductance common-emitter (CE) amplifier, in which the input impedance is also controllable by a voltage controlled resistor. Therefore, by cleverly composing these functions of the controllable components, a low noise VGA with 50dB gain control range result.
Liu, Bang-Zhi y 劉邦志. "Implementation of 6-Bit Digital control Variable Gain Amplifier with High Linear Gain". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/40855833975865745996.
Texto completo中華大學
電機工程學系碩士班
102
The propose of this thesis is to design and implement the circuits of a Digital control Variable Gain Amplifier with High Linear Gain. We use HSPICE and MATLAB for circuit simulation and analysis. Circuit layout is used the Laker which provided by CIC. The Chip is fabricated by TSMC 0.18 um CMOS process. In this thesis, the variable gain amplifier is divided into two parts: Amplifier circuit and control circuit. The amplifier circuit is designed by exponential function which approximated by second order Taylor’s polynomial. The control circuit is designed by one set of segmentation control circuit. The amplifier circuit is designed by four sets of second order Taylor’s polynomial circuit at different input points and one set of segmentation control circuit. The simulated result is based on the input range of -10μA to 10μA, the power supply of 1.8V and the linear gain error within±0.5dB. The linear gain range is 108dB, the bandwidth is 37MHz to 268MHz, the power consumption is from 7.8mW to 10.1mW and the area of chip is 0.432*0.32(mm2).
Tsou, Shan-Chih y 鄒善智. "CMOS Variable Gain Amplifier for Multi-Standard Receiver". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/31899508987093420198.
Texto completo國立清華大學
電機工程學系
92
With the rapid growth of higher data rate, integrating the analog circuit block with wide bandwidth in the baseband will be an indispensable trend in the future. On the other hand, a single circuit block which can be used for multi-standard receiver is an economic implementation way to enhance the usability of the cell phone. A CMOS variable gain amplifier (VGA) for multi-standard receiver described in this thesis aims to meet these two demands. In general, VGA is controlled by an automatic gain control (AGC) loop. As the data rate increases, the data slot which is used for the AGC loop to settle is getting smaller. A fast gain settling of the AGC loop becomes more and more important to make sure the data transfer is correct. The performance of the AGC loop can be characterized not only by a fast gain settling, but also the precise gain settling, the stable gain settling, and a low-distortion output signal. Alinear model of the AGC loop is set up and simulated with the performance of VGA modeled as the proposed one to see the dynamics of the loop. In this thesis, a proposed VGA for the multi-standard receiver is analyzed, designed, and implemented using the standard 0.18um 1P6M CMOS technology. The output signal of the VGA can be of constant signal level and contant group delay. The bandwidth of the VGA is extended from GSM 100KHz, WCDMA 2MHz to WLAN 10MHz, and designed to be adjustable for the noise and linearity concern of the total architecture. The gain of tha VGA ranges from -10dB to 20dB, and the constant bandwidth peroperty with different gain settings helps the simplification of DSP circuitry in the baseband. The total power consumption of the VGA is 2.43mW at 1.8V supply voltage. The chip area is 0.645mm x 0.465mm.
Song, Guang-Fong y 宋光峰. "The Design of A Variable Gain Instrumentation Amplifier". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/24520553586227143218.
Texto completo中原大學
電子工程學系
87
A variable gain instrumentation amplifier (IA) has been designed in this thesis. Buffered two-stage operational amplifier and poly resistors construct the core of the instrumentation amplifier. In order to obtain good amplifier performance, the circuit configuration of the IA and its output stage, the offset and noise effects have been analyzed and investigated in this thesis. We also present key layout methods such as common-centroid structure, dummy device and guard-ring option for differential input transistor pair, compensated capacitor and poly resistors. Full custom design flow has been used in the instrumentation amplifier design. The circuit has been integrated in a 0.5mm double poly double metal n-well CMOS process. In this research, several characterization methods have been developed to measure instrumentation amplifier. In order to assure the measurements, the commercial IA device has been also tested in this research. The test results show that the proposed IA has a variable gain of 0 dB to 40dB and a common-mode rejection ratio (CMRR) of more than 85dB. The minimum input offset voltage of less than 1mV has been measured. The amplifier has an acceptable die size of 810×400mm2 and its power consumption is 13mW at 5V operation.
Hu, Yun-Chung y 胡運忠. "Low Power Variable Gain Amplifier for UWB systems". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/13040808438308906179.
Texto completo中原大學
電子工程研究所
95
The booming development of the wireless communication technology in recent years make the relevant products, such as GSM, CDMA, Bluetooth, 802.11 (Wi-Fi), ZigBee and Ultra wide band (UWB) widely used in our daily life and became important research topics. This thesis proposes a Variable Gain Amplifier (VGA) that is suitable for UWB system. It consists of a main amplifier, gain control circuit, and a common mode feedback loop. The main amplifier is realized by a folded cascode amplifier with feedback and the gain control function is utilized by a source-coupled pair to realize controllable gain. A modified pseudo-exponential equation is proposed to improve the linearity of the proposed VGA. The circuit is designed and simulated in TSMC 0.18um CMOS process. The gain range of 18dB and the 3dB frequency of 610MHz at the maximum gain that meets the specification of UWB system is obtained. The power dissipation is less then 2mW at 1.8V supply voltage.
Lee, Jun-Yi y 李俊億. "Design of a variable-gain CMOS Optical Receiver". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/03963634580322183010.
Texto completo國立雲林科技大學
電子與光電工程研究所碩士班
100
A Voltage-controlled variable-gain optical receiver for optical wireless communication is described. A stable variable-gain fully-differential transimpedance feedback amplifier is designed employing a current-mode amplifier as the feedforward gain element. Using a photodiode capacitance of 5pF, the transimpedance gain, bandwidth, and power consumption of the optical receiver are 98dBΩ, 119MHz, and 88mW respectively. A voltage-control resistor is adopted in the feedback transimpedance amplifier. The receiver is designed and implemented using a 0.35μm 2P4M CMOS technology with 3.3V supply voltage. The optical receiver occupies a total chip area of 566um × 655um.
Chen, Sz-Han y 陳思涵. "A 1.5-GHz Variable-Gain Amplifier and Filter". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3kjgaf.
Texto completo國立交通大學
電子研究所
108
For the fifth generation (5G) communication system, we use variable gain amplifier (VGA) to amplifier the baseband signal at receiver and use filter to filter out noise and any other signals which are not in the signal band. After that, we use analog-to-digital converter (ADC) to convert analog signal to digital signal for digital circuits and complete the baseband front-end receiver circuit of the fifth generation communication system. This paper is about VGA and filter. ar Due to the specification of bandwidth is wider in the fifth generation communication system, we use Gm-Miller-C filter instead of switch-capacitor filter and active-RC filter to reach the specification. The Gm-Miller-C filter is more suitable for high speed system, but the main disadvantage is the worse linearity. It is the most important part for us to improve the linearity. ar The VGA structure is based on the design of Gm-Miller-C filter and we can change the value of resistors to get programmable voltage gain. We applied the VGA and Gm-Miller-C filter as a third-order baseband chain in the fifth generation communication system and get 1.5625 GHz -3dB frequency also we can change the voltage gain from 8 dB to 40 dB for each 1 dB step. Also, we use DC-offset cancellation technique with negative feedback topology. Comparing the positive and negative output voltage and feedback to the first stage after amplifier the mismatch to reduce the impact of offset. ar This design use TSMC 28 nm CMOS process and the layout area is 198.07 x 90.88 um$^{2}$. the main circuit operate at 1 V and 1.5 V for the last stage to meet the output swing of +/- 400 mV. For the input signal bandwidth is from 5 MHz to 1.5625 GHz and input swing is +/- 150 mV, we can get SFDR is more than 47 dB, SNDR is more than 36 dB and THD is more than -38 dB. The whole design consumes 48 mW.
Yang, Hui-Chen y 楊蕙甄. "A Short-Channel Variable Gain Amplifier with DC Offset Cancellation and Gain Calibration Loop". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/63026791132656734491.
Texto completo國立清華大學
電機工程學系
98
In this thesis, a short-channel variable gain amplifier with digital feedback loops is proposed. For the purpose of area saving, the entire work is implemented with minimum gate length CMOS devices. This results in severe circuit process variations. To overcome this problem, two digital feedback loops are needed for the DC offset cancellation and gain calibration. The VGA circuit is based on a fully-differential gain stage with a degeneration resistor network. The resistance of this resistor network is digitally controlled to provide enough gain range and resolution. To properly set the VGA gain, the digital gain calibration loop is enabled before the VGA operates. The DC offset cancellation loop is always active to prevent the VGA output from DC saturation. With the aid of both loops, the proposed VGA is robust against process variations. An experimental chip is fabricated in TSMC 0.18-μm 1P6M CMOS process. The core area occupies 292 μm × 592 μm. The available gain range of the VGA is -3.9 ~ 48.3 dB. For a 6-dB gain step requirement, the gain error is less than 0.5 dB. The bandwidth at the maximum gain setting is 10.85 MHz. With 10-MHz 400-mVppd sinusoidal output waveform, the total harmonic distortion (THD) at maximum and minimum gain setting are -33.82 dB and -48.08 dB respectively. The output DC offset voltage is less than 20 mV when the input DC offset voltage is within -70 ~ +50 mV. The current consumption from a single 1.8-V power supply is 12.1 mA.
Krstic, Marko. "An Optimized, Variable-Gain Switched-Capacitor DC-DC Converter". Thesis, 2013. http://hdl.handle.net/1974/7868.
Texto completoThesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-04-03 23:27:24.183
Chen, Chia-Jung y 陳佳蓉. "Investigation of a variable-gain circuit for hydrogen detector". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/92400931422928360611.
Texto completo朝陽科技大學
資訊工程系碩士班
97
In this thesis, a 3×3 gas sensors array with on chip multiple input integrated circuitry by using microelectromechanical system (MEMS) was fabricated. Hydrogen sensors fabricated with different structures can be measured simultaneously. The hydrogen sensing chip has two advantages. First, the structure of the array has a cantilever beam, it can prevent the hot effect. Second the fabrication can consistent with CMOS technology. It’s easy to measure and analysis by using the chip with variable-gain.Traditionally, the hydrogen sensing device and the sensing chip were divided. It will restrict the application due to the noise at the interface between the device and chip. Our device integrate the hydrogen sensing device and sensing circuit on the same chip. Palladium (Pd) is selected as the catalytic metal. Further more in contrast to the conventional amplifier, using resistance-ratio, our design amplifier base on capacitance-ratio can prevent the influence of fabrication parameters. The DC offset also can be improved. Finally, the designed circuit has the advantages of low cost and low power consumption.
Lin, Yi-Chen y 林宜蓁. "CMOS Dual-Band Constant-IF-Bandwidth Variable Gain Up-Converter". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/97256719958668456921.
Texto completo國立交通大學
電信工程系所
96
In this thesis, we focus on Radio Frequency Integrated Circuits. We combine IF variable gain amplifier with up-converter by using a new modified V-to-I transconductor stage, therefore, both frequency up-conversion and variable-gain amplification are achieved by using current-mode operation in a single chip. We implement several variable gain up-converter with constant IF bandwidth for WLAN and UWB communication systems by using TSMC 0.18μm CMOS technology and TSMC 0.35μm SiGe BiCMOS technology. Moreover, in order to do multi-band multi-mode signal processing by a single chip, we also implement a CMOS dual-band (2.4/5.7GHz) variable gain up-converter with constant IF bandwidth for IEEE 802.11a/b/g applications.
Hung, Chia-Cheng y 洪家正. "A Low Voltage, Variable Gain Design for Low Noise Amplifier". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/15654715837525270170.
Texto completo長庚大學
電子工程研究所
92
In the thesis, an integrated RF circuit topology that can be used to realize low voltage ( i.e. 1V ) low noise amplifier is presented. The design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated circuits. Based on a LC-folded cascode LNA topology, it is implemented with a modified LC-folded cascode LNA configuration using two common source transistors to improve linearity. The linearity is improved about 2 to 3 dB. On LC-folded cascode topology, another merit that only increases in the LNA circuit complexity is an extra gain control signal, Vtune. Gain variation is achieved by controlling the Vtune, hence adjusting the overall gain of the LNA without affecting the input noise and impedance matching. The technique is applied to the design of a proposed LNA operating at 2.4 GHz using a TSMC 0.18 μm mixed signal ( 1P6M ) CMOS technology. A low voltage, variable gain design for low noise amplifier is fully on chip between input and output. The proposed LNA chip achieves measured results of 11.14 dB for power gain, 3.981 dB for noise figure, the input and output return loss of -26.06 dB and -6.827 dB, the 1-dB compression point and IIP3 of -14 dBm and -5 dBm, respectively. The circuit has 10 dB of gain tuning, and can operate at a low supply voltage of 1 V.
Wang, Po-Sheng y 王柏勝. "Design of Variable-Gain Low-Noise Amplifiers in CMOS Technology". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/46392548950397376660.
Texto completo國立中正大學
電機工程所
98
This thesis presents three enhanced CMOS low-noise amplifiers (LNA). First, a differential wideband low-noise amplifier was designed by using a shunt-shunt feedback in 0.18-μm CMOS technology. The measured power gain is 8.1?0.6 dB and noise figure is 3.5?0.3 dB in 2.3–4 GHz. The 3-dB gain bandwidth is 1–4.2 GHz. The input return losses is greater than 10.4 dB. The measured input 1-dB-compressed power is -8.8 dBm and input-referred third-order intercept (IIP3) is 0 dBm at 3 GHz. The power consumption is 19.8 mW from a 1.8 V supply. The second design is a wideband inductor-less low-noise amplifier with tunable power gain in 0.18-μm CMOS technology. The 3-dB gain bandwidth is 0.7–3.58 GHz. The power consumption is 25.2 mW from a 1.8 V supply. The measured power gain is 14.7?2.3 dB and noise figure is 3.3?0.6 dB. The input return losses is larger than 10.1. The input 1-dB-compressed power is -13.8 dBm and input-referred third-order intercept (IIP3) is -6 dBm at 3 GHz. The gain tuning range is from -2.5 to 16 dB at 3 GHz. The last design is a gm-boosted variable-gain low-noise amplifier in 0.18-μm CMOS technology. The simulation power gain is 10.13–12.91 dB and a noise figure of 3.16–3.45 dB at 3.5 GHz. The input return is greater than 14.0 dB. The simulation input 1-dB-compressed power is -20.3 dBm and input-referred third-order intercept (IIP3) is -12.2 dBm. The gain tuning range is from -1.27 dB to 12.79 dB. The power consumption is 3.4 mW from 1.2 V.
洪德儒. "A Variable-Gain 0.35um SiGe 5.25GHz RF Front-End Integrated Circuit". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/66180291387058812835.
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