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Artículos de revistas sobre el tema "Adaptive Phase Lock Loop"

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Publicado: 14 de marzo de 2023

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1

Taheri, H. E. "A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop". Engineering, Technology & Applied Science Research 7, n.º 2 (24 de abril de 2017): 1473–77. http://dx.doi.org/10.48084/etasr.1099.

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A low power, low phase noise adaptive bandwidth phase locked loop is presented in this paper. The proposed structure benefits from a novel lock status monitor unit (LSMU) that determines loop operation and loop bandwidth. The loop filter resistance and charge pump current are inversely proportional and bandwidth to reference frequency is maintained fixed. This structure is simulated in 0.18 μm CMOS technology and simulation results are presented.

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2

Cortés, Iñigo, Johannes Rossouw van der Merwe, Jari Nurmi, Alexander Rügamer y Wolfgang Felber. "Evaluation of Adaptive Loop-Bandwidth Tracking Techniques in GNSS Receivers". Sensors 21, n.º 2 (12 de enero de 2021): 502. http://dx.doi.org/10.3390/s21020502.

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Global navigation satellite system (GNSS) receivers use tracking loops to lock onto GNSS signals. Fixed loop settings limit the tracking performance against noise, receiver dynamics, and the current scenario. Adaptive tracking loops adjust these settings to achieve optimal performance for a given scenario. This paper evaluates the performance and complexity of state-of-the-art adaptive scalar tracking techniques used in modern digital GNSS receivers. Ideally, a tracking channel should be adjusted to both noisy and dynamic environments for optimal performance, defined by tracking precision and loop robustness. The difference between the average tracking jitter of the discriminator’s output and the square-root Cramér-Rao bound (CRB) indicates the loops’ tracking capability. The ability to maintain lock characterizes the robustness in highly dynamic scenarios. From a system perspective, the average lock indicator is chosen as a metric to measure the performance in terms of precision, whereas the average number of visible satellites being tracked indicates the system’s robustness against dynamics. The average of these metrics’ product at different noise levels leads to a reliable system performance metric. Adaptive tracking techniques, such as the fast adaptive bandwidth (FAB), the fuzzy logic (FL), and the loop-bandwidth control algorithm (LBCA), facilitate a trade-off for optimal performance. These adaptive tracking techniques are implemented in an open software interface GNSS hardware receiver. All three methods steer a third-order adaptive phase locked loop (PLL) and are tested in simulated scenarios emulating static and high-dynamic vehicular conditions. The measured tracking performance, system performance, and time complexity of each algorithm present a detailed analysis of the adaptive techniques. The results show that the LBCA with a piece-wise linear approximation is above the other adaptive loop-bandwidth tracking techniques while preserving the best performance and lowest time complexity. This technique achieves superior static and dynamic system performance being 1.5 times more complex than the traditional tracking loop.

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3

Won, Jong-Hoon. "A Novel Adaptive Digital Phase-Lock-Loop for Modern Digital GNSS Receivers". IEEE Communications Letters 18, n.º 1 (enero de 2014): 46–49. http://dx.doi.org/10.1109/lcomm.2013.111113.131849.

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4

Joonsuk Lee y Beomsup Kim. "A low-noise fast-lock phase-locked loop with adaptive bandwidth control". IEEE Journal of Solid-State Circuits 35, n.º 8 (agosto de 2000): 1137–45. http://dx.doi.org/10.1109/4.859502.

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5

CHAU, YAWGENG A. y CHEN-FENG CHEN. "ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS". Journal of Circuits, Systems and Computers 20, n.º 06 (octubre de 2011): 1037–49. http://dx.doi.org/10.1142/s0218126611007748.

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The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.

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6

Hu, Yu Feng, Bin Liu y Jun Liu. "PFC Controller Based on Self-Adaptive Proportional-Resonant Control". Advanced Materials Research 588-589 (noviembre de 2012): 1533–38. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.1533.

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Proportional-resonant is introduced in PFC controller design and the coefficients are easy to tune. Zero-tracking-error can be achieved for the fundamental frequency and selective harmonic compensation can be achieved as well. Also a novel Phase-Loop-Lock controller is given based on which a self-adaptive proportional resonant PFC controller is induced at last.

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7

Zhang, Youming, Xusheng Tang, Zhennan Wei, Kaiye Bao y Nan Jiang. "A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control". Electronics 10, n.º 2 (7 de enero de 2021): 109. http://dx.doi.org/10.3390/electronics10020109.

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This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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8

Zhang, Youming, Xusheng Tang, Zhennan Wei, Kaiye Bao y Nan Jiang. "A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control". Electronics 10, n.º 2 (7 de enero de 2021): 109. http://dx.doi.org/10.3390/electronics10020109.

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This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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9

Liu, G. y L. Wang. "JOINT TRACKING GPS AND LEO SIGNALS WITH ADAPTIVE VECTOR TRACKING LOOP IN CHALLENGING ENVIRONMENTS". International Archives of the Photogrammetry, Remote Sensing and Spatial Information Sciences XLVI-3/W1-2022 (22 de abril de 2022): 119–24. http://dx.doi.org/10.5194/isprs-archives-xlvi-3-w1-2022-119-2022.

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Abstract. Navigation from LEO satellites own many merits and attracts increasing popularity recently. In addition to increasing the signal availability, the low signal strength loss and fast satellite geometry change from LEO satellite are particularly appealing in challenging environments. Recently, a few researchers attempt to navigate with non-cooperative signals from LEO satellites with pure phase lock loop (PLL) or frequency lock loop (FLL), while a more practical solution to utilizing LEO navigation is joint positioning with the existing GNSS signals which has not been seriously studied. In this study, we proposed a joint GPS and LEO navigation signal tracking strategy that employs a vector tracking loop (VTL) with fully considering the high dynamic characteristics of the LEO signals. In order to solve the high dynamics problem, the second-order deviation parameters were considered in the extended Kalman filter, which is more adaptive to the non-linear variation of the signal acceleration. In addition, a carrier-to-noise ratio (C/N0) based observation noise determination strategy is employed to adapt different observation conditions. The proposed method was verified with different simulation data and the results indicate the adaptive vector tracking loop is capable of tracking GPS and LEO signals simultaneously and robustly. The benefit is particularly in the weak signal scenarios. The experiment results also reveal that the joint vector tracking loop improves positioning accuracy in GNSS challenging environments.

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10

Wang, Binghui, Haigang Yang y Yiping Jia. "A 1-to-3 GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28 nm CMOS". Electronics 11, n.º 13 (22 de junio de 2022): 1954. http://dx.doi.org/10.3390/electronics11131954.

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Based on a self-biased architecture, this paper presents a novel adaptive fast-locking, wide operating range and low-jitter phase-locked loop (PLL). A current injection and adaptive bandwidth technology with minimum area overhead is employed to speed up the loop equilibrium acquisition process, without any adverse impact on the steady-state loop dynamics and the jitter performance. The proposed start-up circuit resets the loop to an appropriate initial state in order to shorten the initial ramp-up interval of the voltage-controlled oscillator (VCO), also resulting in cutting down the pull-in time. In addition, a proportional factor is introduced to give some kind of flexibility in the circuit design optimization. The proposed adaptive fast-locking self-biased PLL (AFL-SPLL) is designed and realized in a prototype based on TSMC 28 nm CMOS process, having a supply voltage of 0.9 V and an area of 0.0281 mm2. This PLL demonstrates a tuning range of 1 to 3 GHz and power consumptions from 0.91 mW at 1 GHz to 4.6 mW at 3 GHz operating frequency. The experimental results show that the capture process has been accelerated by up to 84.7% over large division ratios, yet the capture performance did not deteriorate at all for small division ratios. Meanwhile, the circuit implementation gave almost no area increase and yet achieved a reduction in the lock-in time of about 6.5 times, namely from 23.5 μs (without the adaptive locking) to only 3.6 μs (with the adaptive locking) on the maximum operation frequency condition of 3 GHz.

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11

Le, Phuong Minh, Duy Vo Duc Hoang, Hoa Thi Xuan Pham y Huy Minh Nguyen. "New adaptive droop control with combined line impedance estimation method for parallel inverters". Science and Technology Development Journal 19, n.º 4 (31 de diciembre de 2016): 45–64. http://dx.doi.org/10.32508/stdj.v19i4.781.

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This paper presents a new load sharing control between paralleled three-phase inverters in an islanded-microgrid based on the line impedance estimation online by the use of the Kalman filter. We can solve the mismatch of power sharing when the line impedance changes due to the temperature and frequency, significant differences of line parameters and requirements of Plug-and-Play mode of inverters connected to the microgrid. Moreover, the paper also presents a new Droop control method working with the line impedance which is different from the Droop traditional algorithm when the line impedance is assumed pure resistance R or pure inductance X. In the paper, the line impedance estimation for parallel inverters uses the least squares method combined with Kalman filter. In addition, secondary control loops are designed to restore the voltage amplitude and frequency of the microgrid by using a combined nominal value SOGI-PLL with generalized integral block and phase lock loop to exactly monitor the voltage magnitude and frequency phase at common PCC. Control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of the power sharing. The simulation results have shown the accuracy of the proposed control method. Therefore, the proposed adaptive droop control method based on line impedance estimation can be an alternative one for load sharing control in islanded microgrids.

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12

Guo, You Gui, Ping Zeng, Li Juan Li, Jie Qiong Zhu, Wen Lang Deng y Frede Blaabjerg. "Adaptive Hysteresis Band Current Control (AHB) with PLL of Grid Side Converter-Based Wind Power Generation System". Applied Mechanics and Materials 52-54 (marzo de 2011): 1911–16. http://dx.doi.org/10.4028/www.scientific.net/amm.52-54.1911.

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Adaptive hysteresis band current control(AHB CC) is used to control the three-phase grid currents by means of grid side converter in wind power generation system in this paper. AHB has reached the good purpose with PLL (Lock phase loop). First the mathematical models of each part are given. Then the control strategy of grid side converter-based wind power generation system is given in detail mainly including ABH CC and PI controllers of DC-link voltage, active power, reactive power. Finally the simulation model is set up which consists of power circuits, such as the grid side converter, LCL filter, transformer and grid, and control parts, etc. The simulation results have verified that the control strategy is feasible to fit for control of gird currents, active power, reactive power and DC-link voltage in wind power generation system.

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13

Chou, Hsiao-Hsing y Hsin-Liang Chen. "A Novel Buck Converter with Constant Frequency Controlled Technique". Energies 14, n.º 18 (17 de septiembre de 2021): 5911. http://dx.doi.org/10.3390/en14185911.

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This paper presents a buck converter with a novel constant frequency controlled technique, which employs the proposed frequency detector and adaptive on-time control (AOT) logic to lock the switching frequency. The control scheme, design concept, and circuit realization are presented. In contrast to a complex phase lock loop (PLL), the proposed scheme is easy to implement. With this novel technique, a buck converter is designed to produce an output voltage of 1.0–2.5 V at the input voltage of 3.0–3.6 V and the maximum load current of 500 mA. The proposed scheme was verified using SIMPLIS and MathCAD. The simulation results show that the switching frequency variation is less than 1% at an output voltage of 1.0–2.5 V. Furthermore, the recovery time is less than 2 μs for a step-up and step-down load transient. The circuit will be fabricated using UMC 0.18 μm 1P6M CMOS processes. The control scheme, design concept and circuit realization are presented in this paper.

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14

Yang, Haotian, Bin Zhou, Lixin Wang, Qi Wei, Feng Ji y Rong Zhang. "Performance and Evaluation of GNSS Receiver Vector Tracking Loop Based on Adaptive Cascade Filter". Remote Sensing 13, n.º 8 (12 de abril de 2021): 1477. http://dx.doi.org/10.3390/rs13081477.

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In the scenario of high dynamics and low C/N0, the discriminator output of a GNSS tracking loop is noisy and nonlinear. The traditional method uses a fixed-gain loop filter for error estimation, which is prone to lose lock and causes inaccurate navigation and positioning. This paper proposes a cascaded adaptive vector tracking method based on the KF+EKF architecture through the GNSS Software defined receiver in the signal tracking module and the navigation solution module. The linear relationships between the pseudo-range error and the code phase error, the pseudo-range rate error and the carrier frequency error are obtained as the measurement, and the navigation filter estimation is performed. The signal C/N0 ratio and innovation sequence are used to adjust the measurement noise covariance matrix and the process noise covariance matrix, respectively. Then, the estimated error value is used to correct the navigation parameters and fed back to the local code/carrier NCO. The field vehicle test results show that, in the case of sufficient satellite signals, the positioning error of the proposed method has a slight advantage compared with the traditional method. When there is signal occlusion or interference, the traditional method cannot achieve accurate positioning. However, the proposed method can maintain the same accuracy for the positioning results.

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15

MIAO, Jian-Feng, Wu CHEN, Yong-Rong SUN y Jian-Ye LIU. "Adaptively Robust Phase Lock Loop for Low C/N Carrier Tracking in a GPS Software Receiver". Acta Automatica Sinica 37, n.º 1 (25 de mayo de 2011): 52–60. http://dx.doi.org/10.3724/sp.j.1004.2011.00052.

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16

MIAO, Jian-Feng, Wu CHEN, Yong-Rong SUN y Jian-Ye LIU. "Adaptively Robust Phase Lock Loop for Low C/N Carrier Tracking in a GPS Software Receiver". Acta Automatica Sinica 37, n.º 1 (enero de 2011): 52–60. http://dx.doi.org/10.1016/s1874-1029(11)60198-5.

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17

Luo, Y., C. Yu, J. Li y N. El-Sheimy. "PERFORMANCE OF GNSS CARRIER-TRACKING LOOP BASED ON KALMAN FILTER IN A CHALLENGING ENVIRONMENT". ISPRS - International Archives of the Photogrammetry, Remote Sensing and Spatial Information Sciences XLII-2/W13 (5 de junio de 2019): 1687–93. http://dx.doi.org/10.5194/isprs-archives-xlii-2-w13-1687-2019.

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<p><strong>Abstract.</strong> The global navigation satellite system (GNSS) recently plays an extremely important role in positioning, navigation, and timing (PNT) applications for the modernized automations and mechanizations, e.g., unmanned aerial vehicles (UAVs), unmanned ground vehicles (UGVs), military aircrafts, etc. Nevertheless, GNSS signals are very vulnerable to the influence of various interferences when they are received on Earth, and the reason why it happens is that the long line-of-sight (LOS) distance between the satellite and the receiver user dramatically reduces the power strength after the signal reaches at the ground. The weak GNSS signal is hard to be handled with traditional phase lock loop (PLL), especially in a dynamic environment. Again, the trade-off among the coherent integration time of tracking loop, received signal power strength, and signal or user receiver dynamics is still a tough and remained problem to be solved. The Kalman filter (KF) is always a promising tool to efficiently decrease the random noise for the tracking process. In our work, we evaluate the performances of the tracking loop modelled with both standard KF and extended Kalman filter (EKF). An adaptive algorithm for the covariance matrix of the process noise is contained in our system to increase the tracking ability in a weak and dynamic environment. Besides, a noise channel is also contained to automatically adjust the priori measurement covariance for the KF tracking loop model. Simulation results demonstrate the performance with the proposed technique.</p>

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18

Dash, Byomakesh, Renu Sharma y Bidyadhar Subudhi. "A multiobjective grid interactive solar photovoltaic DSTATCOM system using cascaded observer-based DFLL approach". World Journal of Engineering 17, n.º 5 (30 de junio de 2020): 641–59. http://dx.doi.org/10.1108/wje-01-2020-0009.

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Purpose A cascaded observer-based transfer delay frequency locked loop (CODFLL) algorithm is developed to control the distribution static compensator (DSTATCOM) to address various power quality (PQ) issues arise because of distorted grid and load conditions. Moreover, frequency locked loop is included along with the observer to take care of the frequency drift from nominal value and to improve its performance during steady state and transient conditions. During daylight, the proposed system works as photovoltaic (PV) DSTATCOM and performs multiple functions for improving PQ whilst transferring power to grid and load. The system under consideration acts as DSTATCOM during night and bad weather condition to nullify the PQ issues. Design/methodology/approach CODFLL control algorithm generates reference signal for hysteresis controller. This reference signal is compared with an actual grid signal and a gate pulse is produced for a voltage source converter. The system is made frequency adaptive by transfer delay adaptive frequency locked loop (FLL). Peak power is extracted from a PV source using the perturb and observe technique irrespective of disturbances encountered in the system. Findings The PV system’s performance with the proposed controller is studied and compared with conventional control algorithms such as least mean fourth (LMF), improved second-order generalized integrator frequency locked loop (ISOGI-FLL), synchronous reference frame phased lock loop (SRF-PLL) and frequency adaptive disturbance observer (DOB) for different cases, for example, steady-state condition, dynamic condition, variable insolation, voltage sag and swell and frequency wandering in the supply side. It is found that the proposed method tracks the frequency variation faster as compared to ISOGI-FLL without any oscillations. During unbalanced loading conditions, CODFLL exhibits zero oscillations. Harmonics in system parameters are reduced to the level of IEEE standard; unity power factor is maintained at the grid side; hassle-free power flow takes place from the source to the grid and load; and consistent voltage profile is maintained at the coupling point. Originality/value CODFLL control algorithm is developed for PV-DSTATCOM systems to generate a reference grid current.

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19

Jwo, Dah-Jing, Chi-Fan Yang, Chih-Hsun Chuang y Kun-Chieh Lin. "A Novel Design for the Ultra-Tightly Coupled GPS/INS Navigation System". Journal of Navigation 65, n.º 4 (30 de mayo de 2012): 717–47. http://dx.doi.org/10.1017/s0373463312000161.

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This paper presents a sensor fusion method for the Ultra-Tightly Coupled (UTC) Global Positioning System (GPS)/Inertial Navigation System (INS) integrated navigation. The UTC structure, also known as the deep integration, exhibits many advantages, e.g., disturbance and multipath rejection capability, improved tracking capability for dynamic scenarios and weak signals, and reduction of acquisition time. This architecture involves the integration of I (in-phase) and Q (quadrature) components from the correlator of a GPS receiver with the INS data. The Particle Filter (PF) exhibits superior performance as compared to an Extended Kalman Filter (EKF) and Unscented Kalman Filter (UKF) in state estimation for the nonlinear, non-Gaussian system. To handle the problem of heavy-tailed probability distribution, one of the strategies is to incorporate the UKF into the PF as the proposal distribution, leading to the Unscented Particle Filter (UPF). The combination of an adaptive UPF and Fuzzy Logic Adaptive System (FLAS) is adopted for reducing the number of particles with sufficiently good results. The GPS tracking loops may lose lock due to the signals being weak, subjected to excessive dynamics or completely blocked. One of the principal advantages of the UTC structure is that a Doppler frequency derived from the INS is integrated with the tracking loops to improve the receiver tracking capability. The Doppler frequency shift is calculated and fed to the GPS tracking loops for elimination of the effect of stochastic errors caused by the Doppler frequency. In this paper, several nonlinear filtering approaches, including EKF, UKF, UPF and ‘FLAS assisted UPF’ (FUPF), are adopted for performance comparison for ultra-tight integration of GPS and INS. It is assumed that no outage occurs such that the inertial sensor errors can be properly corrected and accordingly the aiding information is working well. Two examples are provided for performance assessment for the various data fusion methods. The FUPF algorithm with Doppler velocity aiding demonstrates remarkable improvement, especially in the high dynamic environments, in navigation estimation accuracy with reduction of number of particles.

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20

Salamah, A. M., S. J. Finney y B. W. Williams. "Three-phase phase-lock loop for distorted utilities". IET Electric Power Applications 1, n.º 6 (2007): 937. http://dx.doi.org/10.1049/iet-epa:20070036.

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21

Kaplan, B. Z., M. Rolnick y D. Wulich. "A new fast-response double-loop phase-lock loop". Proceedings of the IEEE 74, n.º 2 (1986): 368–69. http://dx.doi.org/10.1109/proc.1986.13466.

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22

Shewale, Saurabh J. "Design and Analysis of CMOS Phase Lock Loop (PLL) Using VLSI Technology". International Journal for Research in Applied Science and Engineering Technology 9, n.º 11 (30 de noviembre de 2021): 1334–37. http://dx.doi.org/10.22214/ijraset.2021.38363.

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Abstract: This paper proffers comparative research of Complementary MOSFET (CMOS) of the Phase Lock Loop (PPL) circuit. Our approach is based on hybrid design Phase Lock Loop (PLL) circuits combined in a single unit. A phase-locked loop (PLL) is used in space communication for synchronization purposes also very useful in time to digital converters and in instrumentation engineering. A phased lock loop (PLL) is a control system that makes an output signal whose frequency depends on the input phase difference. The phase detector takes the phase of an input signal and compares it with the phase procured from its output oscillator regulates the frequency of its oscillator to manage the phase matches. Different techniques like analogue and digital simulation with the help of mathematical/logical connections are found in Research to create the Phase Locked Loop (PLL). This limitation can be overcome by replicating the circuit block whose supply voltage is being reduced to manage the same throughout. This paper includes design features for low power phase-locked loop using Very-large-scale integration (VLSI) technology. The signal from the phase detector controls the oscillator in a feedback loop. As such: an operational device the PLL has a wide range of applications in computers sciences, telecommunication, and electronic system applications; we aim to design and examine the phase lock loop circuit in multiple technologies and examine their power capacity. By using the hybrid structure of NMOS and PMOS, here we have achieved the circuit of Phase Lock Loop (PLL) using VLSI technology. Keywords: Technology, CMOS, Phase lock loop, Micro wind, Voltage control oscillator, VLSI technology.

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23

Biswas, B. N., S. Sarkar y S. Chatterjee. "Interference and long-loop phase-lock receivers". Electronics Letters 24, n.º 16 (1988): 1035. http://dx.doi.org/10.1049/el:19880705.

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24

Engelberg, S. y M. Wexler. "The operation of the phase-lock loop". Computers & Mathematics with Applications 40, n.º 10-11 (noviembre de 2000): 1253–61. http://dx.doi.org/10.1016/s0898-1221(00)00236-4.

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25

Kumar, Amit, Shailendra Singh Ojha y Shyam Akashe. "Reduction of Phase Noise and Lock Time in Low Power Phase Lock Loop (PLL)". Journal of Computational and Theoretical Nanoscience 15, n.º 4 (1 de abril de 2018): 1360–67. http://dx.doi.org/10.1166/jctn.2018.7216.

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26

Fan, Guangteng, Yangbo Huang, Yingxue Su, Jingyuan Li y Guangfu Sun. "A reduced bias delay lock loop for adaptive filters". Advances in Space Research 59, n.º 1 (enero de 2017): 230–35. http://dx.doi.org/10.1016/j.asr.2016.09.007.

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27

Patil, Pallavi y Virendra K. Verma. "Integer N Frequency Synthesizer using Phase Lock Loop". International Journal of Computer Trends and Technology 32, n.º 1 (25 de enero de 2016): 8–13. http://dx.doi.org/10.14445/22312803/ijctt-v32p102.

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28

Wu, Kuen-Der y Hurng-Liahng Jou. "A new phase detection method for a phase lock loop". International Journal of Electronics 86, n.º 11 (noviembre de 1999): 1359–66. http://dx.doi.org/10.1080/002072199132644.

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29

Ding, Zhaoming, Haiqi Liu y Qiang Li. "Phase‐error cancellation technique for fast‐lock phase‐locked loop". IET Circuits, Devices & Systems 10, n.º 5 (septiembre de 2016): 417–22. http://dx.doi.org/10.1049/iet-cds.2015.0201.

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30

Winkler, Irwin C., Mary A. Norton y Charles Higgs. "Adaptive phase compensation in a Raman look-through configuration". Optics Letters 14, n.º 1 (1 de enero de 1989): 69. http://dx.doi.org/10.1364/ol.14.000069.

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31

Ramos, Rogerio T., Alwyn J. Seeds, Aldario Bordonalli, Philippe Gallion y Didier Erasme. "Optical injection locking and phase-lock loop combined systems". Optics Letters 19, n.º 1 (1 de enero de 1994): 4. http://dx.doi.org/10.1364/ol.19.000004.

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32

Balakier, Katarzyna, Martyn J. Fice, Lalitha Ponnampalam, Alwyn J. Seeds y Cyril C. Renaud. "Monolithically Integrated Optical Phase Lock Loop for Microwave Photonics". Journal of Lightwave Technology 32, n.º 20 (15 de octubre de 2014): 3893–900. http://dx.doi.org/10.1109/jlt.2014.2317941.

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33

Stensby, John. "False Lock and Bifurcation in the Phase Locked Loop". SIAM Journal on Applied Mathematics 47, n.º 6 (diciembre de 1987): 1177–84. http://dx.doi.org/10.1137/0147079.

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34

Chunhua Wei, Chunhua Wei, Shuhua Yan Shuhua Yan, Aiai Jia Aiai Jia, Yukun Luo Yukun Luo, Qingqing Hu Qingqing Hu y and Zehuan Li and Zehuan Li. "Compact phase-lock loop for external cavity diode lasers". Chinese Optics Letters 14, n.º 5 (2016): 051403–51406. http://dx.doi.org/10.3788/col201614.051403.

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35

Hasan, P. y M. Brunk. "Exact calculation of phase-locked loop lock-in frequency". Electronics Letters 22, n.º 25 (1986): 1340. http://dx.doi.org/10.1049/el:19860921.

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36

Bałakier, Katarzyna, Martyn J. Fice, Lalitha Ponnampalam, Chris S. Graham, Adrian Wonfor, Alwyn J. Seeds y Cyril C. Renaud. "Foundry fabricated photonic integrated circuit optical phase lock loop". Optics Express 25, n.º 15 (10 de julio de 2017): 16888. http://dx.doi.org/10.1364/oe.25.016888.

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37

Gupta, A. Sen, A. K. Hanjura y B. S. Mathur. "Digital Phase Lock Loop for Tracking Very Low Frequencies". IETE Technical Review 3, n.º 3 (marzo de 1986): 85–88. http://dx.doi.org/10.1080/02564602.1986.11437906.

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38

Shi Hao y Yan Puqiang. "A high lock-in speed digital phase-locked loop". IEEE Transactions on Communications 39, n.º 3 (marzo de 1991): 365–68. http://dx.doi.org/10.1109/26.79274.

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39

Engelberg, S. "Errata to “The operation of the phase-lock loop”". Computers & Mathematics with Applications 47, n.º 6-7 (marzo de 2004): 1141–42. http://dx.doi.org/10.1016/s0898-1221(04)90094-6.

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40

Stensby, John. "VCO sweep-rate limit for a phase-lock loop". Journal of the Franklin Institute 346, n.º 3 (abril de 2009): 223–36. http://dx.doi.org/10.1016/j.jfranklin.2008.09.002.

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41

Banerjee, Abhijit y Baidyanath Biswas. "Pull-in analysis of dither optical phase-lock loop". Optics Communications 426 (noviembre de 2018): 278–86. http://dx.doi.org/10.1016/j.optcom.2018.05.018.

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42

Xu, Chao, Yumeng Xie y Yuan Zhou. "Design of double ring lock ring in extensible frequency clock generator chip". Journal of Physics: Conference Series 2137, n.º 1 (1 de diciembre de 2021): 012041. http://dx.doi.org/10.1088/1742-6596/2137/1/012041.

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Abstract With the continuous development of computer technology and the continuous improvement of interface data rate, the clock frequency has reached the demand of several gigahertz, which makes the electromagnetic interference problem very serious. Spread spectrum clock is an effective method to reduce electromagnetic interference of digital chips. Therefore, this paper designs a double-loop phase-locked loop that can spread spectrum and has strong anti-electromagnetic noise interference ability. The designed dual-loop phase-locked loop can be used in the clock generator chip. The overall structure of the circuit consists of a main loop and a secondary loop. The main loop is an adjustable phase-locked loop circuit that can provide an output with a center frequency of 500MHz. The secondary loop can realize the spread spectrum function by charging and discharging the filter capacitor of the main loop loop, and at the same time, the spreading depth can be set by the feedback based on the frequency division. The dual-loop phase-locked loop designed in this paper has a good effect in spread spectrum and anti-electromagnetic interference noise.

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43

Zhou, Duo, Jin Yi Zhang y Bo Ye. "An Implementation of Wide-Range Digital Delay Locked Loop". Advanced Materials Research 945-949 (junio de 2014): 2226–29. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.2226.

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This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. The experimental result shows that the chip could work in a wide frequency range from 10 MHz to 1 GHz, with less than 20 cycles lock-in time, 10-ps delay resolution, and 6.4 mW at 1 GHz power dissipation.

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44

Steed, Robert J., Francesca Pozzi, Martyn J. Fice, Cyril C. Renaud, David C. Rogers, Ian F. Lealman, David G. Moodie et al. "Monolithically integrated heterodyne optical phase-lock loop with RF XOR phase detector". Optics Express 19, n.º 21 (29 de septiembre de 2011): 20048. http://dx.doi.org/10.1364/oe.19.020048.

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45

Khudchenko, A. V., V. P. Koshelets, A. B. Ermakov y P. N. Dmitriev. "A cryogenic phase detector for a cooled wideband phase-lock loop system". Journal of Communications Technology and Electronics 53, n.º 5 (mayo de 2008): 594–99. http://dx.doi.org/10.1134/s1064226908050197.

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46

Hu, Shi Chang, Hui Jie Zhu, Ming Jun Ma, Yi Dong Liu y Zhong He Jin. "An Improved Phase Lock Loop for Micromechanical Gyroscope with a Carrier Modulation". Key Engineering Materials 562-565 (julio de 2013): 398–402. http://dx.doi.org/10.4028/www.scientific.net/kem.562-565.398.

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This paper presents an improved phase lock loop for a micromechanical vibrating gyroscope with a carrier modulation. The loop keeps the gyroscope working at the resonant frequency of its drive mode. Digital signal processing is adopted in design of the loop and Xilinx virtex4 series FPGA is used. Compare with the conventional way, it decreases the resources in FPGA including registers, LUTs, and DSP48s. The realization shows a reduction of 51.06% for registers, 52.68% for LUTs and 18.18% for DSP48s. Besides, the loop has good portability for different devices which have different resonant frequencies due to the fabrication error. No adjustment is needed unlike the conventional loop whose reference phase has to be adjusted manually.

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47

Nam, Hyungseok, Ngoc Duc Au, Duy Ninh Dang, Moongyu Lee, Seunghun Lee, Minho Go y Chulhun Seo. "Phase Locked Loop with Fast Lock Time using Active Filter". Journal of the Institute of Electronics and Information Engineers 55, n.º 10 (31 de octubre de 2018): 20–25. http://dx.doi.org/10.5573/ieie.2018.55.10.20.

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48

Hisata, Yudai, Akira Mizutori y Masafumi Koga. "Automatic optical heterodyne phase lock by microcomputer-assisted loop filter". IEICE Communications Express 5, n.º 12 (2016): 448–53. http://dx.doi.org/10.1587/comex.2016xbl0152.

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49

Davidson, F. y C. T. Field. "Optical phase lock loop with a photorefractive optical beam combiner". IEEE Photonics Technology Letters 5, n.º 10 (octubre de 1993): 1238–40. http://dx.doi.org/10.1109/68.248440.

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50

Glance, B. S. "New Phase-Lock Loop Circuit Providing Very Fast Acquisition Time". IEEE Transactions on Microwave Theory and Techniques 33, n.º 9 (septiembre de 1985): 747. http://dx.doi.org/10.1109/tmtt.1985.1133122.

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