Artículos de revistas sobre el tema "32 NM TECHNOLOGY NODE"
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Allgair, John, Benjamin Bunday, Aaron Cordes, Pete Lipscomb, Milt Godwin, Victor Vartanian, Michael Bishop, Doron Arazi y Kye-Weon Kim. "Metrology Requirements for the 32 nm Technology Node and Beyond". ECS Transactions 18, n.º 1 (18 de diciembre de 2019): 151–60. http://dx.doi.org/10.1149/1.3096443.
Texto completoHuang, Zhengfeng, Di Cao, Jianguo Cui, Yingchun Lu, Yiming Ouyang, Haochen Qi, Qi Xu, Huaguo Liang y Tianming Ni. "Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology". Journal of Computer-Aided Design & Computer Graphics 33, n.º 3 (1 de marzo de 2021): 346–55. http://dx.doi.org/10.3724/sp.j.1089.2021.18385.
Texto completoHuang, Zhengfeng, Yang Guo, Shangjie Pan, Yingchun Lu, Huaguo Liang, Haochen Qi, Yiming Ouyang, Tianming Ni y Qi Xu. "Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology". Journal of Computer-Aided Design & Computer Graphics 32, n.º 12 (1 de diciembre de 2020): 2013–20. http://dx.doi.org/10.3724/sp.j.1089.2020.18160.
Texto completoOno, Kazuo, Kenzo Kurotsuchi, Yoshihisa Fujisaki, Riichiro Takemura, Motoyasu Terao y Norikatsu Takaura. "Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond". Japanese Journal of Applied Physics 48, n.º 4 (20 de abril de 2009): 04C160. http://dx.doi.org/10.1143/jjap.48.04c160.
Texto completoOrlowski, Marius y Andreas Wild. "Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?" ECS Transactions 3, n.º 6 (21 de diciembre de 2019): 3–17. http://dx.doi.org/10.1149/1.2357050.
Texto completoPark, Dae-Gyu, Mike Chudzik y Haizhou Yin. "Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond". ECS Transactions 11, n.º 6 (19 de diciembre de 2019): 371–77. http://dx.doi.org/10.1149/1.2778394.
Texto completoHussain, Inamul y Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications". Nanoscience & Nanotechnology-Asia 10, n.º 3 (17 de junio de 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.
Texto completoKumar, Amresh y Aminul Islam. "Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node". Microsystem Technologies 23, n.º 9 (6 de julio de 2016): 4099–109. http://dx.doi.org/10.1007/s00542-016-3055-4.
Texto completoAndrieu, F., O. Weber, T. Ernst, O. Faynot y S. Deleonibus. "Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node". Microelectronic Engineering 84, n.º 9-10 (septiembre de 2007): 2047–53. http://dx.doi.org/10.1016/j.mee.2007.04.132.
Texto completoCollaert, N., R. Rooyackers, A. Hikavyy, A. Dixit, F. Leys, P. Verheyen, R. Loo, M. Jurczak y S. Biesemans. "Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth". Thin Solid Films 517, n.º 1 (noviembre de 2008): 101–4. http://dx.doi.org/10.1016/j.tsf.2008.08.031.
Texto completoSankar, P. A. Gowri y K. Udhayakumar. "Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes". Journal of Low Power Electronics 10, n.º 4 (1 de diciembre de 2014): 602–16. http://dx.doi.org/10.1166/jolpe.2014.1355.
Texto completoMorgenfeld, Bradley. "Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes". Journal of Micro/Nanolithography, MEMS, and MOEMS 11, n.º 1 (19 de marzo de 2012): 013010. http://dx.doi.org/10.1117/1.jmm.11.1.013010.
Texto completoHeyns, M. y W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials". MRS Bulletin 34, n.º 7 (julio de 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.
Texto completoSharma, Vijay Kumar y Manisha Pattanaik. "Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library". Journal of Circuits, Systems and Computers 25, n.º 11 (14 de agosto de 2016): 1650134. http://dx.doi.org/10.1142/s0218126616501346.
Texto completoTrojman, Lionel, Eduardo Holguin, Marco Villegas, Luis-Miguel Procel y Ramiro Taco. "From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits". Electronics 11, n.º 4 (10 de febrero de 2022): 525. http://dx.doi.org/10.3390/electronics11040525.
Texto completoBourgeat, Johan y Philippe Galy. "Single and compact ESD device Beta-Matrix solution based on bidirectional SCR Network in advanced 28/32 nm technology node". Solid-State Electronics 87 (septiembre de 2013): 34–42. http://dx.doi.org/10.1016/j.sse.2013.04.033.
Texto completoMannaert, G., L. Witters, Denis Shamiryan, Werner Boullart, K. Han, S. Luo, A. Falepin, R. Sonnemans, Ivan L. Berry y Carlo Waldfried. "Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond". Solid State Phenomena 145-146 (enero de 2009): 253–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.253.
Texto completoHussin, H., N. Soin, M. F. Bukhori, S. Wan Muhamad Hatta y Y. Abdul Wahab. "Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs". Scientific World Journal 2014 (2014): 1–13. http://dx.doi.org/10.1155/2014/490829.
Texto completoWada, Masayuki, H. Takahashi, J. Snow, Rita Vos, P. W. Mertens y H. Shirakawa. "Applicable Solvent Photoresist Strip Process for High-K/Metal Gate". Solid State Phenomena 187 (abril de 2012): 105–8. http://dx.doi.org/10.4028/www.scientific.net/ssp.187.105.
Texto completoPham, Huyen Thi, Hung Tuan Dao y Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder". Journal of Science and Technology on Information security 9, n.º 01 (9 de abril de 2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.
Texto completoFeruglio, S., F. Andrieu, O. Faynot y G. Ghibaudo. "Low-temperature electrical characterization of fully depleted eXtra-strained SOI n-MOSFETs with TiN/HfO2 gate stack for the 32-nm technology node". Cryogenics 49, n.º 11 (noviembre de 2009): 605–10. http://dx.doi.org/10.1016/j.cryogenics.2008.12.004.
Texto completoJin, Yurin, Yeonho Seo, Sungmi Kim y Seongik Cho. "Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero". Electronics 12, n.º 11 (23 de mayo de 2023): 2361. http://dx.doi.org/10.3390/electronics12112361.
Texto completoSharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit". Journal of Circuits, Systems and Computers 26, n.º 09 (24 de abril de 2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.
Texto completoDinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan y Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE". Journal of Computer Science and Cybernetics 37, n.º 2 (31 de mayo de 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.
Texto completoCho, Sangki, Sueyeon Kim, Insoo Choi, Myounggon Kang, Seungjae Baik y Jongwook Jeon. "Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor". AIP Advances 13, n.º 4 (1 de abril de 2023): 045211. http://dx.doi.org/10.1063/5.0141131.
Texto completoSharma, Himanshu y Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects". Journal of Circuits, Systems and Computers 29, n.º 12 (5 de febrero de 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
Texto completoAhmed Khan, Imran. "Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications". Journal of Physics: Conference Series 2161, n.º 1 (1 de enero de 2022): 012050. http://dx.doi.org/10.1088/1742-6596/2161/1/012050.
Texto completoSharma, Neha y Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS". International Journal of Modeling, Simulation, and Scientific Computing 12, n.º 04 (9 de marzo de 2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.
Texto completoAmin, Abu Bony, Syed Muhammad Shakil y Muhammad Sana Ullah. "A Theoretical Modeling of Adaptive Mixed CNT Bundles for High-Speed VLSI Interconnect Design". Crystals 12, n.º 2 (27 de enero de 2022): 186. http://dx.doi.org/10.3390/cryst12020186.
Texto completoGarg, Sandeep y Tarun K. Gupta. "A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology". Journal of Circuits, Systems and Computers 28, n.º 10 (septiembre de 2019): 1950165. http://dx.doi.org/10.1142/s0218126619501652.
Texto completoZhu, Yihan y Takashi Ohsawa. "A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters". Japanese Journal of Applied Physics 61, SC (21 de febrero de 2022): SC1053. http://dx.doi.org/10.35848/1347-4065/ac44ce.
Texto completoGhasemian, Arsalan, Ebrahim Abiri, Kourosh Hassanli y Abdolreza Darabi. "HF-QSRAM: Half-Select Free Quaternary SRAM Design with Required Peripheral Circuits for IoT/IoVT Applications". ECS Journal of Solid State Science and Technology 11, n.º 1 (1 de enero de 2022): 011002. http://dx.doi.org/10.1149/2162-8777/ac4798.
Texto completoBendre, Varsha S., A. K. Kureshi y Saurabh Waykole. "Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier". Journal of Nanotechnology 2018 (4 de diciembre de 2018): 1–15. http://dx.doi.org/10.1155/2018/2301421.
Texto completoLai, Fu-Der y Jian Long Huang. "Proposed single layer composite film used as high transmission phase shifting masks for the 32, 45, and 65 nm technology nodes". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, n.º 6 (2007): 1799. http://dx.doi.org/10.1116/1.2790920.
Texto completoBhuvana, B. P. y V. S. Kanchana Bhaaskaran. "Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures". Journal of Circuits, Systems and Computers 29, n.º 01 (23 de abril de 2019): 2050016. http://dx.doi.org/10.1142/s0218126620500164.
Texto completoDadoria, Ajay Kumar, Kavita Khare, Tarun Kumar Gupta y R. P. Singh. "New Leakage Reduction Techniques for FinFET Technology with Its Application". Journal of Circuits, Systems and Computers 27, n.º 07 (26 de marzo de 2018): 1850112. http://dx.doi.org/10.1142/s0218126618501128.
Texto completoBhattacharya, Sandip, Debaprasad Das y Hafizur Rahaman. "Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network". Journal of Circuits, Systems and Computers 27, n.º 01 (23 de agosto de 2017): 1850001. http://dx.doi.org/10.1142/s0218126618500019.
Texto completoPark, Jun-Young, Minhyun Jin, Soo-Youn Kim y Minkyu Song. "Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips". Electronics 11, n.º 6 (10 de marzo de 2022): 877. http://dx.doi.org/10.3390/electronics11060877.
Texto completoDecoster, Stefan, Elisabeth Camerotto, Gayle Murdoch, Souvik Kundu, Quoc Toan Le, Zsolt Tőkei, Gosia Jurczak y Frédéric Lazzarino. "Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below". Journal of Vacuum Science & Technology B 40, n.º 3 (mayo de 2022): 032802. http://dx.doi.org/10.1116/6.0001791.
Texto completoDecoster, Stefan, Elisabeth Camerotto, Gayle Murdoch, Souvik Kundu, Quoc Toan Le, Zsolt Tőkei, Gosia Jurczak y Frédéric Lazzarino. "Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below". Journal of Vacuum Science & Technology B 40, n.º 3 (mayo de 2022): 032802. http://dx.doi.org/10.1116/6.0001791.
Texto completoLai, Fu-Der, Jui-Ming Hua, C. Y. Huang, Fu-Hsiang Ko, L. A. Wang, C. H. Lin, C. M. Chang, S. Lee y Gia-Wei Chern. "ArF-line high transmittance attenuated phase shift mask blanks using amorphous Al2O3–ZrO2–SiO2 composite thin films for the 65-, 45- and 32-nm technology nodes". Thin Solid Films 496, n.º 2 (febrero de 2006): 247–52. http://dx.doi.org/10.1016/j.tsf.2005.08.382.
Texto completoKim, Youngbae, Shuai Li, Nandakishor Yadav y Kyuwon Ken Choi. "A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks". Electronics 10, n.º 17 (6 de septiembre de 2021): 2181. http://dx.doi.org/10.3390/electronics10172181.
Texto completoBilouk, Sabrina, Carole Pernel, Lucile Broussous, Valentina Ivanova y Ricardo Nogueira. "Electrochemical Behavior of Cobalt in Post-Via Etch Cleaning Solutions". Solid State Phenomena 145-146 (enero de 2009): 343–46. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.343.
Texto completoKang, Bong Kyun, Ji Hyun Jeong, Min Su Kim, Hong Seong Sohn, Ahmed A. Busnaina y Jin Goo Park. "Acoustic Cavitation Behavior in Isopropyl Alcohol Added Cleaning Solution". Solid State Phenomena 195 (diciembre de 2012): 169–72. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.169.
Texto completoGanesh, Chokkakula y Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell". Active and Passive Electronic Components 2023 (30 de junio de 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.
Texto completoItani, Toshiro. "157 nm Lithography for 70 nm Technology Node". Japanese Journal of Applied Physics 41, Part 1, No. 6B (30 de junio de 2002): 4033–36. http://dx.doi.org/10.1143/jjap.41.4033.
Texto completoPark, Joon-Min, Ilsin An y Hye-Keun Oh. "Resist Reflow Process for 32 nm Node Arbitrary Pattern". Japanese Journal of Applied Physics 48, n.º 4 (20 de abril de 2009): 046501. http://dx.doi.org/10.1143/jjap.48.046501.
Texto completoElangovan, M. y K. Gunavathi. "High Stable and Low Power 8T CNTFET SRAM Cell". Journal of Circuits, Systems and Computers 29, n.º 05 (2 de agosto de 2019): 2050080. http://dx.doi.org/10.1142/s0218126620500802.
Texto completoThornton, Trevor J., William Lepkowski y Seth J. Wilk. "Impact Ionization in SOI MESFETs at the 32-nm Node". IEEE Transactions on Electron Devices 63, n.º 10 (octubre de 2016): 4143–46. http://dx.doi.org/10.1109/ted.2016.2601241.
Texto completoPetrillo, Karen, Yayi Wei, R. Brainard, G. Denbeaux, Dario Goldfarb, C. S. Koay, J. Mackey et al. "Are extreme ultraviolet resists ready for the 32 nm node?" Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, n.º 6 (2007): 2490. http://dx.doi.org/10.1116/1.2787815.
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