Artículos de revistas sobre el tema "22-nm technology node"
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Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang y Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies". Electronics 11, n.º 11 (1 de junio de 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.
Texto completoXu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang y Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm". ECS Transactions 44, n.º 1 (15 de diciembre de 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.
Texto completoHolmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices". Journal of Micro/Nanolithography, MEMS, and MOEMS 9, n.º 1 (1 de enero de 2010): 013001. http://dx.doi.org/10.1117/1.3302125.
Texto completoBaklanov, Mikhail R., Evgeny A. Smirnov y Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond". ECS Transactions 35, n.º 4 (16 de diciembre de 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.
Texto completoSaxena, Shubhangi y Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node". ECS Transactions 107, n.º 1 (24 de abril de 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.
Texto completoHuang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan y Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology". Microelectronics Reliability 147 (agosto de 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.
Texto completoLi, Zongru, Christopher Elash, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Jiesi Xing, Shuting Shi, Zhi Wu Yang y Bharat L. Bhuva. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node". Microelectronics Reliability 146 (julio de 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.
Texto completoLu, Peng, Can Yang, Yifei Li, Bo Li y Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs". Eng 2, n.º 4 (3 de diciembre de 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.
Texto completoChanghwan Shin, Min Hee Cho, Yasumasa Tsukamoto, Bich-Yen Nguyen, Carlos Mazuré, Borivoje Nikolić y Tsu-Jae King Liu. "Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node". IEEE Transactions on Electron Devices 57, n.º 6 (junio de 2010): 1301–9. http://dx.doi.org/10.1109/ted.2010.2046070.
Texto completoShin, Changhwan, Nattapol Damrongplasit, Xin Sun, Yasumasa Tsukamoto, Borivoje Nikolic y Tsu-Jae King Liu. "Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node". IEEE Transactions on Electron Devices 58, n.º 7 (julio de 2011): 1846–54. http://dx.doi.org/10.1109/ted.2011.2139213.
Texto completoMah, Siew Kien, Pin Jern Ker, Ibrahim Ahmad, Noor Faizah Zainul Abidin y Mansur Mohammed Ali Gamel. "A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length". Materials 14, n.º 19 (30 de septiembre de 2021): 5721. http://dx.doi.org/10.3390/ma14195721.
Texto completoDuari, Chusen, Shilpi Birla y Amit Kumar Singh. "A Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability". Journal of Integrated Circuits and Systems 15, n.º 2 (31 de julio de 2020): 1–7. http://dx.doi.org/10.29292/jics.v15i2.140.
Texto completoMazurier, J., O. Weber, F. Andrieu, A. Toffoli, O. Thomas, F. Allain, J. P. Noel, M. Belleville, O. Faynot y T. Poiroux. "Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below". Journal of Low Power Electronics 8, n.º 1 (1 de febrero de 2012): 125–32. http://dx.doi.org/10.1166/jolpe.2012.1173.
Texto completoKarthikeyan, A. y P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review". Journal of Circuits, Systems and Computers 26, n.º 03 (21 de noviembre de 2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.
Texto completoValasa, Sresta, Shubham Tayal y Laxman Raju Thoutam. "Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node". ECS Journal of Solid State Science and Technology 11, n.º 4 (1 de abril de 2022): 041008. http://dx.doi.org/10.1149/2162-8777/ac6627.
Texto completoVerbitskiy, V. G., S. V. Voevodin, V. V. Fedulov, G. V. Kalistyi y D. O. Verbitskiy. "Manifestation of the channeling effect when manufacturing JFET transistors". Semiconductor Physics, Quantum Electronics and Optoelectronics 23, n.º 04 (19 de noviembre de 2020): 379–84. http://dx.doi.org/10.15407/spqeo23.04.379.
Texto completoKwon, Ah-Young, Ju-Yeon Jeong, Hyun Park, Sohyun Hwang, Gwangil Kim, Haeyoun Kang, Jin-Hyung Heo, Hye Jin Lee, Tae-Heon Kim y Hee Jung An. "miR-22-3p and miR-30e-5p Are Associated with Prognosis in Cervical Squamous Cell Carcinoma". International Journal of Molecular Sciences 23, n.º 10 (17 de mayo de 2022): 5623. http://dx.doi.org/10.3390/ijms23105623.
Texto completoKumar Rai, Mayank, Rajesh Khanna y Sankar Sarkar. "Control of tube parameters on SWCNT bundle interconnect delay and power dissipation". Microelectronics International 31, n.º 1 (20 de diciembre de 2013): 24–31. http://dx.doi.org/10.1108/mi-03-2013-0016.
Texto completoBoureau, Victor, Aurèle Durand, Patrice Gergaud, Delphine Le Cunff, Matthew Wormington, Denis Rouchon, Alain Claverie, Daniel Benoit y Martin Hÿtch. "Dark-field electron holography as a recording of crystal diffraction in real space: a comparative study with high-resolution X-ray diffraction for strain analysis of MOSFETs". Journal of Applied Crystallography 53, n.º 4 (18 de junio de 2020): 885–95. http://dx.doi.org/10.1107/s1600576720006020.
Texto completoMerad, Faiza y Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor". International Journal of Electrical and Computer Engineering (IJECE) 10, n.º 4 (1 de agosto de 2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.
Texto completoWu, Banqiu. "Next-generation lithography for 22 and 16 nm technology nodes and beyond". Science China Information Sciences 54, n.º 5 (mayo de 2011): 959–79. http://dx.doi.org/10.1007/s11432-011-4227-6.
Texto completoGanesh, Chokkakula y Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell". Active and Passive Electronic Components 2023 (30 de junio de 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.
Texto completoMcCants, Carl E. "The IARPA Circuit Analysis Tools Program". EDFA Technical Articles 15, n.º 4 (1 de noviembre de 2013): 52–54. http://dx.doi.org/10.31399/asm.edfa.2013-4.p052.
Texto completoSharma, Himanshu y Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects". Journal of Circuits, Systems and Computers 29, n.º 12 (5 de febrero de 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
Texto completoWang, Guilei, Qiang Xu, Tao Yang, Jinjuan Xiang, Jing Xu, Jianfeng Gao, Chunlong Li et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology". ECS Journal of Solid State Science and Technology 3, n.º 4 (2014): P82—P85. http://dx.doi.org/10.1149/2.015404jss.
Texto completoVeloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil y Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications". Japanese Journal of Applied Physics 50, n.º 4S (1 de abril de 2011): 04DC16. http://dx.doi.org/10.7567/jjap.50.04dc16.
Texto completoWang, G., Q. Xu, T. Yang, J. Luo, J. Xiang, J. Xu, G. Xu et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology". ECS Transactions 58, n.º 10 (31 de agosto de 2013): 317–24. http://dx.doi.org/10.1149/05810.0317ecst.
Texto completoVeloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil y Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications". Japanese Journal of Applied Physics 50, n.º 4 (20 de abril de 2011): 04DC16. http://dx.doi.org/10.1143/jjap.50.04dc16.
Texto completoZhao, Chun, C. Z. Zhao, M. Werner, S. Taylor y P. R. Chalker. "Advanced CMOS Gate Stack: Present Research Progress". ISRN Nanotechnology 2012 (9 de febrero de 2012): 1–35. http://dx.doi.org/10.5402/2012/689023.
Texto completoCui, Hushan, Jun Luo, Jing Xu, Jianfeng Gao, Jinjuan Xiang, Zhaoyun Tang, Xiaolei Wang et al. "Investigation of TaN as the wet etch stop layer for HKMG-last integration in the 22 nm and beyond nodes CMOS technology". Vacuum 119 (septiembre de 2015): 185–88. http://dx.doi.org/10.1016/j.vacuum.2015.05.021.
Texto completoVeloso, Anabela, Soon Aik Chew, Tom Schram, Harold Dekkers, Annemie Van Ammel, Thomas Witters, Hilde Tielens et al. "W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes". Japanese Journal of Applied Physics 52, n.º 4S (1 de abril de 2013): 04CA03. http://dx.doi.org/10.7567/jjap.52.04ca03.
Texto completoDAOUD, HOUDA, SAMIR BENSELEM, SONIA ZOUARI y MOURAD LOULOU. "USE OF ROBUST PREDICTIVE METHOD FOR NANO-CMOS PROCESS: APPLICATION TO BASIC BLOCK ANALOG CIRCUIT DESIGN". Journal of Circuits, Systems and Computers 21, n.º 07 (noviembre de 2012): 1250061. http://dx.doi.org/10.1142/s0218126612500612.
Texto completoChiu, H. Y., Y. K. Fang, T. H. Chou, Y. T. Chiang y C. I. Lin. "A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology". Semiconductor Science and Technology 22, n.º 10 (7 de septiembre de 2007): 1157–60. http://dx.doi.org/10.1088/0268-1242/22/10/013.
Texto completo"Ultra Low Dielectric Constant Materials for 22 nm Technology Node and beyond". ECS Meeting Abstracts, 2011. http://dx.doi.org/10.1149/ma2011-01/22/1407.
Texto completoLi, Zongru, Christopher Elash, Jiesi Xing, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Shuting Shi, Zhi Wu Yang y Bharat L. Bhuva. "SEU Performance of RHBD Flip-Flops Using Guard-Gates at 22-nm FDSOI Technology Node". IEEE Transactions on Nuclear Science, 2023, 1. http://dx.doi.org/10.1109/tns.2023.3284758.
Texto completoWang, Hanbin, Jinshun Bi, Jianhui Bu, Hainan Liu, Fazhan Zhao, Huajun Cao y Chao Ai. "Characteristics of 22 nm UTBB-FDSOI technology with an ultra-wide temperature range". Semiconductor Science and Technology, 4 de agosto de 2022. http://dx.doi.org/10.1088/1361-6641/ac86ec.
Texto completoWang, Guilei, Jun Luo, Jinbiao Liu, Tao Yang, Yefeng Xu, Junfeng Li, Huaxiang Yin et al. "pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology". Nanoscale Research Letters 12, n.º 1 (26 de abril de 2017). http://dx.doi.org/10.1186/s11671-017-2080-2.
Texto completoSharma, Vijay Kumar. "A Survey on Low Power Design Approaches in nanoscale regime". Micro and Nanosystems 12 (23 de junio de 2020). http://dx.doi.org/10.2174/1876402912999200623120558.
Texto completoBarik, Rasmita, Rudra Sankar Dhar, Falah Awwad y Mousa I. Hussein. "Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances". Scientific Reports 13, n.º 1 (14 de julio de 2023). http://dx.doi.org/10.1038/s41598-023-38239-x.
Texto completoYin, Zihan, Md Abdullah-Al Kaiser, Lamine Ousmane Camara, Mark Camarena, Maryam Parsa, Ajey Jacob, Gregory Schwartz y Akhilesh Jaiswal. "IRIS: Integrated Retinal Functionality in Image Sensors". Frontiers in Neuroscience 17 (1 de septiembre de 2023). http://dx.doi.org/10.3389/fnins.2023.1241691.
Texto completoDobbie, Andy, Maksym Myronov, Xue-Chao Liu, Van Huy Nguyen, Evan Parker y David Leadley. "Investigation of the Thermal Stability of Strained Ge Layers Grown at Low Temperature by Reduced-pressure Chemical Vapour Deposition on Si0.2Ge0.8 Relaxed Buffers". MRS Proceedings 1252 (2010). http://dx.doi.org/10.1557/proc-1252-i04-06.
Texto completoTang, Guangzhi, Kanishkan Vadivel, Yingfu Xu, Refik Bilgic, Kevin Shidqi, Paul Detterer, Stefano Traferro et al. "SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges". Frontiers in Neuroscience 17 (23 de junio de 2023). http://dx.doi.org/10.3389/fnins.2023.1187252.
Texto completoAyush, Poornima Mittal y Rajesh Rohilla. "Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM". ACM Transactions on Design Automation of Electronic Systems, 2 de agosto de 2023. http://dx.doi.org/10.1145/3611672.
Texto completoLetertre, Fabrice Jerome. "Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology". MRS Proceedings 1068 (2008). http://dx.doi.org/10.1557/proc-1068-c01-01.
Texto completoMoreau, Stephane, Fré;déric Gaillard, Jean-Charles Barbé, Raphaël Gras, Gérard Passemard y Joaquin Torres. "Mechanical Integrity Study of Air Gap Structures Assisted by FE Simulations". MRS Proceedings 1079 (2008). http://dx.doi.org/10.1557/proc-1079-n02-02.
Texto completo"Application of Atomic Layer Deposition Tungsten (ALD W) as gate filling metal for 22 nm and beyond nodes CMOS technology". ECS Meeting Abstracts, 2013. http://dx.doi.org/10.1149/ma2013-02/24/1890.
Texto completoDhillon, Gurleen y Karmjit Singh Sandha. "Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes". Journal of Circuits, Systems and Computers 31, n.º 05 (10 de noviembre de 2021). http://dx.doi.org/10.1142/s0218126622500980.
Texto completo"Two-Dimensional Chemical Delineation of Junction Profile with High Spatial Resolution and Application in Failure Analysis in 65 nm Technology Node". ECS Meeting Abstracts, 2009. http://dx.doi.org/10.1149/ma2009-02/22/1988.
Texto completoSmaani, Billel, Neha Paras, Shiromani Balmukund Rahi, Young Suh Song, Ramakant Yadav y Shubham Tayal. "Impact of the Self-Heating Effect on Nanosheet Field Effect Transistor Performance". ECS Journal of Solid State Science and Technology, 6 de febrero de 2023. http://dx.doi.org/10.1149/2162-8777/acb96b.
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