Bibliografías temáticas / 22-nm technology node

Literatura académica sobre el tema "22-nm technology node"

Autor: Grafiati
Publicado: 6 de septiembre de 2023

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Artículos de revistas sobre el tema "22-nm technology node"

1

Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang y Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies". Electronics 11, n.º 11 (1 de junio de 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.
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Xu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang y Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm". ECS Transactions 44, n.º 1 (15 de diciembre de 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.

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Holmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices". Journal of Micro/Nanolithography, MEMS, and MOEMS 9, n.º 1 (1 de enero de 2010): 013001. http://dx.doi.org/10.1117/1.3302125.

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Baklanov, Mikhail R., Evgeny A. Smirnov y Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond". ECS Transactions 35, n.º 4 (16 de diciembre de 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.

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Saxena, Shubhangi y Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node". ECS Transactions 107, n.º 1 (24 de abril de 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new materials and devices hold promise as potential device candidates to be integrated onto the silicon platform to enhance semiconductor industry growth and extend Moore's Law. Here we address state–of–the–art research trends in nanomaterials and nanodevices for future technology node and discuss associated challenges.
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Huang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan y Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology". Microelectronics Reliability 147 (agosto de 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.

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Li, Zongru, Christopher Elash, Chen Jin, Li Chen, Shi-Jie Wen, Rita Fung, Jiesi Xing, Shuting Shi, Zhi Wu Yang y Bharat L. Bhuva. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node". Microelectronics Reliability 146 (julio de 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.

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Lu, Peng, Can Yang, Yifei Li, Bo Li y Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs". Eng 2, n.º 4 (3 de diciembre de 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.

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The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.
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Changhwan Shin, Min Hee Cho, Yasumasa Tsukamoto, Bich-Yen Nguyen, Carlos Mazuré, Borivoje Nikolić y Tsu-Jae King Liu. "Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node". IEEE Transactions on Electron Devices 57, n.º 6 (junio de 2010): 1301–9. http://dx.doi.org/10.1109/ted.2010.2046070.

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Shin, Changhwan, Nattapol Damrongplasit, Xin Sun, Yasumasa Tsukamoto, Borivoje Nikolic y Tsu-Jae King Liu. "Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node". IEEE Transactions on Electron Devices 58, n.º 7 (julio de 2011): 1846–54. http://dx.doi.org/10.1109/ted.2011.2139213.

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Tesis sobre el tema "22-nm technology node"

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Bansal, Anil Kumar. "CMOS scaling considerations in sub 10-nm node multiple-gate FETS". Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8046.

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Libros sobre el tema "22-nm technology node"

1

Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6.

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Wang, Guilei. Investigation on Sige Selective Epitaxy for Source and Drain Engineering in 22 Nm CMOS Technology Node and Beyond. Springer Singapore Pte. Limited, 2020.

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer, 2019.

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4

Balasinski, Artur. Design for Manufacturability: From 1d to 4D for 90 22 NM Technology Nodes. Springer New York, 2016.

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5

Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90–22 nm Technology Nodes. Springer, 2013.

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6

Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90-22 Nm Technology Nodes. Springer London, Limited, 2013.

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Capítulos de libros sobre el tema "22-nm technology node"

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Wang, Guilei. "Strained Silicon Technology". En Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 9–21. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_2.

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Kaur, Ravneet, Charu Madhu y Deepti Singh. "Impact of Buried Oxide Layer Thickness on the Performance Parameters of SOI FinFET at 22 nm Node Technology". En Advances in Intelligent Systems and Computing, 537–44. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_54.

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Wang, Guilei. "Introduction". En Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 1–7. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_1.

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Wang, Guilei. "Epitaxial Growth of SiGe Thin Films". En Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 23–48. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_3.

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5

Wang, Guilei. "SiGe S/D Integration and Device Verification". En Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 49–92. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_4.

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Wang, Guilei. "Pattern Dependency of SiGe Layers Selective Epitaxy Growth". En Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 93–111. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_5.

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Wang, Guilei. "Conclusions and Prospects". En Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 113–15. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_6.

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8

Yin, Huaxiang y Jiaxin Yao. "Advanced Transistor Process Technology from 22- to 14-nm Node". En Complementary Metal Oxide Semiconductor. InTech, 2018. http://dx.doi.org/10.5772/intechopen.78655.

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Actas de conferencias sobre el tema "22-nm technology node"

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Gambino, J. P. "Copper interconnect technology for the 22 nm node". En 2011 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2011. http://dx.doi.org/10.1109/vtsa.2011.5872228.

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Finders, Jo, Mircea Dusa, Jan Mulkens, Yu Cao y Maryana Escalante. "Solutions for 22-nm node patterning using ArFi technology". En SPIE Advanced Lithography. SPIE, 2011. http://dx.doi.org/10.1117/12.881598.

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Kazuya Ohuchi, Christian Lavoie, Conal E. Murray, Chris P. D'Emic, Isaac Lauer, Jack O. Chu, Bin Yang et al. "Extendibility of NiPt silicide to the 22-nm node CMOS technology". En 2008 International Workshop on Junction Technology (IWJT). IEEE, 2008. http://dx.doi.org/10.1109/iwjt.2008.4540037.

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4

Kim, Ryoung-Han, Steven Holmes, Scott Halle, Vito Dai, Jason Meiring, Aasutosh Dave, Matthew E. Colburn y Harry J. Levinson. "22 nm technology node active layer patterning for planar transistor devices". En SPIE Advanced Lithography, editado por Harry J. Levinson y Mircea V. Dusa. SPIE, 2009. http://dx.doi.org/10.1117/12.814277.

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5

Zhou, Renjie, Gabriel Popescu y Lynford L. Goddard. "Finding defects in a 22 nm node wafer with visible light". En CLEO: Applications and Technology. Washington, D.C.: OSA, 2013. http://dx.doi.org/10.1364/cleo_at.2013.af2j.2.

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6

Agarwal, Vivek Kumar, Manisha Guduri y Aminul Islam. "Power and variability analysis of CMOS logic families @ 22-nm technology node". En 2014 3rd International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions). IEEE, 2014. http://dx.doi.org/10.1109/icrito.2014.7014674.

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Roy, Chandaramauleshwar y Aminul Islam. "Comparative analysis of various 9T SRAM cell at 22-nm technology node". En 2015 IEEE 2nd International Conference on Recent Trends in Information Systems (ReTIS). IEEE, 2015. http://dx.doi.org/10.1109/retis.2015.7232929.

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Gallitre, M., L. G. Gosset, A. Farcy, B. Blampey, R. Gras, C. Bermond, B. Flechet y J. Torres. "Performance predictions of prospective air gap architectures for the 22 nm node". En 2007 IEEE International Interconnect Technology Conferencee. IEEE, 2007. http://dx.doi.org/10.1109/iitc.2007.382374.

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Lu, Hai-Jin, Zong-Yan Pan, Pei-Yu Chen, Zhi-Cheng Zhang y Ming-Zhi Chen. "Optimization of contact W related processes for 28/22 nm HKMG technology node". En 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2021. http://dx.doi.org/10.1109/edtm50988.2021.9420977.

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Colombeau, B., T. Thanigaivelan, E. Arevalo, T. Toh, R. Miura y H. Ito. "Ultra-shallow Carborane molecular implant for 22-nm node p-MOSFET performance boost". En 2009 International Workshop on Junction Technology (IWJT). IEEE, 2009. http://dx.doi.org/10.1109/iwjt.2009.5166211.

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