Artículos de revistas sobre el tema "10T SRAM CELL"
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Elangovan, M. y K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell". Journal of Circuits, Systems and Computers 29, n.º 10 (19 de diciembre de 2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.
Texto completoReddy Gujjula, Nagarjuna y Rameshbabu Kellampalli. "Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor". International Journal of Scientific Methods in Engineering and Management 01, n.º 01 (2023): 47–57. http://dx.doi.org/10.58599/ijsmem.2023.1105.
Texto completoGanesh, Chokkakula y Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell". Active and Passive Electronic Components 2023 (30 de junio de 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.
Texto completoRao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak y Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications". Journal of Electrical and Computer Engineering 2023 (7 de junio de 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.
Texto completoIslam, A. y M. Hasan. "Leakage Characterization of 10T SRAM Cell". IEEE Transactions on Electron Devices 59, n.º 3 (marzo de 2012): 631–38. http://dx.doi.org/10.1109/ted.2011.2181387.
Texto completoChaurasia, Ranu, Brijesh Kumar, Sudhanshu Verma y Akhilesh Kumar. "Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques". IOP Conference Series: Materials Science and Engineering 1272, n.º 1 (1 de diciembre de 2022): 012007. http://dx.doi.org/10.1088/1757-899x/1272/1/012007.
Texto completoLiu, Changjun, Hongxia Liu y Jianye Yang. "A Novel Low-Power and Soft Error Recovery 10T SRAM Cell". Micromachines 14, n.º 4 (13 de abril de 2023): 845. http://dx.doi.org/10.3390/mi14040845.
Texto completoZhou, Hong Gang, Qiang Song, Chun Yu Peng y Shou Biao Tan. "A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture". Applied Mechanics and Materials 263-266 (diciembre de 2012): 9–14. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.9.
Texto completoSingh, Arjun y Sangeeta Nakhte. "Optimized High Performance 10T SRAM Cell Characterization". International Journal of Computer Applications 134, n.º 5 (15 de enero de 2016): 29–33. http://dx.doi.org/10.5120/ijca2016907964.
Texto completoGupta, Neha, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl y Patrick Girard. "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications". Electronics 10, n.º 14 (17 de julio de 2021): 1718. http://dx.doi.org/10.3390/electronics10141718.
Texto completoShah, Ambika Prasad y Michael Waltl. "Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell". Electronics 9, n.º 2 (3 de febrero de 2020): 256. http://dx.doi.org/10.3390/electronics9020256.
Texto completoAparna y Ram Chandra Singh Chauhan. "Low Power PPN inverter based 10T SRAM Cell". Indian Journal of Science and Technology 14, n.º 20 (25 de mayo de 2021): 1699–710. http://dx.doi.org/10.17485/ijst/v14i20.400.
Texto completoSharma, Neha y Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS". International Journal of Modeling, Simulation, and Scientific Computing 12, n.º 04 (9 de marzo de 2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.
Texto completoLakshmi, T. Venkata, T. Edukondalu, S. Rahul, R. S. P. L. Suvarna y T. Rohit Chaitanya. "A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS". International Journal for Research in Applied Science and Engineering Technology 11, n.º 4 (30 de abril de 2023): 714–21. http://dx.doi.org/10.22214/ijraset.2023.50158.
Texto completoZhou, Hong Gang, Shou Biao Tan, Qiang Song y Chun Yu Peng. "A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS". Applied Mechanics and Materials 373-375 (agosto de 2013): 1607–11. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.1607.
Texto completoLeavline, Epiphany Jebamalar y Arumugam Sugantha. "Reliability improved dual driven feedback 10T SRAM bit cell". Microelectronics Reliability 139 (diciembre de 2022): 114804. http://dx.doi.org/10.1016/j.microrel.2022.114804.
Texto completoAhmad, Sayeed, Naushad Alam y Mohd Hasan. "A Robust 10T SRAM Cell with Enhanced Read Operation". International Journal of Computer Applications 129, n.º 2 (17 de noviembre de 2015): 7–12. http://dx.doi.org/10.5120/ijca2015906751.
Texto completoLimachia, Mitesh Jethabhai, Rajesh A. Thakker y Nikhil J. Kothari. "Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology". Circuit World 44, n.º 4 (5 de noviembre de 2018): 187–94. http://dx.doi.org/10.1108/cw-01-2018-0002.
Texto completoJoshi, Shital y Umar Alabawi. "Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM". Journal of Nanotechnology 2017 (2017): 1–9. http://dx.doi.org/10.1155/2017/4575013.
Texto completoMansore, S. R. y Amit Naik. "Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell". Journal of VLSI Design and Signal Processing 8, n.º 3 (16 de noviembre de 2022): 18–22. http://dx.doi.org/10.46610/jovdsp.2022.v08i03.003.
Texto completoBhanuchandar, R., B. Harikrishna y Suman Mishra. "10T Sram cell designusing single ended decoupled read bit line". Indian Journal of Public Health Research & Development 9, n.º 11 (2018): 2081. http://dx.doi.org/10.5958/0976-5506.2018.01757.6.
Texto completoShah, Ambika Prasad, Santosh Kumar Vishvakarma y Michael Hübner. "Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications". Journal of Electronic Testing 36, n.º 2 (6 de marzo de 2020): 255–69. http://dx.doi.org/10.1007/s10836-020-05864-7.
Texto completoManikandan, A. "Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures". Journal of Electronics,Computer Networking and Applied Mathematics, n.º 22 (26 de marzo de 2022): 29–39. http://dx.doi.org/10.55529/jecnam.22.29.39.
Texto completoYao, Ruxue, Hongliang Lv, Yuming Zhang, Xu Chen, Yutao Zhang, Xingming Liu y Geng Bai. "A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications". Micromachines 14, n.º 7 (25 de junio de 2023): 1305. http://dx.doi.org/10.3390/mi14071305.
Texto completoMuthusamy, Parimaladevi y Sharmila Dhandapani. "Leakage Characterization of a Novel Transmission Gate based 10T SRAM Cell". Asian Journal of Research in Social Sciences and Humanities 6, n.º 7 (2016): 844. http://dx.doi.org/10.5958/2249-7315.2016.00469.x.
Texto completoKumar, C. I. y B. Anand. "Design of highly reliable energy‐efficient SEU tolerant 10T SRAM cell". Electronics Letters 54, n.º 25 (diciembre de 2018): 1423–24. http://dx.doi.org/10.1049/el.2018.7267.
Texto completoFeki, Anis, Bruno Allard, David Turgis, Jean-Christophe Lafont, Faress Tissafi Drissi, Fady Abouzeid y Sebastien Haendler. "Sub-threshold 10T SRAM bit cell with read/write XY selection". Solid-State Electronics 106 (abril de 2015): 1–11. http://dx.doi.org/10.1016/j.sse.2014.11.018.
Texto completoSudha, D., Ch Santhi Rani y Sreenivasa Rao Ijjada. "SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects". Acta Physica Polonica A 135, n.º 4 (abril de 2019): 702–4. http://dx.doi.org/10.12693/aphyspola.135.702.
Texto completoMansore, S. R., R. S. Gamad y D. K. Mishra. "A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability". Journal of Circuits, Systems and Computers 29, n.º 05 (1 de julio de 2019): 2050067. http://dx.doi.org/10.1142/s021812662050067x.
Texto completoKiran, PN Vamsi y Nikhil Saxena. "Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed". International Journal of Hybrid Information Technology 9, n.º 2 (28 de febrero de 2016): 111–22. http://dx.doi.org/10.14257/ijhit.2016.9.2.10.
Texto completoRahman Aura, Shourin, S. M. Ishraqul Huq y Satyendra N. Biswas. "Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature". International journal of electrical and computer engineering systems 13, n.º 9 (6 de diciembre de 2022): 823–29. http://dx.doi.org/10.32985/ijeces.13.9.11.
Texto completoShakouri, Erfan, Behzad Ebrahimi, Nima Eslami y Mohammad Chahardori. "Single-Ended 10T SRAM Cell with High Yield and Low Standby Power". Circuits, Systems, and Signal Processing 40, n.º 7 (11 de enero de 2021): 3479–99. http://dx.doi.org/10.1007/s00034-020-01636-y.
Texto completoDohar, Suraj Singh, Siddharth R. K., Vasantha M. H. y Nithin Kumar Y. B. "A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application". IEEE Transactions on Electron Devices 68, n.º 5 (mayo de 2021): 2265–70. http://dx.doi.org/10.1109/ted.2021.3064899.
Texto completoDolatshah, Amir, Erfan Abbasian, Maryam Nayeri y Sobhan Sofimowloodi. "A sub-threshold 10T FinFET SRAM cell design for low-power applications". AEU - International Journal of Electronics and Communications 157 (diciembre de 2022): 154417. http://dx.doi.org/10.1016/j.aeue.2022.154417.
Texto completoMANSORE, Shivram y Radheshyam GAMAD. "A data-aware write-assist 10T SRAM cell with bit-interleaving capability". TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 26, n.º 5 (28 de septiembre de 2018): 2361–73. http://dx.doi.org/10.3906/elk-1801-272.
Texto completoJahinuzzaman, Shah M., David J. Rennie y Manoj Sachdev. "A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability". IEEE Transactions on Nuclear Science 56, n.º 6 (diciembre de 2009): 3768–73. http://dx.doi.org/10.1109/tns.2009.2032090.
Texto completoAbbasian, Erfan, Farzaneh Izadinasab y Morteza Gholipour. "A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins". IEEE Transactions on Circuits and Systems I: Regular Papers 69, n.º 4 (abril de 2022): 1606–16. http://dx.doi.org/10.1109/tcsi.2021.3138849.
Texto completoSachdeva, Ashish y V. K. Tomar. "Design of 10T SRAM cell with improved read performance and expanded write margin". IET Circuits, Devices & Systems 15, n.º 1 (15 de diciembre de 2020): 42–64. http://dx.doi.org/10.1049/cds2.12006.
Texto completoShirode, Ujwal R., Rajendra D. Kanphade y Ajjay S. Gaadhe. "Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node". Key Engineering Materials 945 (19 de mayo de 2023): 41–46. http://dx.doi.org/10.4028/p-73f387.
Texto completoKrishna, R. y Punithavathi Duraiswamy. "Low leakage 10T SRAM cell with improved data stability in deep sub-micron technologies". Analog Integrated Circuits and Signal Processing 109, n.º 1 (6 de mayo de 2021): 153–63. http://dx.doi.org/10.1007/s10470-021-01870-7.
Texto completoBansal, Saloni y V. K. Tomar. "Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices". IOP Conference Series: Materials Science and Engineering 1116, n.º 1 (1 de abril de 2021): 012111. http://dx.doi.org/10.1088/1757-899x/1116/1/012111.
Texto completoLo, Cheng-Hung y Shi-Yu Huang. "P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation". IEEE Journal of Solid-State Circuits 46, n.º 3 (marzo de 2011): 695–704. http://dx.doi.org/10.1109/jssc.2010.2102571.
Texto completoFuketa, Hiroshi, Masanori Hashimoto, Yukio Mitsuyama y Takao Onoye. "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM". IEEE Transactions on Nuclear Science 58, n.º 4 (agosto de 2011): 2097–102. http://dx.doi.org/10.1109/tns.2011.2159993.
Texto completoHarada, R., S. Abe, H. Fuketa, T. Uemura, M. Hashimoto y Y. Watanabe. "Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM". IEEE Transactions on Nuclear Science 59, n.º 6 (diciembre de 2012): 2791–95. http://dx.doi.org/10.1109/tns.2012.2224373.
Texto completoEslami, Nima, Behzad Ebrahimi, Erfan Shakouri y Deniz Najafi. "A single-ended low leakage and low voltage 10T SRAM cell with high yield". Analog Integrated Circuits and Signal Processing 105, n.º 2 (8 de junio de 2020): 263–74. http://dx.doi.org/10.1007/s10470-020-01669-y.
Texto completoSheu, Ming-Hwa, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin y Jin-Fa Lin. "A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications". Sensors 21, n.º 19 (2 de octubre de 2021): 6591. http://dx.doi.org/10.3390/s21196591.
Texto completoSHIBATA, Nobutaro, Yoshinori GOTOH y Takako ISHIHARA. "A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications". IEICE Transactions on Electronics E99.C, n.º 6 (2016): 717–26. http://dx.doi.org/10.1587/transele.e99.c.717.
Texto completoUpadhyay, Prashant, Rajib Kar, Durbadal Mandal y Sakti Prasad Ghoshal. "Characteristic analysis of a novel low power 10T SRAM cell during read and write operations". International Journal of Computer Aided Engineering and Technology 7, n.º 4 (2015): 496. http://dx.doi.org/10.1504/ijcaet.2015.072603.
Texto completoSable, Varun y Shyam Akashe. "Noise Voltage Apportioned a New Reliability Concern in Low Power 10T SRAM Cell Using FinFET Device". Journal of Nanoelectronics and Optoelectronics 10, n.º 6 (1 de diciembre de 2015): 745–48. http://dx.doi.org/10.1166/jno.2015.1833.
Texto completoSable, et al., Varun. "Static Noise Margin Enhanced in FinFET Based 10T SRAM Cell at 45 nm using EDA Tool". International Journal of Computing and Digital Systemss 5, n.º 6 (1 de noviembre de 2016): 451–56. http://dx.doi.org/10.12785/ijcds/050603.
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